The MAX8667/MAX8668 dual step-down converters
with dual low-dropout (LDO) linear regulators are
intended to power low-voltage microprocessors or
DSPs in portable devices. They feature high efficiency
with small external component size. The step-down
converters are adjustable from 0.6V to 3.3V (MAX8668)
or factory preset (MAX8667) with guaranteed output
current of 600mA for OUT1 and 1200mA for OUT2. The
1.5MHz hysteretic-PWM control scheme allows for tiny
external components and reduces no-load operating
current to 100µA with all outputs enabled. Dual low-quiescent-current, low-noise LDOs operate down to 1.7V
supply voltage. The MAX8667/MAX8668 have individual enables for each output, maximizing flexibility.
The MAX8667/MAX8668 are available in the spacesaving, 3mm x 3mm, 16-pin thin QFN package.
600mA Guaranteed Output Current on OUT1
1200mA Guaranteed Output Current on OUT2
Tiny Size 2.2µH Chip Inductor (0805)
Output Voltage from 0.6V to 3.3V (MAX8668)
Ultra-Fast Line and Load Transients
Low 25µA Supply Current Each
♦ LDOs
300mA Guaranteed
Low 1.7V Minimum Supply Voltage
Low Output Noise
MAX8667/MAX8668
1.5MHz Dual Step-Down DC-DC Converters
with Dual LDOs and Individual Enables
= 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN12, IN34, FB1, FB2, EN1, EN2, EN3, EN4, OUT1,
OUT2, REF to GND............................................-0.3V to +6.0V
OUT3,
OUT4 to GND.....-0.3V to the lesser of + 6V or (V
IN34
+ 0.3V)
PGND1, PGND2 to GND .......................................-0.3V to +0.3V
LX1, LX2 Current ..........................................................1.5A RMS
LX1, LX2 to GND (Note 1) .......................-0.3V to (V
7REFREFReference Output. Bypass REF with a 0.01µF ceramic capacitor to GND.
8OUT2—Feedback Input for Regulator 2. Connect OUT2 directly to the output of step-down regulator 2.
9PGND2PGND2Power Ground for Step-Down Regulator 2
10LX2LX2Inductor Connection for Regulator 2
11IN12IN12
12LX1LX1Inductor Connection for Regulator 1
13PGND1PGND1Power Ground for Step-Down Regulator 1
14OUT1—Feed b ack Inp ut for Reg ul ator 1. C onnect OU T1 d i r ectl y to the outp ut of step - d ow n r eg ul ator 1.
15EN1EN1
16EN2EN2
—EPEPExposed Paddle. Connect to GND, PGND1, PGND2, and circuit ground.
NAME
—FB2
—FB1
Enable Input for Regulator 3. Drive EN3 high or connect to IN34 to turn on regulator 3. Drive low
to turn off regulator 3 and reduce input quiescent current.
Output of Regulator 3. Bypass OUT3 with a 4.7µF ceramic capacitor to GND. OUT3 is
discharged to GND through an internal 1kΩ in shutdown.
Input Voltage for LDO Regulators 3 and 4. Supply voltage range is from 1.7V to 5.5V. This
supply voltage must not exceed V
to ground.
Output of Regulator 4. Bypass OUT4 with a 4.7µF ceramic capacitor to GND. OUT4 is
discharged to GND through an internal 1kΩ in shutdown.
Enable Input for Regulator 4. Drive EN4 high or connect to IN34 to turn on regulator 4. Drive low
to turn off regulator 4 and reduce input quiescent current.
Feedback Input for Regulator 2. Connect FB2 to the center of a resistor feedback divider
between the output of regulator 2 and ground to set the output voltage. See the Setting theOutput Voltages and Voltage Positioning section.
Input Voltage for Step-Down Regulators 1 and 2. Supply voltage range is from 2.6V to 5.5V. This
supply voltage must not be less than V
IN12 to ground.
Feedback Input for Regulator 1. Connect FB1 to the center of a resistor feedback divider
between the output of regulator 1 and ground to set the output voltage. See the Setting theOutput Voltages and Voltage Positioning section.
E nab l e Inp ut for Reg ul ator 1. D r i ve E N 1 hi g h or connect to IN 12 to tur n on step - d ow n r eg ul ator 1.
D r i ve l ow to tur n off the r eg ul ator and r ed uce i np ut q ui escent cur r ent.
E nab l e Inp ut for Reg ul ator 2. D r i ve E N 2 hi g h or connect to IN 12 to tur n on step - d ow n r eg ul ator 2.
D r i ve l ow to tur n off the r eg ul ator and r ed uce i np ut q ui escent cur r ent.
FUNCTION
. Connect a 4.7µF or larger ceramic capacitor from IN34
IN12
. Connect a 10µF or larger ceramic capacitor from
IN34
MAX8667/MAX8668
1.5MHz Dual Step-Down DC-DC Converters
with Dual LDOs and Individual Enables
The MAX8667/MAX8668 dual step-down converters
with dual low-dropout (LDO) linear regulators are
intended to power low-voltage microprocessors or
DSPs in portable devices. They feature high efficiency
with small external component size. The step-down outputs are adjustable from 0.6V to 3.3V (MAX8668) or
factory preset (MAX8667) with guaranteed output current of 600mA for OUT1 and 1200mA for OUT2. The
1.5MHz hysteretic-PWM control scheme allows for tiny
external components and reduces no-load operating
current to 100µA (typ) with all regulators enabled. Dual,
low-quiescent-current, low-noise LDOs operate down to
1.7V supply voltage. The MAX8667/MAX8668 have
individual enable inputs for each output to facilitate any
supply sequencing.
Step-Down DC-DC Regulators
(OUT1, OUT2)
Step-Down Regulator Architecture
The MAX8667/MAX8668 step-down regulators are optimized for high-efficiency voltage conversion over a
wide load range, while maintaining excellent transient
response, minimizing external component size, and
minimizing output voltage ripple. The DC-DC converters (OUT1, OUT2) also feature an optimized on-resistance internal MOSFET switch and synchronous
rectifier to maximize efficiency. The MAX8667/
MAX8668 utilize a proprietary hysteretic-PWM control
scheme that switches with nearly fixed frequency at up
to 1.5MHz allowing for ultra-small external components.
The step-down converter output current is guaranteed
up to 600mA for OUT1 and 1200mA for OUT2.
When the step-down converter output voltage falls below
the regulation threshold, the error comparator begins a
switching cycle by turning the high-side p-channel
MOSFET switch on. This switch remains on until the minimum on-time (t
ON
) expires and the output voltage is in
regulation or the current-limit threshold (I
LIMP_
) is
exceeded. Once off, the high-side switch remains off
until the minimum off-time (t
OFF
) expires and the output
voltage again falls below the regulation threshold.
During this off period, the low-side synchronous rectifier turns on and remains on until either the high-side
switch turns on or the inductor current reduces to the
rectifier-off current threshold (I
LXOFF
= 60mA typ). The
internal synchronous rectifier eliminates the need for an
external Schottky diode.
Input Supply and Undervoltage Lockout
The input voltage range of step-down regulators OUT1
and OUT2 is 2.6V to 5.5V. This supply voltage must be
greater than or equal to the LDO supply voltage (V
IN34
).
A UVLO circuit prevents step-down regulators OUT1
and OUT2 from switching when the supply voltage is
too low to guarantee proper operation. When V
IN12
falls
below 2.4V (typ), OUT1 and OUT2 are shut down.
OUT1 and OUT2 turn on and begin soft-start when
V
IN12
rises above 2.5V (typ).
Soft-Start
When initially powered up, or enabled with EN_, the
step-down regulators soft-start by gradually ramping
up the output voltage. This reduces inrush current during startup. See the startup waveforms in the
Typical
Operating Characteristics
section.
Current Limit
The MAX8667/MAX8668 limit the peak inductor current
of the p-channel MOSFET (I
LIMP_
). A valley current limit
is used to protect the step-down regulators during
severe overload and output short-circuit conditions.
When the peak current limit is reached, the internal
p-channel MOSFET turns off and remains off until the
output drops below regulation, the inductor current falls
below the valley current-limit threshold, and the minimum off-time has expired.
Voltage Positioning
The OUT1 and OUT2 output voltages and voltage positioning of the MAX8668 are set by a resistor network
connected to FB_. With this configuration, a portion of
the feedback signal is sensed on the switched side of
the inductor, and the output voltage droops slightly as
the load current is increased due to the DC resistance
of the inductor. This output voltage droop is known as
voltage positioning. Voltage positioning allows the load
regulation to be set to match the voltage droop during
a load transient, reducing the peak-to-peak output voltage deviation during a load transient, and reducing the
output capacitance requirements.
Dropout
As the input voltage approaches the output voltage, the
duty cycle of the p-channel MOSFET reaches 100%. In
this state, the p-channel MOSFET is turned on constantly (not switching), and the dropout voltage is the
voltage drop due to the output current across the onresistance of the internal p-channel MOSFET (R
PCH
)
and the inductor’s DC resistance (R
L
):
LDO Linear Regulators (OUT3, OUT4)
The MAX8667/MAX8668 contain two low-dropout linear
regulators (LDOs), OUT3 and OUT4. The LDO output
voltages are factory preset, and each LDO supplies
VI R R
=+
DOLOAD PCHL
()
MAX8667/MAX8668
1.5MHz Dual Step-Down DC-DC Converters
with Dual LDOs and Individual Enables
loads up to 300mA. The LDOs include an internal reference, error amplifier, p-channel pass transistor, and
internal voltage-dividers. Each error amplifier compares
the reference voltage to the output voltage (divided by
the internal voltage-divider) and amplifies the difference. If the divided feedback voltage is lower than the
reference voltage, the pass-transistor gate is pulled
lower, allowing more current to pass to the outputs and
increasing the output voltage. If the divided feedback
voltage is too high, the pass-transistor gate is pulled
up, allowing less current to pass to the output.
Input Supply and Undervoltage Lockout
The input voltage range of LDO regulators OUT3 and
OUT4 is 1.7V to 5.5V. This supply voltage must be less
than or equal to the voltage applied to IN12 (V
IN34
≤
V
IN12
).
An undervoltage lockout circuit turns off the LDO regulators when the input supply voltage is too low to guarantee
proper operation. When V
IN34
falls below 1.5V (typ),
OUT3 and OUT4 are shut down. OUT3 and OUT4 turn
on and begin soft-start when V
IN34
rises above 1.6V (typ).
Soft-Start
When initially powered up, or enabled with EN_, the
LDOs soft-start by gradually ramping up the output
voltage. This reduces inrush current during startup. The
soft-start ramp time is typically 100µs from the start of
the soft-start ramp to the output reaching its nominal
regulation voltage.
Current Limit
The OUT3 and OUT4 output current is limited to 375mA
(min). If the output current exceeds the current limit, the
corresponding LDO output voltage drops.
Dropout
The maximum dropout voltage for the linear regulators
is 250mV at 300mA load. To avoid dropout, make sure
the IN34 supply voltage is at least 250mV higher than
the highest LDO output voltage.
Thermal-Overload Protection
Thermal-overload protection limits the total power dissipation in the MAX8667/MAX8668. Thermal-protection
circuits monitor the die temperature. If the die temperature exceeds +160°C, the IC is shut down, allowing the
IC to cool. Once the IC has cooled by 15°C, the IC is
enabled again. This results in a pulsed output during
continuous thermal-overload conditions. The thermaloverload protection protects the MAX8667/MAX8668 in
the event of fault conditions. For continuous operation,
do not exceed the absolute maximum junction temperature of +150°C. See the
Thermal Considerations
sec-
tion for more information.
Figure 2. Timing Diagram
IN12
ENx
OUTx
ENy
OUTy
t
IS THE PERIOD REQUIRED TO ENABLE FROM SHUTDOWN
PWRON
t
PWRON
tEN IS THE ENABLE TIME FOR SUBSEQUENT ENABLE
SIGNALS FOLLOWING THE FIRST ENABLE
t
EN
ENx, ENy ARE ANY COMBINATION OF EN1–EN4.
MAX8667/MAX8668
1.5MHz Dual Step-Down DC-DC Converters
with Dual LDOs and Individual Enables
The LDO output voltages of the MAX8667/MAX8668,
and the step-down outputs of the MAX8667 are factory
preset. See the
Selector Guide
to find the part number
corresponding to the desired output voltages.
The OUT1 and OUT2 output voltages of the MAX8668
are set by a resistor network connected to FB_ as
shown in Figure 5. With this configuration, a portion of
the feedback signal is sensed on the switched side of
the inductor (LX), and the output voltage droops slightly
as the load current is increased due to the DC resistance of the inductor (DCR). This allows the load regulation to be set to match the voltage droop during a
load transient (voltage positioning), reducing the peakto-peak output-voltage deviation during a load transient, and reducing the output capacitance
requirements.
For the simplest method of setting the output voltage,
R6 is not installed. Choose the value of R2 (a good
starting value is 100kΩ), and then calculate the value of
R1 as follows:
where VFBis the feedback regulation voltage (0.6V).
With the voltage set in this manner, the voltage positioning depends only on the DCR, and the maximum
output voltage droop is:
Setting the Output Voltages with
Reduced Voltage Positioning
To obtain less voltage positioning than described in the
previous section, use the following procedure for setting the output voltages. The OUT1 and OUT2 output
voltages and voltage positioning of the MAX8668 are
set by a resistor network connected to FB_ as shown in
Figure 5.
To set the output voltage (V
OUT
), first select a value for
R2 (a good starting value is 100kΩ). Then calculate the
value of REQ(the equivalent parallel resistance of R1
and R6) as follows:
where VFBis the feedback-regulation voltage (0.6V).
Calculate the factor m based on the desired load-regulation improvement:
where I
OUT(MAX)
is the maximum output current, DCR is
the inductor series resistance, and ΔV
OUT(DESIRED)
is the
maximum allowable droop in the output voltage at full
load. The calculated value for m must be between 1.1 and
2; m = 2 results in a 2x improvement in load regulation.
Now calculate the values of R1 and R6 as follows:
The value of R1 should always be lower than the value
of R6.
Power-Supply Sequencing
The MAX8667/MAX8668 have individual enable inputs
for each regulator to allow complete control over the
power sequencing. When all EN_ inputs are low, the IC
is in low-power shutdown mode, reducing the supply
current to less than 1µA. After one of the EN_ inputs
asserts high, the corresponding regulator begins softstart after a delay of tEN(see Figure 2). The first output
enabled from shutdown mode or initially powering up
the IC has a longer delay (t
PWRON
) as the IC exits the
low-power shutdown mode.
Inductor Selection
The MAX8667/MAX8668 step-down converters operate
with inductors between 2.2µH and 4.7µH. Low inductance values are physically smaller, but require faster
switching, resulting in some efficiency loss. The inductor’s DC current rating must be high enough to account
Figure 5. MAX8668 Feedback Network
RR
121=× −
ΔVDCR I
OUT MAXOUT MAX()()
V
⎛
OUT
⎜
⎝
V
FB
⎞
⎟
⎠
=×
R1
R2
L1DCR
C4
(OPTIONAL)
OUT
R6
ESR
C6
R
LOAD
LX_
FB_
IDCR
OUT MAX
m
=
V
Δ
OUT DESIRED
×
()
()
RR m
1
=×
EQ
RR
6
=×
EQ
m
m
1
−
R
V
⎛
OUT
=−
EQ
⎜
⎝
V
FB
⎞
×12
R
⎟
⎠
MAX8667/MAX8668
1.5MHz Dual Step-Down DC-DC Converters
with Dual LDOs and Individual Enables
for peak ripple current and load transients. The stepdown converter’s unique architecture has minimal current overshoot during startup and load transients and in
most cases, an inductor capable of 1.3x the maximum
load current is acceptable.
For output voltages above 2V, when light-load efficiency
is important, the minimum recommended inductor is
2.2µH. For optimum voltage-positioning load transients,
choose an inductor with DC series resistance in the
50mΩ to 150mΩ range. For higher efficiency at heavy
loads (above 200mA) and minimal load regulation,
keep the inductor resistance as small as possible. For
light-load applications (up to 200mA), higher resistance
is acceptable with very little impact on performance.
Capacitor Selection
Input Capacitors
The input capacitor for the step-down converters (C2 in
Figures 3 and 4) reduces the current peaks drawn from
the battery or input power source and reduces switching noise in the IC. The impedance of C2 at the switching frequency should be very low. Surface-mount
ceramic capacitors are a good choice due to their
small size and low ESR. Make sure the capacitor maintains its capacitance over temperature and DC bias.
Ceramic capacitors with X5R or X7R temperature characteristics generally perform well. A 10µF ceramic
capacitor is recommended.
A 4.7µF ceramic capacitor is recommended for the
LDO input capacitor (C3 in Figure 3).
Step-Down Output Capacitors
The step-down output capacitors (C6 and C7 in Figures
3 and 4) are required to keep the output-voltage ripple
small and to ensure regulation loop stability. These
capacitors must have low impedance at the switching
frequency. Surface-mount ceramic capacitors are a
good choice due to their small size and low ESR. Make
sure the capacitor maintains its capacitance over temperature and DC bias. Ceramic capacitors with X5R or
X7R temperature characteristics generally perform well.
The output capacitance can be very low. For most
applications, a 2.2µF ceramic capacitor is sufficient.
For optimum load-transient performance and very low
output ripple, the output capacitor value in µF should
be equal to or greater than the inductor value in µH.
Feed-Forward Capacitor
The feed-forward capacitors on the MAX8668 (C4 and
C5 in Figure 4) set the feedback loop response, control
the switching frequency, and are critical in obtaining
the best efficiency possible. Small X7R and C0G
ceramic capacitors are recommended.
For OUT1, calculate the value of C4 as follows:
C4 = 1.2 x 10-5(s/V) x (V
OUT
/ R1)
For OUT2, calculate the value of C5 and C10 as follows:
Cff= 1.2 x 10-5(s/V) x (V
OUT
/ R3)
Cff= C5 + (C10 / 2)
(C10 / C5) + 1 = (V
OUT
/ VFB), where VFBis 0.6V.
Rearranging the formulas:
C10 = 2 x Cffx (V
OUT
- VFB)/(V
OUT
+ VFB)
C5 = Cff– (C10 / 2)
C10 is needed if V
OUT
> 1.5V or V
IN12
can be less than
V
OUT
/ 0.65.
Table 1. Recommended Inductors
MANUFACTURERINDUCTORL (µH)RL (mΩ)CURRENT RATING (A)L x W x H (mm)
FDKMIPF20162.21101.12.0 x 1.6 x 1.0
FDKMIPF2520D2.2801.32.5 x 2.0 x 1.0
Murata
SumidaCDRH2D092.21200.443.2 x 3.2 x 1.0
TDKGLF251812T2.22000.62.5 x 1.8 x 1.35
TOKOD2812C2.21400.772.8 x 2.8 x 1.2
TOKOMDT2520-CR2.2800.72.5 x 2.0 x 1.0
Wurth
Taiyo YudenCB2518T2.2900.512.5 x 1.8 x 2.0
LQH32CN2R2M52.2970.793.2 x 2.5 x 1.55
LQM31P2.22200.93.2 x 1.6 x 0.95
TPC Series2.2551.84.0 x 4.0 x 1.1
TPC Series4.71241.354.0 x 4.0 x 1.1
MAX8667/MAX8668
1.5MHz Dual Step-Down DC-DC Converters
with Dual LDOs and Individual Enables
Connect a 4.7µF ceramic capacitor between OUT3 and
GND, and a second 4.7µF ceramic capacitor from
OUT4 to GND. For a constant loading above 10mA, the
output capacitors can be reduced to 2.2µF. The equivalent series resistance (ESR) of the LDO output capacitors affects stability and output noise. Use output
capacitors with an ESR of 0.1Ω or less to ensure stable
operation and optimum transient response. Surfacemount ceramic capacitors have very low ESR and are
commonly available. Connect these capacitors as
close as possible to the IC’s pins to minimize PCB trace
inductance.
Thermal Considerations
The maximum package power dissipation of the
MAX8667/MAX8668 is 1667mW. Make sure the power
dissipated by the MAX8667/MAX8668 does not exceed
this rating. The total IC power dissipation is the sum of
the power dissipation of the four regulators:
Estimate the OUT1 and OUT2 power dissipations as
follows:
where RLis the inductor’s DC resistance, and η is the
efficiency (see the
Typical Operating Characteristics
section).
Calculate the OUT3 and OUT4 power dissipations as
follows:
The maximum junction temperature of the MAX8667/
MAX8668 is +150°C. The junction-to-case thermal
resistance (θ
JC
) of the MAX8667/MAX8668 is 6.9°C/W.
When mounted on a single-layer PCB, the junction to
ambient thermal resistance (θ
JA
) is about 64°C/W.
Mounted on a multilayer PCB, θJAis about 48°C/W.
Calculate the junction temperature of the
MAX8667/MAX8668 as follows:
where TAis the maximum ambient temperature. Make
sure the calculated value of TJdoes not exceed the
+150°C maximum.
PCB Layout
High switching frequencies and relatively large peak
currents make PCB layout a very important aspect of
design. Good design minimizes excessive EMI on the
feedback paths and voltage gradients in the ground
plane, both of which can result in instability or regulation errors. Connect the input capacitors as close as
possible to the IN_ and PGND_ pins. Connect the
inductor and output capacitors as close as possible to
the IC and keep the traces short, direct, and wide.
The feedback network traces are sensitive to inductor
magnetic field interference. Route these traces away
from the inductors and noisy traces such as LX. Keep
the feedback components close to the FB_ pin.
Connect GND and PGND_ to the ground plane.
Connect the exposed paddle to the ground plane with
one or more vias to help conduct heat away from the
IC.
Refer to the MAX8668 evaluation kit for a PCB layout
example.
PPPPP
=+++
DDDDD
1234
=× ×
PIV
DOUTOUT11 1
=× ×
PIV
DOUTOUT22 2
PIV V
=× −
DOUTINOUT3334 3
()
1
1
−η
η
−η
η
TTP
=+× θ
JADJA
PIV V
=×−
DOUTINOUT4434 4
()
MAX8667/MAX8668
1.5MHz Dual Step-Down DC-DC Converters
with Dual LDOs and Individual Enables
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
MARKING
D/2
D
E
E/2
AAAA
C
L
0.10 C0.08 C
A
A2
A1
(NE - 1) X e
(ND - 1) X e
C
L
L
e
k
L
C
L
e
E2/2
E2
D2/2
D2
b
0.10 M C A B
C
L
L
e
12x16L QFN THIN.EPS
PACKAGE OUTLINE
8, 12, 16L THIN QFN, 3x3x0.8mm
21-0136
1
I
2
MAX8667/MAX8668
1.5MHz Dual Step-Down DC-DC Converters
with Dual LDOs and Individual Enables
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
8L 3x3
PKG
REF.MIN.
MIN.
NOM. M
3.00 3.10
0.65 BSC.
0.55 0.75
8
2
2
0.02
0.20 REF
-
AX.
0.05
-
0.70 0.75 0.80
A
b
0.25 0.30 0.35
2.90
D
2.90 3.00 3.10
E
e
0.35
L
ND
NE
A1
A2
k
0.25
0
12L 3x3
NOM. MAX.NOM.
0.70
0.75
0.50 BSC.
0
0.20 REF
0.25
3.00
3.00
0.55
0.02
0.80
0.30
3.10
3.10
0.65
12N
3
3
0.05
-
-
0.20
2.90
2.90
0.45
0.25
16L 3x3
MIN.MAX.
0.70
0.75
0.25
3.00
3.00
0.50 BSC.
0.40
040.02
0.20 REF
0.80
0.30
3.10
3.10
0.50
16
4
0.05
-
0.20
2.90
2.90
0.30
0.25
EXPOSED PAD VARIATIONS
PKG.
CODES
TQ833-11.250.25 0.700.35 x 45°WEE C1.250.700.25
T1233-1
3
T1233-
T1233-4
T1633-20.9 5
T1633F-3
T1633FH-3 0.65 0.80 0.95
T1633-40.9 5
-
T1633-50.9 5
D2
MIN.
0.95
0.95
0.95
0.65
MAX.
NOM.
1.25
1.10
1.25
1.10
1.251.10
1.25
1.10
0.95
0.80
1.10 1.25 0.95 1.10
1.25
1.10
E2
NOM.
MIN.
0.95
0.95 1.100.35 x 45°1.25WEED-1
0.95
0.65
0.65 0.80
1.10
1.100.95
1.10
0.80
1.10
MAX.
1.25
1.25
0.95
0.95
1.25
1.25
ID
PIN
0.35 x 45°
0.35 x 45°
0.35 x 45°
0.225 x 45°
0.225 x 45°
0.35 x 45°
0.35 x 45°
JEDEC
WEED-1
WEED-11.25
WEED-2
WEED-2
WEED-2
WEED-2
WEED-20.95
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
10. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
12. WARPAGE NOT TO EXCEED
0.10mm.
PACKAGE OUTLINE
8, 12, 16L THIN QFN, 3x3x0.8mm
21-0136
I
2
2
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