The MAX8545/MAX8546/MAX8548 are voltage-mode
pulse-width-modulated (PWM), step-down DC-DC controllers ideal for a variety of cost-sensitive applications.
They drive low-cost N-channel MOSFETs for both the
high-side switch and synchronous rectifier, and require
no external current-sense resistor. These devices can
supply output voltages as low as 0.8V.
The MAX8545/MAX8546/MAX8548 have a wide 2.7V to
28V input range, and do not need any additional bias
voltage. The output voltage can be precisely regulated
from 0.8V to 0.83 x VIN. These devices can provide efficiency up to 95%. Lossless short-circuit and current-limit
protection is provided by monitoring the R
DS(ON)
of the
low-side MOSFET. The MAX8545 and MAX8548 have a
current-limit threshold of 320mV, while the MAX8546 has
a current-limit threshold of 165mV. All devices feature
foldback-current capability to minimize power dissipation
under short-circuit condition. Pulling the COMP/EN pin
low with an open-collector or low-capacitance, opendrain device can shut down all devices.
The MAX8545/MAX8546 operate at 300kHz and the
MAX8548 operates at 100kHz. The MAX8545/
MAX8546/MAX8548 are compatible with low-cost aluminum electrolytic capacitors. Input undervoltage lockout prevents proper operation under power-sag
operations to prevent external MOSFETs from overheating. Internal soft-start is included to reduce inrush current. These devices are offered in space-saving 10-pin
µMAX packages.
(VIN= VL= VCC= 5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND unless otherwise noted.)
V
IN
to GND ............................................................-0.3V to +30V
V
CC
to GND .............................-0.3V, lower of 6V or (VL + 0.3V)
FB to GND ................................................................-0.3V to +6V
BST to GND ............................................................-0.3V to +36V
VL, DL, COMP to GND ..............................-0.3V to (V
CC
+ 0.3V)
BST to LX..................................................................-0.3V to +6V
DH to LX....................................................-0.3V to (V
BST
+ 0.3V)
VL Short to GND ......................................................................5s
LX to GND ......................................................................0 to 30V
Input Current (any pin) .....................................................±50mA
The MAX8545/MAX8546/MAX8548 are BiCMOS switchmode power-supply controllers designed to implement
simple, buck-topology regulators in cost-sensitive
applications. The main power-switching circuit consists
of two N-channel MOSFETs, an inductor, and input/output filter capacitors. An all N-channel synchronous-rectified design provides high efficiency at reduced cost.
These devices have an internal 5V linear regulator that
steps down the input voltage to supply the IC and the
gate drivers. The low-side-switch gate driver is directly
powered from the 5V regulator (VL), while the highside-switch gate driver is indirectly powered from VL
plus an external diode-capacitor boost circuit.
Current-Limit and
Short-Circuit Protection
The MAX8545/MAX8546/MAX8548 employ a valley current-sensing algorithm that uses the R
DS(ON)
of the lowside N-channel MOSFET to sense the current. This
eliminates the need for an external sense resistor usually
placed in series with the output. The voltage measured
across the low-side MOSFET’s R
DS(ON)
is compared to
a fixed -320mV reference for the MAX8545/MAX8548
and a fixed -165mV reference for the MAX8546. The current limit is given by the equations below:
Aside from current limiting, these devices feature foldback short-circuit protection. This feature is designed
to reduce the current limit by 80% as the output voltage
drops to 0V.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving Nchannel MOSFETs with low gate charge. An adaptive
dead-time circuit monitors the DL output and prevents
the high-side MOSFET from turning on until the low-side
MOSFET is fully off. There must be a low-resistance,
low-inductance connection from the DL driver to the
MOSFET gate for the adaptive dead-time circuit to work
properly. Otherwise, the sense circuitry in the MAX8545/
MAX8546/MAX8548 may detect the MOSFET gate as off
while there is actually charge left on the gate. Use very
short, wide traces measuring no less than 50 to 100 mils
wide if the MOSFET is 1 inch away from the MAX8545/
MAX8546/MAX8548. The same type of adaptive deadtime circuit monitors the DH off edge. The same recommendations apply for the gate connection of the
high-side MOSFET.
The internal pulldown transistor that drives DL low is
robust, with a 1.1Ω (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side
synchronous-rectifier MOSFET during the fast rise time
of the LX node.
Soft-Start
The MAX8545/MAX8546/MAX8548 feature an internally
set soft-start function that limits inrush current. It accomplishes this by ramping the internal reference input to the
controller’s transconductance error amplifier from 0 to
the 0.8V reference voltage. The ramp time is 1024 oscillator cycles for the MAX8548 and 2048 oscillator cycles
for the MAX8545/MAX8546. At the nominal 100kHz and
300kHz switching rate, the soft-start ramp is approximately 10.2ms and 6.8ms, respectively.
High-Side Gate-Drive Supply (BST)
A flying-capacitor boost circuit generates gate-drive voltage for the high-side N-channel MOSFET. The flying
capacitor is connected between the BST and LX nodes.
On startup, the synchronous rectifier (low-side MOSFET)
forces LX to ground and charges the boost capacitor to
VL. On the second half-cycle, the MAX8545/MAX8546/
MAX8548 turn on the high-side MOSFET by closing an
internal switch between BST and DH. This provides the
necessary gate-to-source voltage to drive the high-side
MOSFET gate above its source at the input voltage.
Internal 5V Linear Regulator
All MAX8545/MAX8546/MAX8548 functions are internally
powered from an on-chip, low-dropout 5V regulator (VL).
These devices have a maximum input voltage (VIN) of
28V. Connect VCCto VLthrough a 10Ω resistor and
bypass VCCto GND with a 0.1µF ceramic capacitor. The
VIN-to-VL dropout voltage is typically 140mV, so when V
IN
is less than 5.5V, VL is typically VIN- 140mV.
The internal linear regulator can source a minimum of
25mA and a maximum of approximately 40mA to supply
power to the IC low-side and high-side MOSFET drivers.
Duty-Cycle Limitations for
Low V
OUT/VIN
Ratios
The MAX8545/MAX8546/MAX8548’s output voltage is
adjustable down to 0.8V. However, the minimum duty
cycle can limit the ability to supply low-voltage outputs
from high-voltage inputs. With high input voltages, the
required duty factor is approximately:
where R
DS(ON)
x I
LOAD
is the voltage drop across the
synchronous rectifier. Therefore, the maximum input
voltage (V
IN(DFMAX)
) that can supply a given output
voltage is:
If the circuit cannot attain the required duty cycle dictated by the input and output voltages, the output voltage still remains in regulation. However, there may be
intermittent or continuous half-frequency operation as
the controller attempts to lower the average duty cycle
by deleting pulses. This can increase output voltage
ripple and inductor current ripple, which increases
noise and reduces efficiency. Furthermore, circuit stability is not guaranteed.
Applications Information
Design Procedures
1) Input Voltage Range. The maximum value
(V
IN(MAX)
) must accommodate the worst-case high
input voltage. The minimum value (V
IN(MIN)
) must
account for the lowest input voltage after drops due
to connectors, fuses, and switches are considered.
In general, lower input voltages provide the best
efficiency.
2) Maximum Load Current. There are two current
values to consider. Peak load current (I
LOAD(MAX)
)
determines the instantaneous component stresses
and filtering requirements and is key in determining
output capacitor requirements. I
LOAD(MAX)
also
determines the required inductor saturation rating.
Continuous load current (I
LOAD
) determines the
thermal stresses, input capacitor, and MOSFETs,
as well as the RMS ratings of other heat-contributing components such as the inductor.
3) Inductor Value. This choice provides tradeoffs
between size, transient response, and efficiency.
Higher inductance value results in lower inductor
ripple current, lower peak current, lower switching
losses, and, therefore, higher efficiency at the cost
of slower transient response and larger size. Lower
inductance values result in large ripple currents,
smaller size, and poor efficiency, while also providing faster transient response.
Setting the Output Voltage
An output voltage between 0.8V and (0.83 x VIN) can
be configured by connecting FB to a resistive divider
between the output and GND (see Figures 1 and 2).
Select resistor R4 in the 1kΩ to 10kΩ range. R3 is then
given by:
where VFB= +0.8V.
Inductor Selection
Determine an appropriate inductor value with the following equation:
where LIR is the ratio of inductor ripple current to average continuous maximum load current. Choosing LIR
between 20% to 40% results in a good compromise
between efficiency and economy. Choose a low-coreloss inductor with the lowest possible DC resistance.
Ferrite-core-type inductors are often the best choice for
performance; however, the MAX8548’s low switching
frequency also allows the use of powdered iron core
inductors in ultra-low-cost applications where efficiency
is not critical. With any core material, the core must be
large enough not to saturate at the peak inductor current (I
PEAK
).
Setting the Current Limit
The MAX8545/MAX8546/MAX8548 provide valley current limit by sensing the voltage across the external
low-side MOSFET. The minimum current-limit threshold
voltage is -280mV for the MAX8545/MAX8548 and
-140mV for the MAX8546. The MOSFET on-resistance
required to allow a given peak inductor current is:
where I
VALLEY
= I
LOAD(MAX)
x (1 - LIR / 2), and
R
DS(ON)MAX
is the maximum on-resistance of the lowside MOSFET at the maximum operating junction
temperature.
)
V
IN DFMAX
VR I
+×()
OUTDS ONLOAD
1
≤+×
DC
()
V
IN
VR I
()
MIN
()
OUTDS ONLOAD()()
RR
V
34
OUT
V
FB
1=−
LV
=×
OUT
VfLIR I
INOSCLOAD MAX
R
DS ON MAX
R
DS ON MAX
II
=+
PEAKLOAD MAXLOAD MAX
.
028
()
()
≤
I
VALLEY
.
014
I
VALLEY
VV
−
()
INOUT
×××
LIR
()()
2
×
()
I
V
( /
for the MAXMAX
V
( )≤
for the MAX
85458548
8546
MAX8545/MAX8546/MAX8548
Low-Cost, Wide Input Range, Step-Down
Controllers with Foldback Current Limit
A limitation of sensing current across a MOSFET’s onresistance is that the current-limit threshold is not accurate since MOSFET R
DS(ON)
specifications are not
precise. This type of current limit provides a coarse level
of fault protection. It is especially suited when the input
source is already current-limited or otherwise protected.
Power MOSFET Selection
The MAX8545/MAX8546/MAX8548 drive two external,
logic-level, N-channel MOSFETs as the circuit switching elements. The key selection parameters are:
1) On-resistance (R
DS(ON)
): the lower, the better.
2) Maximum drain-to-source voltage (V
DSS
) should be
at least 10% higher than the input supply rail at the
high-side MOSFET’s drain.
3) Gate charges (Qg, Qgd, Qgs): the lower, the better.
Choose the MOSFETs with rated R
DS(ON)
at VGS= 4.5V
for an input voltage greater than 5V, and at VGS= 2.5V
for an input voltage less than 5.5V. For a good compromise between efficiency and cost, choose the high-side
MOSFET (N1) that has conduction losses equal to the
switching losses at nominal input voltage and maximum
output current. For N2, make sure it does not spuriously
turn on due to a dV/dt caused by N1 turning on as this
would result in shoot-through current degrading the
efficiency. MOSFETs with a lower Qgd/ Qgsratio have
higher immunity to dV/dt.
MOSFET Power Dissipation
For proper thermal-management design, the power dissipation must be calculated at the desired maximum
operating junction temperature, maximum output current, and worst-case input voltage (for the low-side
MOSFET (N2) the worst case is at V
IN(MAX)
, for the highside MOSFET (N1) the worst case can be either at
V
IN(MIN)
or V
IN(MAX)
). N1 and N2 have different loss
components due to the circuit operation. N2 operates as
a zero-voltage switch; therefore, the major losses are:
the channel conduction loss (P
N2CC
), the body-diode
conduction loss (P
N2DC
), and the gate-drive loss
(P
N2DR
).
Use R
DS(ON)
at T
J(MAX)
.
where V
F
is the body-diode forward voltage drop, tdtis
the dead time between N1 and N2 switching transitions
(which is 30ns), and fSis the switching frequency.
Because of zero-voltage switch operation, the N2 gatedrive losses are due to charging and discharging the
input capacitor, C
ISS
. These losses are distributed
between the average DL gate driver’s pullup and pulldown resistors and the internal gate resistance. The
RDLis typically 1.8Ω, and the internal gate resistance
(R
GATE
) of the MOSFET is typically 2Ω. The drive
power dissipated in N2 is given by:
N1 operates as a duty-cycle control switch and has the
following major losses: the channel conduction loss
(P
N1CC
), the voltage and current overlapping switching
loss (P
N1SW
), and the drive loss (P
N1DR
). N1 does not
have a body-diode conduction loss because the diode
never conducts current.
Use R
DS(ON)
at T
J(MAX)
.
where I
GATE
is the average DH high driver output-cur-
rent capability determined by:
where RDHis the high-side MOSFET driver’s average
on-resistance (2.05Ω typ) and R
GATE
is the internal
gate resistance of the MOSFET (2Ω typ).
where VGS~ VL.
In addition to the losses above, allow about 20% more
for additional losses due to MOSFET output capacitance and N2 body-diode reverse recovery charge dissipated in N1. Refer to the MOSFET data sheet for
thermal resistance specifications to calculate the PC
board area needed. This information is essential to
maintain the desired maximum operating junction temperature with the above calculated power dissipation.
To reduce EMI caused by switching noise, add a 0.1µF
ceramic capacitor from the high-side MOSFET drain to
the low-side MOSFET source or add resistors in series
P
NCC
1=−
PIVtf
N DCLOADFdtS2
V
OUT
××
V
IN
2=×× × ×
2
IR
LOAD
DS ON2
()
PCVf
=×
N DRISSGSS
2
2
()
××
R
GATE
RR
+
GATEDL
P
NCC
PVI f
=
=×××
N SWINLOADS
1
V
OUT
V
IN
×
()
2
IR
LOADDS ON1
×
QQ
GSGD
I
GATE
()
+
I
GATE ON
()
1
=×
2
VL
+
RR
DHGATE
PQVf
=×××
NDRGSGS S
1
R
GATE
+
RR
DHGATE
MAX8545/MAX8546/MAX8548
Low-Cost, Wide Input Range, Step-Down
Controllers with Foldback Current Limit
with DH and DL to slow down the switching transitions.
However, adding series resistors increases the power
dissipation of the MOSFET, so ensure temperature ratings of the MOSFET are not exceeded.
Input-Capacitor Selection
The input capacitors (C2 and C3 in Figure 1) reduce
noise injection and current peaks drawn from the input
supply. The input capacitor must meet the ripple-current requirement (I
RMS
) imposed by the switching cur-
rents. The RMS input ripple current is given by:
For optimal circuit reliability, choose a capacitor that
has less than 10°C temperature rise at the RMS current.
I
RMS
is maximum when the input voltage equals 2 x
V
OUT
, where I
RMS
= 1/2 I
LOAD
.
Output Capacitor Selection
The key parameters for the output capacitor are the
actual capacitance value, the equivalent series resistance (ESR), the equivalent series inductance (ESL),
and the voltage-rating requirements. All these parameters affect the overall stability, output ripple voltage,
and transient response.
The output ripple has three components: variations in the
charge stored in the output capacitor, the voltage drop
across the ESR, and the voltage drop across the ESL.
V
RIPPLE
= V
RIPPLE(ESR)
+ V
RIPPLE(C)
+ V
RIPPLE(ESL)
The output voltage ripple as a consequence of the ESR
and output capacitance is:
where I
P-P
is the peak-to-peak inductor current (see the
Inductor Selection section).
While these equations are suitable for initial capacitor
selection to meet the ripple requirement, final values
may also depend on the relationship between the LC
double-pole frequency and the capacitor ESR-zero frequency. Generally, the ESR zero is higher than the LC
double pole; however, it is preferable to keep the ESR
zero close to the LC double pole when possible to
negate the sharp phase shift of the typically high-Q
double LC pole (see the Compensation Design section). Aluminum electrolytic or POS capacitors are recommended. Higher output current requires multiple
capacitors to meet the output ripple voltage.
The MAX8545/MAX8546/MAX8548s’ response to a load
transient depends on the selected output capacitor. After
a load transient, the output instantly changes by (ESR x
∆I
LOAD
) + (ESL x dI/dt). Before the controller can
respond, the output deviates further depending on the
inductor and output capacitor values. After a short period
of time (see the Typical Operating Characteristics), the
controller responds by regulating the output voltage back
to its nominal state. The controller response time
depends on the closed-loop bandwidth. Higher bandwidth results in faster response time, preventing the output voltage from further deviation. Do not exceed thecapacitor’s voltage or ripple-current ratings.
Boost Diode and Capacitor Selection
A low-current Schottky diode, such as the CMPSH-3
from Central Semiconductor, works well for most applications. Do not use large power diodes since higher
junction capacitance can charge up BST to LX voltage
that could exceed the device rating of 6V. The boost
capacitor should be in the range of 0.1µF to 0.47µF,
depending on the specific input and output voltages
and the external components and PC board layout. The
boost capacitance needs to be as large as possible to
prevent it from charging to excessive voltage, but small
enough to adequately charge during the minimum lowside MOSFET conduction time, which happens at the
maximum operating duty cycle (this occurs at the minimum input voltage). In addition, ensure the boost
capacitor does not discharge to below the minimum
gate-to-source voltage required to keep the high-side
MOSFET fully enhanced for lowest on-resistance. This
minimum gate-to-source voltage V
GS(MIN)
is deter-
mined by:
where Qg is the total gate charge of the high-side
MOSFET and C
BOOST
is the boost capacitor value.
Compensation Design
The MAX8545/MAX8546/MAX8548 use a voltage-mode
control scheme that regulates the output voltage. This is
done by comparing the error amplifier’s output (COMP) to
a fixed internal ramp. The inductor and output capacitor
create a double pole at the resonant frequency, which
has a gain drop of 40dB per decade, and a phase shift
of 180°. The error amplifier must compensate for this
gain drop and phase shift to achieve a stable highbandwidth, closed-loop system.
The basic regulator loop consists of a power modulator
(Figure 3), an output feedback divider, and an error
amplifier. The power modulator has DC gain set by
VIN/V
RAMP
, with a double pole set by the inductor and
output capacitor, and a single zero set by the output
capacitor (C
OUT
) and its equivalent series resistance
(ESR). Below are equations that define the power modulator:
The DC gain of the power modulator is:
where V
RAMP
= 1V.
The pole frequency due to the inductor and output
capacitor is:
The zero frequency due to the output capacitor’s ESR is:
The output capacitor is usually comprised of several
same capacitors connected in parallel. With n capacitors in parallel, the output capacitance is:
C
OUT
= n X C
EACH
The total ESR is:
The ESR zero (f
ZESR
) for a parallel combination of
capacitors is the same as for an individual capacitor.
The feedback divider has a gain of GFB= VFB/V
OUT
,
where VFBis 0.8V.
The transconductance error amplifier has DC gain
G
EA(dc)
of 72dB. A dominant pole (f
DPEA
) is set by the
compensation capacitor (CC), the amplifier output
resistance (RO) equals 37MΩ, and the compensation
resistor (RC):
The compensation resistor and the compensation
capacitor set a zero:
The total closed-loop gain must equal unity at the
crossover frequency. The crossover frequency should
be higher than f
ZESR
, so that the -1 slope is used to
cross over at unity gain. Also, the crossover frequency
should be less than or equal to 1/5 the switching frequency (fSW) of the controller.
The loop-gain equation at the crossover frequency is:
VFB/V
OUT
x G
EA(fC)
x G
MOD(fC)
= 1
where G
EA(fc)
= g
mEA
× RC, and G
MOD(fc)
= G
MOD(DC)
× (f
PMOD
)2 / (f
ZESR
× fC).
The compensation resistor, RC, is calculated from:
RC= V
OUT
/ g
mEA
x VFBx G
MOD(fC)
where g
mEA
= 108µS.
Due to the underdamped (Q > 1) nature of the output
LC double pole, the error-amplifier compensation zero
should be approximately 0.2 f
PMOD
to provide good
phase boost. CCis calculated from:
A small capacitor, CF, can also be added from COMP to
GND to provide high-frequency decoupling. CFadds
another high-frequency pole, f
PHF
, to the error-amplifier
response. This pole should be greater than 100 times the
error-amplifier zero frequency to have negligible impact
on the phase margin. This pole should also be less than
1/2 the switching frequency for effective decoupling.
100 f
ZEA
< f
PHF
< 0.5 f
sw
Select a value for f
PHF
in the range given above, then
solve for CFusing the following equation:
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and stable operation. If possible, mount all the
power components on the top side of the board with their
G
MOD DC
()
=
V
IN
V
RAMP
f
PMOD
f
ZESR
=
=
LC
2π
××
2π
1
OUT
1
ESR C
OUT
ESR
=
ESR
EACH
n
f
DPEA
=
2π
1
CRR
×× +
()
COC
f
ZEA
=
CR
××
2π
1
CC
ff
ZESRC
<≤
f
SW
5
C
=
C
2π
5
Rf
××
CPMOD
C
F
=
××
2π
1
Rf
CPHF
MAX8545/MAX8546/MAX8548
Low-Cost, Wide Input Range, Step-Down
Controllers with Foldback Current Limit
ground terminals flush against one another. Follow these
guidelines for good PC board layout:
1) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
2) Connect the power and analog grounds close to
the IC pin 7.
3) Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a few milohms of excess trace resistance
cause a measurable efficiency penalty.
4) LX and GND connections to the low-side MOSFET
for current sensing must be made using Kelvin
sense connections to guarantee the current-limit
accuracy. With SO-8 MOSFETs, this is best done
by routing power to the MOSFETs from outside
using the top copper layer, while connecting LX
and GND inside (underneath) the SO-8 package.
5) When tradeoffs in trace lengths must be made, it’s
preferable to allow the inductor charging current
path to be longer than the discharge path. For
example, it’s better to allow some extra distance
between the inductor and the low-side MOSFET or
between the inductor and the output filter capacitor.
6) Ensure that the connection between the inductor
and C3 is short and direct.
7) Route switching nodes (BST, LX, DH, and DL) away
from sensitive analog areas (COMP and FB).
Ensure the C1 ceramic bypass capacitor is immediately
adjacent to the pins and as close to the device as possible. Furthermore, the VINand GND pins of MAX8545/
MAX8546/MAX8548 must terminate at the two ends of
C1 before connecting to the power switches and C2.
Low-Cost, Wide Input Range, Step-Down
Controllers with Foldback Current Limit
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
0.6±0.1
e
10
ÿ 0.50±0.1
1
0.6±0.1
TOP VIEW
D2
A2
b
D1
FRONT VIEW
4X S
10
H
1
BOTTOM VIEW
GAGE PLANE
A
A1
α
E2
E1
SIDE VIEW
INCHES
MAX
MIN
DIM
A1
A2 0.030 0.0370.750.95
D1
D2
E1
E2
H
L
L1
b
e
c
S
α
c
L
L1
PROPRIETARY INFORMATION
TITLE:
0.043
-A
0.006
0.002
0.116
0.120
0.114
0.118
0.116
0.120
0.114
0.118
0.187
0.199
0.0157
0.0275
0.037 REF
0.007
0.0106
0.0197 BSC
0.0035
0.0078
0.0196 REF
6∞
0∞0∞6∞
PACKAGE OUTLINE, 10L uMAX/uSOP
21-0061
MILLIMETERS
MAX
MIN
1.10
-
0.15
0.05
3.05
2.95
3.00
2.89
3.05
2.95
2.89
3.00
4.75
5.05
0.40
0.70
0.940 REF
0.177
0.270
0.500 BSC
0.090
0.200
0.498 REF
10LUMAX.EPS
REV.DOCUMENT CONTROL NO.APPROVAL
1
I
1
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