The MAX7360 I2C-interfaced peripheral provides microprocessors with management of up to 64 key switches,
with an additional eight LED drivers/GPIOs that feature
constant-current, PWM intensity control, and rotary
switch control options.
The key-switch drivers interface with metallic or resistive
switches with on-resistances up to 5kI. Key inputs
are monitored statically, not dynamically, to ensure
low-EMI operation. The MAX7360 features autosleep
and autowake modes to further minimize the power
consumption of the device. The autosleep feature puts
the device in a low-power state (1FA typ) after a sleep
timeout period. The autowake feature configures the
MAX7360 to return to normal operating mode from sleep
upon a keypress.
The key controller debounces and maintains a FIFO of
keypress and release events (including autorepeat, if
enabled). An interrupt (INTK) output can be configured
to alert keypresses, as they occur, or at maximum rate.
There are eight open-drain I/O ports, which can be used
to drive LEDs. The maximum constant-current level for
each open-drain port is 20mA. The intensity of the LED
on each open-drain port can be individually adjusted
through a 256-step PWM control. An input port pair
(PORT6, PORT7) can be configured to accept 2-bit gray
code inputs from a rotary switch. In addition, if not used
for key-switch control, up to six column pins can be used
as general-purpose open-drain outputs (GPOs) for LED
drive or logic control.
The MAX7360 is offered in a 40-pin (5mm x 5mm) thin
QFN package with an exposed pad, and a small 36-bump
wafer level package (WLP) for cell phones, pocket PCs,
and other portable consumer electronic applications. The
MAX7360 operates over the -40NC to +85NC extended
temperature range.
Applications
Cell Phones
PDAs
Handheld Games
Portable Consumer Electronics
Printers
Instrumentation
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a single layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Note 2: Refer to Pb-free solder-reflow requirements described in J-STD-020, Rev D.1, or any other paste supplier specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
ESD Protection
Human Body Model (RD = 1.5kI, CS = 100pF)
All Pins .............................................................................Q2kV
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.62V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25NC.) (Notes 3, 4)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Data Hold Timet
Data Setup Timet
SCL Clock Low Periodt
SCL Clock High Periodt
MAX7360
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Signal,
Transmitting
Pulse Width of Spike Suppressedt
Capacitive Load for Each Bus
Line
Note 3: All parameters are tested at TA = +25NC. Specifications over temperature are guaranteed by design.
Note 4: All digital inputs at VCC or GND.
Note 5: Guaranteed by design.
Note 6: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 7: Cb = total capacitance of one bus line in pF. tR and tF measured between +0.8V and +2.1V.
Note 8: I
Note 9: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
P 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between +0.8V and +2.1V.
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Pin Description
PIN
TQFNWLP
1A6ROW0Row Input from Key Matrix. Leave ROW0 unconnected or connect to GND if unused.
2B6ROW1Row Input from Key Matrix. Leave ROW1 unconnected or connect to GND if unused.
3C4ROW2Row Input from Key Matrix. Leave ROW2 unconnected or connect to GND if unused.
MAX7360
4C6ROW3Row Input from Key Matrix. Leave ROW3 unconnected or connect to GND if unused.
5, 15, 25, 35B4, C5, D2,
E4
6D6ROW4Row Input from Key Matrix. Leave ROW4 unconnected or connect to GND if unused.
7D5ROW5Row Input from Key Matrix. Leave ROW5 unconnected or connect to GND if unused.
8E6ROW6Row Input from Key Matrix. Leave ROW6 unconnected or connect to GND if unused.
9D4ROW7Row Input from Key Matrix. Leave ROW7 unconnected or connect to GND if unused.
10, 20, 27,
30, 40
11F6COL0Column Output to Key Matrix. Leave COL0 unconnected if unused.
12E5COL1Column Output to Key Matrix. Leave COL1 unconnected if unused.
24D1INTIActive-Low GPI Interrupt Output. INTI is open drain and requires a pullup resistor.
26C1V
28B1AD0Address Input. AD0 selects up to four device slave addresses (Table 3).
29A1I.C.Internally Connected. Connect to GND for normal operation.
31B2PORT0
32A2PORT1
33B3PORT2
34A3PORT3
36A4PORT4
37C3PORT5
38A5PORT6
39B5PORT7
——EP
NAMEFUNCTION
Positive Supply Voltage. Bypass VCC to GND with a 0.1FF or higher ceramic capacitor.
CC
GPIO Port. Open-drain I/O rated at +14V. PORT0 can be configured as a constantcurrent output.
GPIO Port. Open-drain I/O rated at +14V. PORT1 can be configured as a constantcurrent output.
GPIO Port. Open-drain I/O rated at +14V. PORT2 can be configured as a constantcurrent output.
GPIO Port. Open-drain I/O rated at +14V. PORT3 can be configured as a constantcurrent output.
GPIO Port. Open-drain I/O rated at +14V. PORT4 can be configured as a constantcurrent output.
GPIO Port. Open-drain I/O rated at +14V. PORT5 can be configured as a constantcurrent output.
GPIO Port. Open-drain I/O rated at +14V. PORT6 Can be configured as a constantcurrent output, or a rotary switch input.
GPIO Port. Open-drain I/O rated at +14V. PORT7 can be configured as a constantcurrent output, or a rotary switch input.
Exposed Pad (TQFN only). EP is internally connected to GND. Connect EP to a ground
plane to increase thermal performance.
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Functional Block Diagram
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
COL0
COL1
COL2*
COL3*
COL4*
COL5*
COL6*
COL7*
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
MAX7360
INTI
INTK
SDA
SCL
AD0
MAX7360
I2C
INTERFACE
BUS
TIMEOUT
128kHz
OSCILLATOR
CONTROL
REGISTERS
FIFO
POR
PWM
GPIO
LOGIC
ROTARY
KEY
SCAN
LED ENABLE
GPIO ENABLE
GPIO INPUT
COLUMN ENABLE
GPO ENABLE
CURRENT DETECT
ROW ENABLE
PORT GPIO
AND
CONSTANT-
CURRENT
LED DRIVE
CURRENT
SOURCE
COLUMN
DRIVES
OPENDRAIN
ROW
DRIVES
*GPO
Detailed Description
The MAX7360 is a microprocessor peripheral low-noise
key-switch controller that monitors up to 64 key switches
with optional autorepeat, and key events that are
presented in a 16-byte FIFO. The MAX7360 also features
eight open-drain GPIOs configured for digital I/O or
constant-current output for LED applications up to +14V.
The MAX7360 features an automatic sleep mode and
automatic wakeup that further reduce supply current
consumption. The MAX7360 can be configured to enter
sleep mode after a programmable time following a key
event. The FIFO content is maintained and can be read
in sleep mode. The MAX7360 does not enter autosleep
when a key is held down. The autowake feature takes
To prevent overloading the microprocessor with too
many interrupts, interrupt requests are issued on a
programmable number of FIFO entries, and/or after a
set period of time (Table 10). The key-switch status is
checked by reading the key-switch FIFO. A 1-byte read
access returns both the next key event in the FIFO (if
there is one) and the FIFO status. INTK functions as an
open-drain general-purpose output (GPO) capable of
driving an LED if key-switch interrupts are not required.
Up to six of the key-switch outputs function as opendrain GPOs capable of driving additional LEDs when
the application requires fewer keys to be scanned. For
each key-switch output used as a GPO, the number of
monitored key switches reduces by eight.
the MAX7360 out of sleep mode following a keypress
event. Enable/disable autosleep and autowake through
the configuration register (Table 8).
Key inputs are scanned statically, not dynamically,
to ensure low-EMI operation. As inputs only toggle
in response to switch changes, the key matrix can be
routed closer to sensitive circuit nodes.
The key-scan controller debounces and maintains a FIFO
of keypress and release events (including autorepeated
keypresses, if autorepeat is enabled). Table 2 shows the
key-switch order. The user-programmable key-switch
debounce time, and autosleep timer, is derived from the
64kHz clock, which in turn is derived from the 128kHz
oscillator. Time delay for autorepeat and key-switch
interrupt is based on the key-switch debounce time.
Keys FIFO Register (0x00)
The keys FIFO register contains the information pertaining
to the status of the keys FIFO, as well as the key events
that have been debounced (see Table 7 in the Register Tables section). Bits D0–D5 denote which of the 64 keys
have been debounced and the keys are numbered as in
Table 1.
D7 indicates if there is more data in the FIFO, except
when D5:D0 indicate key 63 or key 62. When D5:D0
indicate key 63 or key 62, the host should read one more
time to determine whether there is more data in the FIFO.
Use key 62 and key 63 for rarely used keys. D6 indicates
if it is a keypress or release event, except when D5:D0
indicate key 63 or key 62.
Reading the key-scan FIFO clears the interrupt INTK
depending on the setting of bit D5 in the configuration
register (0x01).
Configuration Register (0x01)
The configuration register controls the I2C bus timeout
feature, enables key-release detection, enables autowake,
and determines how INTK is deasserted. Write to bit D7
to put the MAX7360 into sleep mode or operating mode.
Autosleep and autowake, when enabled, also change the
status of D7 (see Table 8 in the Register Tables section).
Debounce Register (0x02)
The debounce register sets the time for each debounce
cycle, as well as setting whether the GPO ports are
enabled or disabled. Bits D0–D4 set the debounce time
in increments of 1ms starting at 9ms and ending at 40ms
(see Table 9 in the Register Tables section). Bits D5, D6,
and D7 set which of the GPO ports is enabled. Note the
GPO ports are enabled only in the combinations shown
in Table 9, from all disabled to all enabled.
Key-Switch Interrupt Register (0x03)
The interrupt register contains information related to the
settings of the interrupt request function, as well as the
status of the INTK output, which can also be configured
as a GPO. If bits D0–D7 are set to 0x00, the INTK output
is configured as a GPO that is controlled by bit D1 in the
port register. There are two types of interrupts, the FIFObased interrupt and time-based interrupt. Set bits D0–D4
to assert interrupts at the end of the selected number of
debounce cycles following a key event (see Table 10 in
the Register Tables section). This number ranges from
1–31 debounce cycles. Setting bits D7, D6, and D5 set
the FIFO-based interrupt when there are 4–16 key events
stored in the FIFO. Both interrupts can be configured
simultaneously and INTK asserts depending on which
condition is met first. INTK deasserts depending on the
status of bit D5 in the configuration register.
Ports Register (0x04)
The ports register sets the values of PORT2–PORT7
and the INTK port, when configured, as open-drain
GPOs. The settings in this register are ignored for ports
not configured as GPOs, and a read from this register
returns the values stored in the register (see Table 11 in
the Register Tables section).
Autorepeat Register (0x05)
The MAX7360 autorepeat feature notifies the host that at
least one key has been pressed for a continuous period.
The autorepeat register enables or disables this feature,
sets the time delay after the last key event before the key
repeat code (0x7E) is entered into the FIFO, and sets
the frequency at which the key-repeat code is entered
into the FIFO thereafter. Bit D7 specifies whether the
autorepeat function is enabled with 0 denoting autorepeat
disabled, and 1 denoting autorepeat enabled. Bits D0–
D3 specify the autorepeat delay in terms of debounce
cycles ranging from 8–128 debounce cycles (see Table
12 in the Register Tables section). Bits D4, D5, and D6
specify the autorepeat rate or frequency ranging from
4–32 debounce cycles.
When autorepeat is enabled, holding the key pressed
results in a key-repeat event that is denoted by 0x7E. The
key being pressed does not show up again in the FIFO.
Only one autorepeat code is entered into the FIFO,
regardless of the number of keys pressed. The
autorepeat code continues to be entered in the FIFO at
the frequency set by bits D4–D1 until another key event
is recorded. Following the key-release event, if any keys
are still pressed, the MAX7360 restarts the autorepeat
sequence.
Autosleep Register (0x06)
Autosleep puts the MAX7360 in sleep mode to draw
minimal current. When enabled, the MAX7360 enters
sleep mode if no keys are pressed for the autosleep time
(see Table 13 in the Register Tables section).
Key-Switch Sleep Mode
In sleep mode, the MAX7360 draws minimal current.
Switch-matrix current sources are turned off and pulled
up to VCC. When autosleep is enabled, key-switch
inactivity for a period longer than the autosleep time
puts the part into sleep mode (FIFO data is maintained).
Writing a 1 to D7, or a keypress, can take the MAX7360
out of sleep mode. Bit D7 in the configuration register
gives the sleep-mode status and can be read any time.
The FIFO data is maintained while in sleep mode.
Keypresses initiate autowake and the MAX7360 goes into
operating mode. Keypresses that autowake the MAX7360
are not lost. When a key is pressed while the MAX7360
is in sleep mode, all analog circuitry, including switchmatrix current sources, turn on in 2ms. The initial key
needs to be pressed for 2ms plus the debounce time to
be stored in the FIFO. Write a 0 to D1 in the configuration
register (0x01) to disable autowakeup.
The MAX7360 has eight GPIO ports with LED control
functions. The ports can be used as logic inputs, logic
outputs, or constant-current PWM LED drivers. In
addition, PORT7 and PORT8 can function as a rotary
switch input pair. When in PWM mode, the ports are set
up to start their PWM cycle in 45N phase increments. This
prevents large current spikes on the LED supply voltage
when driving multiple LEDs.
GPIO Global Configuration Register (0x40)
The GPIO global configuration register controls the main
settings for the eight GPIOs (see Table 14 in the Register Tables section).
Bit D7 enables PORT[7:6] as inputs for a rotary switch.
Bit D5 enables interrupt generation for I2C timeouts.
D4 is the main enable/shutdown bit for the GPIOs. D3
functions as a software reset for the GPIO registers (0x40
to 0x5F). Bits D[2:0] set the fade in/out time for the GPIOs
configured as constant-current sinks.
GPIO Control Register (0x41)
The GPIO control register configures each port as either
an input or an output (see Table 15 in the Register Tables
section). All GPIOs allow individual configurations,
and power up as inputs. Enabling rotary switch mode
automatically sets D7 and D6 as inputs. The ports
consume additional current if their inputs are left undriven.
GPIO Debounce Configuration Register (0x42)
The GPIO debounce configuration register sets the
amount of time a GPIO must be held for the MAX7360
to register a logic transition (see Table 16 in the
Register Tables section). The GPIO debounce setting
is independent of the key-switch debounce setting. Five
bits (D[4:0]) set 32 possible debounce times from 9ms
up to 40ms.
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
GPIO Constant-Current Setting Register (0x43)
The GPIO constant-current setting register sets the global
constant-current amount (see Table 17 in the Register Tables section). Bits D1 and D0 set the global current
values from 5mA up to 20mA.
GPIO Output Mode Register (0x44)
The GPIO output mode register sets an output as either
a constant-current or non-constant-current output for
MAX7360
PORT[7:0] (see Table 18 in the Register Tables section).
Outputs are configured as constant-current outputs by
default to prevent accidental loading of an LED across
an unregulated output. The constant-current circuits
automatically turn off when not in use to reduce current
consumption.
Common PWM Register (0x45)
The common PWM register stores the common constantcurrent output PWM duty cycle (see Table 19 in the
Register Tables section). The values stored in this register
translate over to a PWM duty cycle in the same manner
as the individual PWM registers (0x50 to 0x57). Ports can
use their own individual PWM value, or the common PWM
value. Write to this register to change the duty cycle of
several ports at once.
Rotary Switch Configuration Register (0x46)
The rotary switch configuration register stores rotary
switch settings for PORT7 and PORT6 (see Table 20 in
the Register Tables section). D7 determines whether
switch counts or a time delay will trigger an interrupt
if enabled. D[6:4] set the count or time amount to wait
before sending an interrupt. Bits D[3:0] set the debounce
cycle time for the rotary switch inputs. Debounce time
ranges from 0 to 15ms.
I2C Timeout Flag Register (0x48) (Read Only)
The I2C timeout flag register contains a single bit (D0),
which indicates if an I2C timeout has occurred (see Table
21 in the Register Tables section). Read this register to
clear an I2C timeout initiated interrupt.
GPIO Input Register (0x49) (Read Only)
The GPIO input register contains the input data for all of
the GPIOs (see Table 22 in the Register Tables section).
Ports configured as outputs are read as high. There is
one debounce period delay prior to detecting a transition
on the input port. This prevents a false interrupt from
occurring when changing a port from an output to an
input. The GPIO input register reports the state of all
input ports regardless of any interrupt mask settings.
Ports configured as an input have a 2FA internal pullup
to VCC for PORT[5:0] and a 10FA internal pullup to VCC
for PORT[7:6].
Rotary Switch Count Register (0x4A) (Read Only)
The MAX7360 keeps a count of the rotary switch rotations
in two’s compliment format (see Table 23 in the Register Tables section). The register values wrap around as the
count value switches from a positive to a negative value
and back again. The count resets to zero after an I2C
read to this register.
PORT0–PORT7 Individual PWM Ratio Registers
(0x50 to 0x57)
Each port has an individual PWM ratio register (0x50 to
0x57, see Table 24 in the Register Tables section). Use
values 0x00 to 0xFE in these registers to configure the
number of cycles out of 256 the output sinks current
(LED is on), from 0 cycles to 254 cycles. Use 0xFF to
have an output continuously sink current (always on).
For applications requiring multiple ports to have the
same intensity, program a particular port’s configuration
register (0x58 to 0x5F) to use the common PWM register
(0x45). New PWM settings take place at the beginning of
a PWM cycle, to allow changes from common intensity to
individual intensity with no interruption in the PWM cycle
PORT0–PORT7 Configuration Registers
(0x58 to 0x5F)
Registers 0x58 to 0x5F set individual configurations for
each port (see Table 25 in the Register Tables section).
Bits D7 and D6 determine the interrupt settings for the
inputs. Interrupts can assert upon detection of a logic
transition, a rising edge, or not at all. D5 sets the port’s
PWM setting to either the common or individual PWM
setting. Bits D[4:2] enable and set the ports’ individual
blink period from 0 to 4096ms. Bits D1 and D0 set a port’s
blink duty cycle.
Fading
Set the fade cycle time in the GPIO global configuration
register (0x40) to a non-zero value to enable fade in/out (see
Table 14 in the Register Tables section). Fade in increases
an LED’s PWM intensity in 16 even steps from zero to its
stored value. Fade out decreases an LED’s PWM intensity in
16 even steps from its current value to zero. Fading occurs
automatically in any of the following scenarios:
1) Change the common PWM register value from any
value to zero to cause all ports using the common
PWM register settings to fade out. No ports using
individual PWM settings are affected.
2) Change the common PWM register value to any value
from zero to cause all ports using the common PWM
register settings to fade in. No ports using individual
PWM settings are affected.
3) Put the part out of shutdown to cause all ports to
fade in. Changing an individual PWM intensity during
fade in automatically cancels that port’s fade and
immediately output at its newly programmed intensity.
4) Put the part into shutdown to cause all ports to fade
out. Changing an individual PWM intensity during
fade out automatically cancels that port’s fade and
immediately turns off.
Blink
Each port has its own blink control settings through
registers 0x58 to 0x5F (see Table 25 in the Register Tables
section). The blink period ranges from 0 (blink disabled)
to 4.096s. Settable blink duty cycles range from 6.25%
to 50%. All blink periods start at the same PWM cycle for
synchronized blinking between multiple ports.
GPIO Port Interrupts (INTI)
Three possible sources generate INTI: I2C timeout,
GPIOs configured as inputs, and the rotary switch
(registers 0x48, 0x49, and 0x4A). Read the respective
data/status registers for each type of interrupt to clear
INTI. Set register 0x46 for rotary switch-based interrupts.
PORT7
PORT6
PORT7
PORT6
ROTARY SWITCH
DEBOUNCE
Figure 1. Rotary Switch Input Signal Timing
INCREMENT
DECREMENT
Set registers 0x58 to 0x5F for individual GPI-based
interrupts. If multiple sources generate the interrupt, all
the related status registers must be read to clear INTI.
Rotary Switch
The MAX7360 can accept a 2-bit rotary switch inputs on
PORT6 and PORT7. Rotation of the switch in a clockwise
direction increments the count. Enable rotary switch
mode from the GPIO global configuration register (0x40).
Several settings for PORT6 and PORT7 occur during
rotary switch mode:
1) Each port has a 10FA pullup to VCC.
2) Register 0x46 sets the debounce time.
3) A debounced rising edge on PORT6 while PORT7 is
high decreases the count.
4) A debounced rising edge on PORT6 while PORT7 is
low increases the count.
For more details, see Figure 1.
Serial Interface
Figure 2 shows the 2-wire serial interface timing details.
Serial Addressing
The MAX7360 operates as a slave that sends and
receives data through an I2C-compatible 2-wire interface.
The interface uses a serial-data line (SDA) and a serialclock line (SCL) to achieve bidirectional communication
between master(s) and slave(s). A master (typically a
microcontroller) initiates all data transfers to and from the
MAX7360 and generates the SCL clock that synchronizes
the data transfer.
The MAX7360’s SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kI,
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
is required on SDA. The MAX7360’s SCL line operates
only as an input. A pullup resistor is required on SCL if
there are multiple masters on the 2-wire interface, or if
the master in a single-master system has an open-drain
SCL output.
Each transmission consists of a START condition (Figure
3) sent by a master, followed by the MAX7360 7-bit slave
address plus R/W bit, a register address byte, one or
MAX7360
more data bytes, and finally, a STOP condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from
high to low while SCL is high. When the master has
finished communicating with the slave, it issues a STOP
(P) condition by transitioning SDA from low to high while
SCL is high. The bus is then free for another transmission.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 4). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 4), which
the recipient uses to handshake receipt of each byte of
data. Thus, each byte transferred effectively requires
9 bits. The master generates the 9th clock pulse, and
the recipient pulls down SDA during the acknowledge
clock pulse; therefore, the SDA line is stable low during
the high period of the clock pulse. When the master is
transmitting to the MAX7360, the MAX7360 generates the
acknowledge bit because the MAX7360 is the recipient.
When the MAX7360 is transmitting to the master, the
master generates the acknowledge bit because the
master is the recipient.
The MAX7360 has a 7-bit long slave address (Figure
6). The bit following a 7-bit slave address is the R/W bit,
which is low for a write command and high for a read
command.
The first 4 bits (MSBs) of the MAX7360 slave address
dynamic signals, care must be taken to ensure that AD0
transitions no sooner than the signals on SDA and SCL.
The MAX7360 monitors the bus continuously, waiting for a
START condition, followed by its slave address. When the
MAX7360 recognizes its slave address, it acknowledges
and is then ready for continued communication.
are always 0111. Slave address bits A3, A2, and A1
correspond, by the matrix in Table 3, to the states of the
device address input AD0, and A0 corresponds to the
R/W bit. The AD0 input can be connected to any of four
signals (GND, VCC, SDA, or SCL), giving four possible
slave address pairs and allowing up to four MAX7360
devices to share the bus. Because SDA and SCL are
The MAX7360 features a 20ms minimum bus timeout
on the 2-wire serial interface, largely to prevent the
MAX7360 from holding the SDA I/O low during a read
transaction should the SCL lock up for any reason before
a serial transaction is completed. Bus timeout operates
by causing the MAX7360 to internally terminate a serial
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
D7 D6 D5 D4 D3 D2 D1 D0D1 D0D3 D2D5 D4D7 D6
ACKNOWLEDGE FROM MAX7360
SAAAP0SLAVE ADDRESSCOMMAND BYTEDATA BYTE
R/W
MAX7360
Figure 9. N Data Bytes Received
Table 4. Autoincrement Rules
REGISTER
FUNCTION
Keys FIFO0x000x00
Autoshutdown0x060x00
All other key switch0x01 to 0x05Addr + 0x01
All other GPIO0x40 to 0x5FAddr + 0x01
transaction, either read or write, if SCL low exceeds
20ms. After a bus timeout, the MAX7360 waits for a valid
START condition before responding to a consecutive
transmission. This feature can be enabled or disabled
under user control by writing to the configuration register
(Table 8 in the Register Tables section).
A write to the MAX7360 comprises the transmission of the
slave address with the R/W bit set to zero, followed by at
least 1 byte of information. The first byte of information
is the command byte. The command byte determines
which register of the MAX7360 is to be written by the next
byte, if received. If a STOP condition is detected after the
command byte is received, the MAX7360 takes no further
action (Figure 7) beyond storing the command byte.
Any bytes received after the command byte are data bytes.
The first data byte goes into the internal register of the
MAX7360 selected by the command byte (Figure 8).
If multiple data bytes are transmitted before a STOP condition
is detected, these bytes are generally stored in subsequent
MAX7360 internal registers, because the command byte
address generally autoincrements (Table 4).
The MAX7360 is read using the internally stored
command byte as an address pointer, the same way the
stored command byte is used as an address pointer for
a write. The pointer generally autoincrements after each
data byte is read using the same rules as for a write
ADDRESS
CODE (hex)
AUTOINCREMENT
ADDRESS (hex)
Message Format for Writing
the Key-Scan Controller
Message Format for Reading
the Key-Scan Controller
ACKNOWLEDGE FROM MAX7360
(Table 4). Thus, a read is initiated by first configuring the
MAX7360’s command byte by performing a write (Figure
6). The master can now read n consecutive bytes from
the MAX7360, with the first data byte being read from
the register addressed by the initialized command byte.
When performing read-after-write verification, remember
to reset the command byte’s address, because the stored
command byte address is generally autoincremented
after the write (Figure 9, Table 4).
When the MAX7360 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7360 uses a
repeated start between the write that sets the MAX7360’s
address pointer, and the read(s) that takes the data
from the location(s). This is because it is possible for
master 2 to take over the bus after master 1 has set up
the MAX7360’s address pointer, but before master 1
has read the data. If master 2 subsequently resets the
MAX7360’s address pointer, master 1’s read can be from
an unexpected location.
Address autoincrementing allows the MAX7360 to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be sent.
The command address stored in the MAX7360 generally
increments after each data byte is written or read (Table
4). Autoincrement only works when doing a multiburst
read or write.
Applications Information
After a catastrophic event such as ESD discharge or
microcontroller reset, use bit D7 of the configuration
register (0x01) as a software reset for the key-switch
state (the key-switch register values and FIFO remain
unaffected). Use bit D4 of the GPIO global configuration
register (0x40) as a software reset for the GPIOs.
Ghost keys are a phenomenon inherent with key-switch
matrices. When three switches located at the corners
of a matrix rectangle are pressed simultaneously, the
switch that is located at the last corner of the rectangle
(the ghost key) also appears to be pressed. This occurs
because the potentials at the two sides of the ghost-key
switch are identical due to the other three connections—
the switch is electrically shorted by the combination of
the other three switches (Figure 10). Because the key
appears to be pressed electrically, it is impossible to
detect which of the four keys is the ghost key.
The MAX7360 employs a proprietary scheme that detects
any three-key combination that generates a fourth ghost
key, and does not report the third key that causes a
ghost-key event. This means that although ghost keys
are never reported, many combinations of three keys
are effectively ignored when pressed at the same time.
Applications requiring three-key combinations (such
as <Ctrl><Alt><Del>) must ensure that the three keys
are not wired in positions that define the vertices of a
rectangle (Figure 11). There is no limit on the number of
keys that can be pressed simultaneously as long as the
keys do not generate ghost-key events and FIFO is not full.
Low-EMI Operation
The MAX7360 uses two techniques to minimize EMI
radiating from the key-switch wiring. First, the voltage
across the switch matrix never exceeds +0.55V if not in
sleep mode, independent of supply voltage VCC. This
reduces the voltage swing at any node when a switch
is pressed to +0.55V maximum. Second, the keys are
not dynamically scanned, which would cause the keyswitch wiring to continuously radiate interference.
Instead, the keys are monitored for current draw (only
occurs when pressed), and debounce circuitry only
operates when one or more keys are actually pressed.
KEY-SWITCH MATRIXKEY-SWITCH MATRIX
Figure 11. Valid Three-Key Combinations
Switch On-Resistance
The MAX7360 is designed to be insensitive to resistance,
either in the key switches, or the switch routing to and
from the appropriate COL_ and ROW_ up to 4kI (max).
These controllers are therefore compatible with low-cost
membrane and conductive carbon switches.
Hot Insertion
The INTI, INTK, SCL, and AD0 inputs and SDA remain
high impedance with up to +3.6V asserted on them when
the MAX7360 powers down (VCC = 0). I/O ports (PORT0–
PORT7) remain high impedance with up to +14V asserted
on them when not powered. Use the MAX7360 in hot-
swap applications.
Staggered PWM
The LED’s on-time in each PWM cycle are phase
delayed 45N into eight evenly spaced start positions.
Optimize phasing when using fewer than eight ports as
constant-current outputs by allocating the ports with the
most appropriate start positions. For example, if using
four constant-current outputs, choose PORT0, PORT2,
PORT4, and PORT6 because their PWM start positions
are evenly spaced. In general, choose the ports that
spread the PWM start positions as evenly as possible.
This optimally spreads out the current demand from the
ports’ load supply.
INTK/INTI
There are two interrupt outputs, INTK and INTI. Each
interrupt operates independently from the other. See
the Key-Switch Interrupt Register (0x03) and the GPIO
Port Interrupts (INTI) sections for additional information
regarding these two interrupts.
Power-Supply Considerations
The MAX7360 operates with a +1.62V to +3.6V power-
supply voltage. Bypass the power supply to GND with a
0.1FF or higher ceramic capacitor as close as possible
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
ESD Protection
All of the MAX7360 pins meet the 2kV Human Body Model
ESD tolerances. Key-switch inputs and GPIOs meet IEC
61000-4-2 ESD protection. The IEC test stresses consist
of 10 consecutive ESD discharges per polarity, at the
maximum specified level and below (per IEC 61000-4-2).
Test criteria include:
1) The powered device does not latch up during the
MAX7360
ESD discharge event.
2) The device subsequently passes the final test used
for prescreening.
Tables 5 and 6 are from the IEC 61000-4-2: Edition 1.1
1999-05: Electromagnetic compatibility (EMC) Testing
and measurement techniques—Electrostatic discharge
immunity test
Table 6. ESD Waveform Parameters
INDICATED
LEVEL
127.50.7 to 142
24150.7 to 184
3622.50.7 to 1126
48300.7 to 1168
VOLTGE
(kV)
FIRST PEAK OF
CURRENT
DISCHARGE ±10%
(A)
Table 5. ESD Test Levels
1A—CONTACT
DISCHARGE
LEVEL
1212
2424
3638
48410
XSpecialXSpecial
X = Open level. The level has to be specified in the
dedicated equipment specification. If higher voltages
than those shown are specified, special test equipment
could be needed.
The key number indicated by D5:D0 is a key
event. D7 is always for a key press of key 62
and key 63. When D7 is 0, the key read is the
last data in the FIFO. When D7 is 1, there is
more data in the FIFO. When D6 is 1, key data
read from FIFO is a key release. When D6 is 0,
key data read from FIFO is a key press.
FIFO is empty.00111111
FIFO is overflow. Continue to read data in FIFO.01111111
Key 63 is pressed. Read one more time to
determine whether there is more data in FIFO.
Key 63 is released. Read one more time to
determine whether there is more data in FIFO.
Key repeat. Indicates the last data in FIFO.00111110
Key repeat. Indicates more data in FIFO.01111110
Key 62 is pressed. Read one more time to
determine whether there is more data in FIFO.
Key 62 is released. Read one more time to
determine whether there is more data in FIFO.
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 8. Configuration Register Format (0x01)
REGISTER
BIT
MAX7360
D7Sleep
D6Reserved0—0
D5Interrupt
D4Reserved0—0
D3
D2Reserved0—0
D1
D0
DESCRIPTIONVALUEFUNCTION
Key-release
enable
Autowakeup
enable
Timeout
disable
X
(when 0x40
D4 = 1)
0
(when 0x40
D4 = 0)
1
(when 0x40
D4 = 0)
0
1
0Disable key releases
1Enable key releases
0Disable keypress wakeup
1Enable keypress wakeup
0
1
Key-switch operating mode. Key switches always remain active
when constant-current PWM is enabled (bit 4 of register 0x40 is
high) regardless of autosleep, autowakeup, or an I2C write to this bit.
Key-switch sleep
mode. The entire
chip is shut down.
Key-switch operating
mode
INTK cleared when FIFO is empty
INTK cleared after host read. In this mode, I2C should read the
FIFO until interrupt condition is removed or further INT may be lost.
I2C timeout enabled
I2C timeout disabled
When constant-current PWM is disabled
(bit 4 of register 0x40 is low), I2C write,
autosleep, and autowakeup all can change
this bit. This bit can be read back by I2C
any time for current status.
Table 9. Debounce Register Format (0x02) (continued)
REGISTER DATA
REGISTER DESCRIPTION
GPO ports 7, 6, and 5 enabled011XXXXX
GPO ports 7, 6, 5, and 4 enabled100XXXXX
GPO ports 7, 6, 5, 4, and 3 enabled101XXXXX
GPO ports 7, 6, 5, 4, 3, and 2 enabled11XXXXXX
Power-up default setting11111111
Table 10. Key-Switch Interrupt Register Format (0x03)
REGISTER DESCRIPTION
INTK used as GPO
FIFO-based INTK disabled
INTK asserts every debounce cycle
INTK asserts every 2 debounce cycles
D7D6D5D4D3D2D1D0
PORTS ENABLEDEBOUNCE TIME
REGISTER DATA
D7D6D5D4D3D2D1D0
FIFO-BASED INTKTIME-BASED INTK
00000000
000Not all zero
00000001
00000010
MAX7360
.
.
.
INTK asserts every 29 debounce cycles
INTK asserts every 30 debounce cycles
INTK asserts every 31 debounce cyclesTime-based INTK disabled
INTK asserts when FIFO has 2 key events
INTK asserts when FIFO has 4 key events
INTK asserts when FIFO has 6 key events
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 13. Autosleep Register Format (0x06)
REGISTERREGISTER DATA
AUTOSLEEP REGISTER
No Autosleep00000000
Autosleep for (ms)
819200000001
MAX7360
409600000010
204800000011
102400000100
51200000101
25600000110
25600000111
Power-up default settings00000111
D7D6D5D4D3D2D1D0
Table 14. GPIO Global Configuration Register (0x40)
REGISTER
BIT
D7
D6Reserved0—0
D5
D4GPIO enable
D3GPIO reset
D[2:0]
DESCRIPTIONVALUEFUNCTION
PORT6/PORT7
rotary switch
I2C timeout
interrupt
enable
Fade in/out
time
0PORT6/PORT7 operate as GPIOs
1PORT6/PORT7 operate as a rotary switch input
0Disabled
1
0
1
0Normal operation
1
000No fading
XXX
INTI is asserted when I2C bus times out. INTI is deasserted when a
read is performed on the I2C timeout flag register (0x48).
PWM, constant-current circuits, and GPIs are shut down. GPO
values depend on their setting. Register 0x41 to 0x5F values are
stored and cannot be changed. The entire part is shut down if the
key switches are in sleep mode (D7 of register 0x01).
Normal GPIO operation. PWM, constant-current circuits, and GPIOs are
enabled regardless of key-switch sleep mode state (see Table 8).
Return all GPIO registers (registers 0x40 to 0x5F) to their POR value.
This bit is momentary and resets itself to 0 after the write cycle.
PWM intensity ramps up (down) between the common PWM value
and 0% duty cycle in 16 steps over the following time period:
D[2:0] = 001 = 256ms
D[2:0] = 010 = 512ms
D[2:0] = 011 = 1024ms
D[2:0] = 100 = 2048ms
D[2:0] = 101 = 4096ms
D[2:0] = 110/111 = Undefined
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 21. I2C Timeout Flag Register (0x48) (Read Only)
REGISTER
BIT
D[7:1]Reserved0000000—0000000
D0
MAX7360
DESCRIPTIONVALUEFUNCTION
I2C timeout flag
0
1
No I2C timeout has occurred since last read or POR
I2C timeout has occurred since last read or POR. This bit is reset to
zero when a read is performed on this register. I2C timeouts must
be enabled for this function to work (see Table 8).
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
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