The MAX7311 2-wire-interfaced expander provides 16bit parallel input/output (I/O) port expansion for
SMBus™-compatible and I2C-compatible applications.
The MAX7311 consists of input port registers, output
port registers, polarity inversion registers, configuration
registers, a bus timeout register, and an SMBus/I2Ccompatible serial interface. The system master can
invert the MAX7311 input data by writing to the activehigh polarity inversion register. The system master can
enable or disable bus timeout by writing to the bus
timeout register.
Any of the 16 I/O ports can be configured as an input or
output. A power-on reset (POR) initializes the 16 I/Os
as inputs. Three address select pins configure one of
64 slave ID addresses.
The MAX7311 is available in 24-pin SO, SSOP, TSSOP,
and thin QFN packages and is specified over the -40°C
to +125°C automotive temperature range.
Applications
Servers
RAID Systems
Industrial Control
Medical Equipment
PLCs
Instrumentation and Test Measurement
Features
♦ 400kbps I2C-Compatible Serial Interface
♦ 2V to 5.5V Operation
♦ 5V Overvoltage Tolerant I/Os
♦ 16 I/O Pins that Default to Inputs on Power-Up
♦ Open-Drain Interrupt Output (INT)
(V+= 2V to 5.5V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at V+= 3.3V, TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+to GND ................................................................-0.3V to +6V
I/O0–I/O15 as Inputs ....................................(GND - 0.3V) to +6V
SCL, SDA, AD0, AD1, AD2, INT...................(GND - 0.3V) to +6V
Maximum V
+
Current ......................................................+250mA
Maximum GND Current ...................................................-250mA
DC Input Current on I/O0–I/O15 .......................................±20mA
DC Output Current on I/O0–I/O15 ....................................±80mA
Continuous Power Dissipation (T
A
= +70°C)
24-Pin Wide SO (derate 11.8mW/°C above +70°C) ....941mW
Note 1: All parameters are 100% production tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Minimum SCL clock frequency is limited by the MAX7311 bus timeout feature, which resets the serial bus interface if either
SDA or SCL is held low for a minimum of 25ms. Disable bus timeout feature for DC operation.
Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IL
of the SCL
signal) in order to bridge the undefined region SCL’s falling edge.
Note 4: C
B
= total capacitance of one bus line in pF.
Note 5: The maximum t
F
for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tFis
specified at 250ns. This allows series protection resistors to be connected between the SDA and SCL pins and the
SDA/SCL bus lines without exceeding the maximum specified t
F
.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
DC ELECTRICAL CHARACTERISTICS (continued)
(V+= 2V to 5.5V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at V+= 3.3V, TA= +25°C.) (Note 1)
AC ELECTRICAL CHARACTERISTICS
(V+= 2V to 5.5V, TA= -40°C to +125°C, unless otherwise noted.) (Note 1)
Leakage Current-1+1µA
Input Capacitance4pF
INT
Low-Level Output CurrentI
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
V
OL
= 0.4V6mA
OL
SCL Clock Frequencyf
Bus Timeoutt
Bus Free Time Between STOP
and START Conditions
Hold Time (Repeated) START
Condition
Repeated START Condition
Setup Time
STOP Condition Setup Timet
Data Hold Timet
Data Setup Timet
SCL Low Periodt
SCL High Periodt
SDA Fall Timet
Pulse Width of Spike Suppressedt
PORT TIMING
Output Data Validt
Input Data Setup Time27µs
Input Data Hold Time0µs
INTERRUPT TIMING
Interrupt Validt
Interrupt Resett
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
SCL
TIMEOUT
t
BUF
t
HD,STA
t
SU,STA
SU,STO
HD,DAT
SU,DAT
LOW
HIGH
SP
PV
IR
(Note 2)400kHz
2961ms
Figure 21.3µs
Figure 20.6µs
Figure 20.6µs
Figure 20.6µs
Figure 2 (Note 3)0.9µs
Figure 2100ns
Figure 21.3µs
Figure 20.7µs
Figure 2 (Notes 4, 5)
F
(Note 6)50ns
Figure 73µs
Figure 930.5µs
IV
Figure 92µs
V+ < 3.3V500
V+ ≥ 3.3V250
ns
MAX7311
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt
Supply Voltage. Bypass with a 0.047µF capacitor to GND.
MAX7311
Detailed Description
The MAX7311 general-purpose input/output (GPIO)
peripheral provides up to 16 I/O ports, controlled
through an I2C-compatible serial interface. The
MAX7311 consists of input port registers, output port
registers, polarity inversion registers, configuration registers, and a bus-timeout register. Upon power-on, all
I/O lines are set as inputs. Three slave ID address select
pins, AD0, AD1, and AD2, choose one of 64 slave ID
addresses, including the eight addresses supported by
the Phillips PCA9555. Table 1 is the register address
table. Tables 2–6 show detailed register information.
Serial Interface
Serial Addressing
The MAX7311 operates as a slave that sends and
receives data through a 2-wire interface. The interface
uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master, typically a microcontroller, initiates all data transfers to and from the
MAX7311, and generates the SCL clock that synchronizes the data transfer (Figure 2).
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt
Each transmission consists of a START condition sent by
a master, followed by the MAX7311 7-bit slave address
plus R/W bit, a register address byte, 1 or more data
bytes, and finally a STOP condition (Figure 3).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit, which the
recipient uses as a handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When
the master is transmitting to the MAX7311, the
MAX7311 generates the acknowledge bit since the
MAX7311 is the recipient. When the MAX7311 is transmitting to the master, the master generates the
acknowledge bit.
Slave Address
The MAX7311 has a 7-bit-long slave address (Figure 6).
The 8th bit following the 7-bit slave address is the R/W
bit. Set this bit low for a write command and high for a
read command.
Slave address pins AD2, AD1, and AD0 choose 1 of 64
slave ID addresses (Table 7).
Data Bus Transaction
The command byte is the first byte to follow the 8-bit
device slave address during a write transmission
(Table 1, Figure 7). The command byte is used to determine which of the following registers are written or read.
Writing to Port Registers
Transmit data to the MAX7311 by sending the device
slave address and setting the LSB to a logic zero. The
command byte is sent after the address and determines which registers receive the data following the
command byte (Figure 7).
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt
0xFFFactory reserved. (Do not write to this register.)——
PROGRAMMABLE
ACKR/W
FUNCTIONPROTOCOL
POWER-UP
DEFAULT
SCL
123456789
COMMAND BYTEPORT 1 DATAPORT 2 DATA
SDA
SA000000176543210A76543210A0A
SLAVE ADDRESS
START
CONDITION
WRITE TO PORT
DATA OUT PORT 1
READ FROM PORT 2
R/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
t
PV
ACKNOWLEDGE
FROM SLAVE
t
PV
Eight of the MAX7311’s nine registers are configured to
operate as four register pairs: input ports, output ports,
polarity inversion ports, and configuration ports. After
sending 1 byte of data to one register, the next byte is
sent to the other register in the pair. For example, if the
first byte of data is sent to output port 2, then the next
byte of data is stored in output port 1. An unlimited
number of data bytes can be sent in one write transmission. This allows each 8-bit register to be updated independently of the other registers.
Reading Port Registers
To read the device data, the bus master must first send
the MAX7311 address with the R/W bit set to zero, followed by the command byte, which determines which
register is accessed. After a restart, the bus master
must then send the MAX7311 address with the R/W bit
set to 1. Data from the register defined by the command byte is then sent from the MAX7311 to the master
(Figures 8, 9).
TRANSFER OF DATA CAN BE STOPPED ANYTIME BY A STOP CONDITION. WHEN THE
STOP CONDITION OCCURS, DATA PRESENT AT THE LAST ACKNOWLEDGE PHASE IS
VALID (OUTPUT MODE) AND COMMAND BYTE HAS PREVIOUSLY BEEN SET TO REGISTER 00.
t
IR
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM MASTER
NONACKNOWLEDGE
FROM MASTER
MAX7311
Data is clocked into a register on the falling edge of the
acknowledge clock pulse. After reading the first byte,
additional bytes may be read and reflect the content in
the other register in the pair. For example, if input port 1
is read, the next byte read is input port 2. An unlimited
number of data bytes can be read in one read transmission, but the final byte received must not be
acknowledged by the bus master.
Interrupt (
INT
)
The open-drain interrupt output, INT, activates when
one of the port pins changes states and only when the
pin is configured as an input. The interrupt deactivates
when the input returns to its previous state or the input
register is read (Figure 9). A pin configured as an output does not cause an interrupt. Each 8-bit port register
is read independently; therefore, an interrupt caused
by port 1 is not cleared by a read of port 2’s register.
Changing an I/O from an output to an input may cause
a false interrupt to occur if the state of that I/O does not
match the content of the input port register.
Input/Output Port
When an I/O is configured as an input, FETs Q1 and Q2
are off (Figure 10), creating a high-impedance input with
a nominal 100kΩ pullup to V+. All inputs are overvoltage
protected to 5.5V, independent of supply voltage. When
a port is configured as an output, either Q1 or Q2 is on,
depending on the state of the output port register. When
V+powers up, an internal power-on reset sets all registers to their respective defaults (Table 1).
Input Port Registers
The input port registers (Table 2) are read-only ports.
They reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or
an output by the respective configuration register. A
read of the input port 1 register latches the current
value of I/O0–I/O7. A read of the input port 2 register
latches the current value of I/O8–I/O15. Writes to the
input port registers are ignored.
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt
The output port registers (Table 3) set the outgoing
logic levels of the I/Os defined as outputs by the
respective configuration register. Reads from the output port registers reflect the value that is in the flip-flop
controlling the output selection, not the actual I/O value.
Polarity Inversion Registers
The polarity inversion registers (Table 4) enable polarity
inversion of pins defined as inputs by the respective
port configuration registers. Set the bit in the polarity
inversion register to invert the corresponding port pin’s
polarity. Clear the bit in the polarity inversion register to
retain the corresponding port pin’s original polarity.
Configuration Registers
The configuration registers (Table 5) configure the
directions of the I/O pins. Set the bit in the respective
configuration register to enable the corresponding port
as an input. Clear the bit in the configuration register to
enable the corresponding port as an output.
Bus Timeout
Set register 0x08 LSB (bit 0) to enable the bus timeout
function (Table 6) or clear it to disable the bus timeout
function. Enabling the timeout feature resets the
MAX7311 serial bus interface when SCL stops either high
or low during a read or write. If either SCL or SDA is low
for more than 29ms after the start of a valid serial transfer,
the interface resets itself and sets up SDA as an input.
The MAX7311 then waits for another START condition.
Standby
The MAX7311 goes into standby when the I2C bus is
idle. Standby supply current is typically 2.9µA.
Applications Information
Power-Supply Consideration
The MAX7311 operates from a supply voltage of 2V to
5.5V. Bypass the power supply to GND with a 0.047µF
capacitor as close to the device as possible.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
e
D
12
MAX
0.078
0.008
0.015
0.008
0.212
0.311
0.037
8∞
MILLIMETERS
MAX
MIN
1.731.99
0.21
0.05
0.38
0.25
0.20
0.09
5.38
5.20
0.65 BSC
7.65
7.90
0.63
0.95
0∞
8∞
MAX
0.249
0.249
0.289
0.328
0.407
MILLIMETERS
MAX
MIN
6.07
6.33
6.07
6.33
7.07
7.33
8.07
8.33
10.07
10.33
N
14L
16L
20L
24L
28L
C
INCHES
MIN
D
0.239
D
0.239
D
0.278
D
0.317
0.397
D
INCHES
DIM
MIN
A
0.068
A1
0.002
B
0.010
C
HE
N
A
B
A1
D
E
e
H
L
0.004
SEE VARIATIONS
0.205
0.0256 BSC
0.301
0.025
0∞
L
SSOP.EPS
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
21-0056
REV.DOCUMENT CONTROL NO.APPROVAL
1
C
1
MAX7311
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
TSSOP4.40mm.EPS
MAX7311
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
24L QFN THIN.EPS
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139A
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
A21-0139
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