For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX7034 fully integrated low-power CMOS superheterodyne receiver is ideal for receiving amplitudeshift-keyed (ASK) data in the 300MHz to 450MHz
frequency range (including the popular 315MHz and
433.92MHz frequencies). The receiver has an RF sensitivity of -114dBm. With few external components and a
low-current power-down mode, it is ideal for cost-sensitive and power-sensitive applications typical in the
automotive and consumer markets. The MAX7034 consists of a low-noise amplifier (LNA), a fully differential
image-rejection mixer, an on-chip phase-locked loop
(PLL) with integrated voltage-controlled oscillator
(VCO), a 10.7MHz IF limiting amplifier stage with
received-signal-strength indicator (RSSI), and analog
baseband data-recovery circuitry.
The MAX7034 is available in a 28-pin TSSOP package
and is specified over the automotive (-40°C to +125°C)
temperature range.
Features
♦ Optimized for 315MHz or 433.92MHz Band
♦ Operates from Single +5.0V Supply
♦ Selectable Image-Rejection Center Frequency
♦ Selectable x64 or x32 f
LO/fXTAL
Ratio
♦ Low (< 6.7mA) Operating Supply Current
♦ < 3.0µA Low-Current Power-Down Mode for
Efficient Power Cycling
♦ 250µs Startup Time
♦ Built-In 44dB RF Image Rejection
♦ Excellent Receive Sensitivity Over Temperature
♦ -40°C to +125°C Operation
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
________________________________________________________________
Maxim Integrated Products
1
Pin Configuration
Ordering Information
Applications
19-3109; Rev 0; 1/08
+
Denotes a lead-free package.
T = Tape-and-reel.
Typical Application Circuit appears at end of data sheet.
Automotive Remote
Keyless Entry
Security Systems
Garage Door Openers
Home Automation
Remote Controls
Local Telemetry
Wireless Sensors
PART TEMP RANGE
MAX7034AUI+T -40°C to +125°C
PINPACKAGE
28 TSSOP
(9.7mm x
4.4mm)
PKG
CODE
U28-1
TOP VIEW
XTAL1
LNAIN
LNASRC
AGND
LNAOUT
MIXIN1
MIXIN2
AGND
MIXOUT
DGND
AV
AV
IRSEL
DV
+
1
2
DD
3
4
5
MAX7034
6
7
DD
8
9
10
11
12
13
14
DD
TSSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
XTAL2
SHDN
PDOUT
DATAOUT
V
DD5
DSP
DFFB
OPP
DSN
DFO
IFIN2
IFIN1
XTALSEL
EN_REG
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(
Typical Application Circuit
, V
DD5
= +4.5V to +5.5V, no RF signal applied. TA= -40°C to +125°C, unless otherwise noted. Typical val-
ues are at V
DD5
= +5.0V and TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
DD5
to AGND.......................................................-0.3V to +6.0V
AV
DD
to AGND ......................................................-0.3V to +4.0V
DV
DD
to DGND......................................................-0.3V to +4.0V
AGND to DGND.....................................................-0.1V to +0.1V
IRSEL, DATAOUT, XTALSEL,
SHDN, EN_REG to AGND ....................-0.3V to (V
DD5
+ 0.3V)
All Other Pins to AGND............................-0.3V to (DV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
28-Pin TSSOP (derate 12.8mW/°C above +70°C) ..1025.6mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Supply Voltage V
Supply Current I
Shutdown Supply Current I
Input-Voltage Low V
Input-Voltage High V
Input Logic Current High I
Image-Reject Select Voltage
(Note 2)
DATAOUT Output-Voltage Low V
DATAOUT Output-Voltage High V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DD5
DD
SHDN
IH
OL
OH
+5.0V nominal supply voltage 4.5 5.0 5.5 V
fRF = 315MHz 6.7 8.2
fRF = 434MHz 7.2 8.7
= D V
IRSEL
IRSEL
IRSEL
D D
= D V
= 0V 0.4
/2 1.1
D D
IL
IH
V
= V
SHDN
V
SHDN
EN_REG, SHDN
XTALSEL
fRF = 434MHz, V
fRF = 375MHz, V
f
RF
I
SINK
I
SOURCE
DD5
= 0V 3 8 µA
= 315MHz, V
= 10µA 0.125 V
= 10µA
V
DD5
D V
D V
0.4
D D
0.4
D D
0.4
-
-
15 µA
-
V
-
D D 5
0.125
0.4 V
D V
-
D D
1.5
mA
V
V
V
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(
Typical Application Circuit
, V
VDD5
= +4.5V to +5.5V, all RF inputs are referenced to 50Ω, fRF= 433.92MHz, TA= -40°C to +125°C,
unless otherwise noted. Typical values are at V
VDD5
= +5.0V and TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL CHARACTERISTICS
Startup Time t
Receiver Input Frequency Range f
Maximum Receiver Input Level 0 dBm
Sensitivity at TA = +25oC (Note 3)
Sensitivity at TA = +125°C
(Note 3)
Maximum Data Rate
LNA/MIXER
LNA/Mixer Voltage Gain (Note 4) 330Ω IF filter load 45 dB
LNA/Mixer Input-Referred 1dB
Compression Point
Mixer Output Impedance Z
Mixer Image Rejection
INTERMEDIATE FREQUENCY (IF)
Input Impedance Z
Operating Frequency f
3dB Bandwidth 10 MHz
RSSI Linearity ±0.5 dB
RSSI Dynamic Range 80 dB
RSSI Level
ON
RF
OUT_MIX
IN_IF
IF
Time for valid signal detection after V
= V
. Does not include baseband filter
DD5
settling.
+25°C, 315MHz -114
+25°C, 434MHz -113
+125°C, 315MHz -113
+125°C, 434MHz -110
Manchester coded 33
NRZ coded 66
fRF = 434MHz, V
fRF = 375MHz, V
= 315MHz, V
f
RF
Bandpass response 10.7 MHz
P
< -120dBm 1.15
RFIN
P
> -40dBm 2.2
RFIN
= DV
IRSEL
IRSEL
IRSEL
DD
= DVDD/2 44
= 0V 44
SHDN
250 µs
300 450 MHz
-50 dBm
330 Ω
42
330 Ω
dBm
dBm
kbps
dB
V
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
4 _______________________________________________________________________________________
Note 1: 100% tested at TA= +125°C. Guaranteed by design and characterization over entire temperature range.
Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image-rejection setting is desired. Bypass
to AGND with a 1nF capacitor in a noisy environment.
Note 3: Peak power level. BER = 2 x 10
-3
, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz.
Note 4: The voltage conversion gain is measured with the LNA input matching inductor and the LNA/Mixer resonator in place, and
does not include the IF filter insertion loss.
Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (f
RF
- 10.7MHz)/64 for
XTALSEL = 0V, and (f
RF
- 10.7MHz)/32 for XTALSEL = DVDD.
AC ELECTRICAL CHARACTERISTICS (continued)
(
Typical Application Circuit
, V
VDD5
= +4.5V to +5.5V, all RF inputs are referenced to 50Ω, fRF= 433.92MHz, TA= -40°C to +125°C,
unless otherwise noted. Typical values are at V
VDD5
= +5.0V and TA= +25°C.) (Note 1)
DATA FILTER
Maximum Bandwidth 50 kHz
DATA SLICER
Comparator Bandwidth 100 kHz
Maximum Load Capacitance C
Output High Voltage V
Output Low Voltage 0V
CRYSTAL OSCILLATOR
Crystal Frequency (Note 5) f
Crystal Tolerance 50 ppm
Input Capacitance From each pin to ground 6.2 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LOAD
XTAL
V
fRF = 433.92MHz
fRF = 315MHz
XTALSEL
V
XTALSEL
V
XTALSEL
V
XTALSEL
10 pF
VDD5
= 0V 6.6128
= DV
DD
= 0V 4.7547
= DV
DD
13.2256
9.5094
V
MHz
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(
Typical Application Circuit
, V
DD5
= +5.0V, fRF= 433.92MHz, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
MAX7034 toc01
4.5 4.7 4.9 5.1 5.3 5.5
6.6
7.0
6.8
7.2
7.4
7.6
7.8
+105°C
+125°C
+85°C
+25°C
-40°C
SUPPLY CURRENT vs. RF FREQUENCY
RF FREQUENCY (MHz)
SUPPLY CURRENT (mA)
MAX7034 toc02
250 300 350 400 450 500
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
+105°C
+125°C
+85°C
+25°C
-40°C
BIT-ERROR RATE
vs. PEAK RF INPUT POWER
PEAK RF INPUT POWER (dBm)
BIT-ERROR RATE (%)
MAX7034 toc03
-130 -125 -120 -115 -110
0.01
0.10
1.00
10.00
100.00
315MHz
433.92MHz
SENSITIVITY vs. TEMPERATURE
TEMPERATURE (°C)
SENSITIVITY (dBm)
MAX7034 toc04
-40 -15 10 35 60 85 110
-120
-118
-116
-114
-112
-110
-108
-106
-104
-102
433.92MHz
315MHz
RSSI vs. RF INPUT POWER
RF INPUT POWER (dBm)
RSSI (V)
MAX7034 toc05
-140 -120 -100 -80 -60 -40 -20 0
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
IF BANDWIDTH = 280kHz
RSSI AND DELTA vs. IF INPUT POWER
IF INPUT POWER (dBm)
RSSI (V)
DELTA
MAX7034 toc06
-25
-20
-15
-10
-5
0
5
10
15
-90 -80 -70 -60 -50 -40 -30 -20 -10 0 10
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
RSSI
DELTA
LNA/MIXER VOLTAGE GAIN
vs. IF FREQUENCY
IF FREQUENCY (MHz)
LNA/MIXER VOLTAGE GAIN (dB)
MAX7034 toc07
0 5 10 15 20 25 30
-5
5
15
25
35
45
55
65
UPPER SIDEBAND
LOWER SIDEBAND
49.7dB
IMAGE
REJECTION
IMAGE REJECTION vs. RF FREQUENCY
RF FREQUENCY (MHz)
IMAGE REJECTION (dB)
MAX7034 toc08
280 300 320 340 360 380 400 420 440 460 480
0
10
20
30
40
50
60
fRF = 315MHz
fRF = 433.92MHz
IMAGE REJECTION vs. TEMPERATURE
TEMPERATURE (°C)
IMAGE REJECTION (dB)
MAX7034 toc09
-40 -15 10 35 60 85 110
40
42
44
46
48
50
52
433.92MHz
315MHz
PHASE NOISE
vs. OFFSET FREQUENCY
MAX7033 toc13
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
1M100k10k1k100
-120
-100
-80
-60
-40
-20
0
-140
10 10M
fRF = 315MHz
PHASE NOISE
vs. OFFSET FREQUENCY
MAX7033 toc14
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
1M100k10k1k100
-120
-100
-80
-60
-40
-20
0
-140
10 10M
fRF = 433.92MHz
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(
Typical Application Circuit
, V
DD5
= +5.0V, fRF= 433.92MHz, TA= +25°C, unless otherwise noted.)
NORMALIZED IF GAIN
vs. IF FREQUENCY
MAX7034 toc10
IF FREQUENCY (MHz)
NORMALIZED IF GAIN (dB)
10
-25
-20
-15
-10
-5
0
5
-30
1 100
S11 MAGNITUDE PLOT OF RFIN
vs. FREQUENCY
MAX7034 toc11
FREQUENCY (MHz)
S
11
MAGNITUDE (dB)
470440380 410260 290 320 350230
-40
-30
-20
-10
0
10
20
30
40
50
-50
200 500
315MHz
-24.1dB
S11 SMITH CHART PLOT OF RFIN
MAX7034 toc12
500MHz
200MHz
WITH INPUT
MATCHING
315MHz
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
_______________________________________________________________________________________ 7
Pin Description
PIN NAME FUNCTION
1 XTAL1 Crystal Input 1
P osi ti ve Anal og S up p l y V ol tag e. AV DD i s connected to an on- chi p + 3.4V l ow - d r op out r eg ul ator . Both
p i ns m ust b e exter nal l y connected to each other . Byp ass p i n 2 to AG N D w i th a 0.1µF cap aci tor as
2, 7 AV
3 LNAIN Low-Noise Amplifier Input. See the Low-Noise Amplifier section.
4 LNASRC
5, 10 AGND Analog Ground
6 LNAOUT
8 MIXIN1
9 MIXIN2
11 IRSEL
12 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
13 DGND Digital Ground
14 DV
15 EN_REG
16 XTALSEL
17 IFIN1
18 IFIN2
19 DFO Data Filter Output
20 DSN Negative Data Slicer Input
21 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter
22 DFFB Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
23 DSP Positive Data Slicer Input
24 V
25 DATAOUT Digital Baseband Data Output
26 PDOUT Peak-Detector Output
27 SHDN
28 XTAL2 C r ystal Inp ut 2. C an al so b e d r i ven w i th an exter nal r efer ence osci l l ator . S ee the C r ystal O sci l l ator secti on.
DD
DD
DD5
AV
DD
cl ose as p ossi b l e to the p i n ( see the Typ i cal Ap p l i cati on C i r cui t) . Byp ass p i n 7 w i th a 0.01µF cap aci tor .
Low-Noise Amplifier Source for external Inductive Degeneration. Connect inductor to ground to set
LNA input impedance. See the Low-Noise Amplifier section.
Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter. See the Low-Noise
Amplifier section.
1st Differential Mixer Input. Connect to LC tank filter from LNAOUT through a 100pF capacitor. See
the Typical Application Circuit.
2nd Differential Mixer Input. Connect to AV
See the Typical Application Circuit.
Image-Rejection Select. Set V
unconnected to center image rejection at 375MHz. Set V
434MHz. See the Mixer section.
Positive Digital Supply Voltage. Connect to AVDD. Bypass to DGND with a 0.01µF capacitor as close
as possible to the pin.
Regulator Enable. Connect to V
operation between +3.0V and +3.6V. See the Voltage Regulator section.
Crystal Divider Ratio Select. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL high to
select divider ratio of 32.
1st Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
bandpass filter.
2nd Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF
capacitor as close as possible to the pin.
+5.0V Supply Voltage
Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a
100kΩ resistor.
= 0V to center image rejection at 315MHz. Leave IRSEL
IRSEL
to enable internal regulator. Pull this pin low to allow device
DD5
side of the LC tank filter through a 100pF capacitor.
DD
= DVDD to center image rejection at
IRSEL
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
8 _______________________________________________________________________________________
Functional Diagram
Detailed Description
The MAX7034 CMOS superheterodyne receiver and a
few external components provide the complete receive
chain from the antenna to the digital output data.
Depending on signal power and component selection,
data rates can be as high as 33kbps Manchester
(66kbps NRZ).
The MAX7034 is designed to receive binary ASK data
modulated in the 300MHz to 450MHz frequency range.
ASK modulation uses a difference in amplitude of the
carrier to represent logic 0 and logic 1 data.
Voltage Regulator
The MAX7034 is designed to work with a nominal +5.0V
supply voltage. The MAX7034 integrates an internal voltage regulator that provides +3.4V to some of the internal
circuits in the device; this voltage is connected to the
AVDD and DVDD pins. The device can be operated from
+3.0V to +3.6V by pulling the EN_REG pin low (which disables the internal voltage regulator) and connecting the
supply voltage to the AVDD and DVDD pins. If the
MAX7034 is powered from +3.0 to +3.6V, the performance is limited to the -40°C to +105°C range.
Low-Noise Amplifier
The LNA is an nMOS cascode amplifier with off-chip
inductive degeneration. The gain and noise figures are
dependent on both the antenna matching network at
the LNA input and the LC tank network between the
LNA output and the mixer inputs.
The off-chip inductive degeneration is achieved by
connecting an inductor from LNASRC to AGND. This
inductor sets the real part of the input impedance at
LNAIN, allowing for a more flexible input impedance
match, such as a typical printed-circuit board (PCB)
trace antenna. A nominal value for this inductor with a
50Ω input impedance is 15nH, but is affected by the
PCB trace.
The LC tank filter connected to LNAOUT comprises L1
and C9 (see the
Typical Application Circuit
). Select L1
and C9 to resonate at the desired RF input frequency.
The resonant frequency is given by:
where:
L
TOTAL
= L1 + L
PARASITICS
.
C
TOTAL
= C9 + C
PARASITICS
.
L
PARASITICS
and C
PARASITICS
include inductance and
capacitance of the PCB traces, package pins, mixer
input impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect
LNAOUT MIXIN1 MIXIN2
EN_REG
4 15 6 8 9 11 12 17 18
3.4V REG
DIVIDE
BY 64
PHASE
÷1
÷2
XTALSEL16XTAL11XTAL2
VCO
LOOP
FILTER
CRYSTAL
DRIVER
28
POWER-
DOWN
SHDN27DATAOUT
AV
V
DD5
DV
AGND
3
2, 7
DD
24
14
DD
13
5, 10
LNAIN
DGND
LNASRC
LNA
DETECTOR
IRSEL
0˚
Q
IMAGE
REJECTION
I
DATA
SLICER
25
∑
90˚
MAX7034
19
DSN20DSP23DFO
IFIN1MIXOUT IFIN2
21
PDOUT26OPP
RSSI
R
DF2
100kΩ
IF LIMITING
AMPS
DATA
FILTER
22
DFFB
R
DF1
100kΩ
f
RF
=
LC
2π
1
TOTAL TOTAL
×
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
_______________________________________________________________________________________ 9
on the tank filter center frequency. The total parasitic
capacitance is generally between 4pF and 6pF.
Mixer
A unique feature of the MAX7034 is the integrated
image rejection of the mixer. This device eliminates the
need for a costly front-end SAW filter for most applications. Advantages of not using a SAW filter are
increased sensitivity, simplified antenna matching, less
board space, and lower cost.
The mixer cell is a pair of double balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz IF from a low-side injected LO (i.e., fLO= fRFfIF). The image-rejection circuit then combines these
signals to achieve 44dB of image rejection. Low-side
injection is required due to the on-chip image-rejection
architecture. The IF output is driven by a source follower biased to create a driving-point impedance of 330Ω;
this provides a good match to the off-chip 330Ω ceram-
ic IF filter.
The IRSEL pin is a logic input that selects one of the
three possible image-rejection frequencies. When V
IRSEL
= 0V, the image rejection is tuned to 315MHz. V
IRSEL
=
DVDD/2 tunes the image rejection to 375MHz, and
V
IRSEL
= DVDDtunes the image rejection to 434MHz.
The IRSEL pin is internally set to DVDD/2 (image rejection
at 375MHz) when it is left unconnected, thereby eliminating the need for an external DVDD/2 voltage.
Phase-Locked Loop
The PLL block contains a phase detector, charge
pump, integrated loop filter, VCO, asynchronous 64x
clock divider, and crystal oscillator driver. Besides the
crystal, this PLL does not require any external components. The VCO generates a low-side LO. The relationship between the RF, IF, and reference frequencies is
given by:
where:
M = 1 (V
XTALSEL
= DVDD) or 2 (V
XTALSEL
= 0V)
To allow the smallest possible IF bandwidth (for best sensitivity), minimize the tolerance of the reference crystal.
Intermediate Frequency and RSSI
The IF section presents a differential 330Ω load to provide matching for the off-chip ceramic filter. The six
internal AC-coupled limiting amplifiers produce an
overall gain of approximately 65dB, with a bandpassfilter-type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz.
The RSSI circuit demodulates the IF by producing a DC
output proportional to the log of the IF signal level, with
a slope of approximately 14.2mV/dB.
Applications Information
Crystal Oscillator
The crystal oscillator in the MAX7034 is designed to
present a capacitance of approximately 3pF between
the XTAL1 and XTAL2. If a crystal designed to oscillate
with a different load capacitance is used, the crystal is
pulled away from its intended operating frequency,
introducing an error in the reference frequency.
Crystals designed to operate with higher differential
load capacitance always pull the reference frequency
higher. For example, a 4.7547MHz crystal designed to
operate with a 10pF load capacitance oscillates at
4.7563MHz with the MAX7034, causing the receiver to
be tuned to 315.1MHz rather than 315.0MHz, an error
of about 100kHz, or 320ppm. It is very important to
use a crystal with a load capacitance that is equal to
the capacitance of the MAX7034 crystal oscillator
plus PCB parasitics.
In actuality, the oscillator pulls every crystal. The crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
where:
fP is the amount the crystal frequency pulled in ppm.
CMis the motional capacitance of the crystal.
C
CASE
is the case capacitance.
C
SPEC
is the specified load capacitance.
C
LOAD
is the actual load capacitance.
When the crystal is loaded as specified (i.e., C
LOAD
=
C
SPEC
), the frequency pulling equals zero.
It is possible to use an external reference oscillator in
place of a crystal to drive the VCO. AC-couple the external oscillator to XTAL2 with a 1000pF capacitor. Drive
XTAL2 with a signal level of approximately 500mV
P-P
.
AC-couple XTAL1 to ground with a 1000pF capacitor.
ff
-
RF IF
=×
32
M
f
REF
⎛
C
M
f
=
P
⎜
CCCC
2
⎝
11
++
CASE LOAD CASE SPEC
-
⎞
10
×
⎟
⎠
6
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external
capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency should be set to
approximately 1.5 times the fastest expected data rate
from the transmitter. Keeping the corner frequency near
the data rate rejects any noise at higher frequencies,
resulting in an increase in receiver sensitivity.
The configuration shown in Figure 1 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of C5 and C6, use the following equations, along
with the coefficients in Table 1:
where f
C
is the desired 3dB corner frequency.
For example, to choose a Butterworth filter response
with a corner frequency of 5kHz:
Choosing standard capacitor values changes C5 to
470pF and C6 to 220pF, as shown in the
Typical
Application Circuit
.
Data Slicer
The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. One input is supplied by the data
filter output. Both comparator inputs are accessible offchip to allow for different methods of generating the
slicing threshold, which is applied to the second comparator input.
The suggested data slicer configuration uses a resistor
(R1) connected between DSN and DSP with a capacitor (C4) from DSN to DGND (Figure 2). This configuration averages the analog output of the filter and sets the
threshold to approximately 50% of that amplitude. With
this configuration, the threshold automatically adjusts
as the analog signal varies, minimizing the possibility
for errors in the digital data. The values of R1 and C4
affect how fast the threshold tracks to the analog amplitude. Be sure to keep the corner frequency of the RC
circuit much lower than the lowest expected data rate.
Note that a long string of zeros or ones can cause the
threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an
equal number of zeros and ones, is used.
To prevent continuous toggling of DATAOUT in the
absence of an RF signal due to noise, add hysteresis to
the data slicer as shown in Figure 3.
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
10 ______________________________________________________________________________________
Figure 1. Sallen-Key Lowpass Data Filter
Table 1. Coefficents to Calculate C5 and C6
=
C
5
6
=
C
C
5
=
1 414 100 3 14 5
..
()( )()()
C
=
6
4 100 3 14 5
()( )( )( )
1 414
k kHz
Ω
b
100
akf
π
()()()
C
a
4 100
1 000
.
k kHz
.
π
kf
()()()
C
Ω
≈
.
225
≈
450
pF
FILTER TYPE a b
Butterworth (Q = 0.707) 1.414 1.000
Bessel (Q = 0.577) 1.3617 0.618
pF
MAX7034
RSSI
R
21
OPP
DF2
100kΩ
C5
19
DFO
C6
22
DFFB
R
DF1
100kΩ
Peak Detector
The peak-detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor provides a path for the capacitor to discharge, allowing the
peak detector to dynamically follow peak changes of
the data-filter output voltage. For faster data slicer
response, use the circuit shown in Figure 4. For more
details on hysteresis and peak-detector applications,
refer to Maxim Application Note 3671,
Data Slicing
Techniques for UHF ASK Receivers
.
Layout Considerations
A properly designed PCB is an essential part of any
RF/microwave circuit. On high-frequency inputs and
outputs, use controlled-impedance lines and keep them
as short as possible to minimize losses and radiation.
At high frequencies, trace lengths that are on the order
of λ/10 or longer act as antennas.
Keeping the traces short also reduces parasitic inductance. Generally, 1 inch of a PCB trace adds about
20nH of parasitic inductance. The parasitic inductance
can have a dramatic effect on the effective inductance
of a passive component. For example, a 0.5 inch trace
connecting a 100nH inductor adds an extra 10nH of
inductance or 10%.
To reduce the parasitic inductance, use wider traces
and a solid ground or power plane below the signal
traces. Also, use low-inductance connections to ground
on all GND pins, and place decoupling capacitors
close to all V
DD
connections.
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
______________________________________________________________________________________ 11
Figure 3. Generating Data Slicer Hysteresis
Figure 4. Using PDOUT for Faster Startup
Figure 2. Generating Data Slicer Threshold
MAX7034
DATA
SLICER
R1
R2
25
DATAOUT
*OPTIONAL
DSP
23
20
DSN
R3
C4
MAX7034
DATA
SLICER
25
DATAOUT
47nF
DSN
20
25kΩ
DSP
19
23
DFO
19
DFO
R4
26
PDOUT
MAX7034
DATA
SLICER
25
DATAOUT
20
DSN
C4
23
DSP
R1
19
DFO
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
12 ______________________________________________________________________________________
Chip Information
PROCESS: CMOS
Typical Application Circuit
*
AT 315MHz
C9
DO NOT POPULATE
L1
51nH
L2
120nH
Y1
9.509375MHz
C18
OPEN
RF_IN
GND
C9
*
L1
*
JU7
C20
0.1μF
TP6
+3.3V
+3.3V VDD
TP5 TP10
DO NOT POPULATE
C7
100pF
C10
220pF
AT 433.92MHz
27nH
56nH
13.225625MHz
L2
0.1μF
*
L3
15nH
+3.3V
C2
0.01μF
+3.3V
+3.3V
1
2
JU6
3
VDD
+3.3V
C1
0.01μF
C12
SHDN
PDOUT
DATAOUT
V
DFFB
DSN
DFO
IFIN2
IFIN1
XTALSEL
EN_REG
321
DSP
OPP
C15
15pF
DD5
C14
Y1
15pF
*
C16
OPEN
128
XTAL1 XTAL2
+3.3V
2
AV
DD
U1
3
MAX7034
LNAIN
4
LNASRC
5
AGND
6
LNAOUT
7
AV
C11
100pF
100pF
DD
8
MIXIN1
9
MIXIN2
C8
10
AGND
11
IRSEL
12
MIXOUT
13
DGND
14
DV
DD
Y2
10.7MHz
IN GND OUT
C19
OPEN
27
26
R2
OPEN
25
24
C23
0.01μF
23
C22
1000pF
JU8
22
C6
220pF
21
20
R1
5.1kΩ
19
C3
1500pF
18
17
16
15
TP11
TP12
1
3
C13
OPEN
VDD
TP4
C4
0.47μF
2
JU5
F_IN
VDD
1
JU1
2
3
VDD
C24
0.1μF
R7
0Ω
TP7
C5
470pF
DSN
TP2
TP3
R8
10kΩ
+3.3V
1
2
JU2
3
EN_REG
DSN
1
JU4
2
3
R5
10kΩ DATA_OUT
C21
10pF
R3
OPEN
3
2
JU3
1
TP9
SHDN
TP8
R6
OPEN
C17
OPEN
MIX_OUT
R4
OPEN
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
13
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
TSSOP4.40mm.EPS
PACKAGE OUTLINE, TSSOP 4.40mm BODY
21-0066
1
I
1
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