General Description
The MAX7033 fully integrated low-power CMOS superheterodyne receiver is ideal for receiving amplitudeshift-keyed (ASK) data in the 300MHz to 450MHz
frequency range. The receiver has an RF input signal
range of -114dBm to 0dBm. With few external components and a low-current power-down mode, it is ideal
for cost-sensitive and power-sensitive applications typical in the automotive and consumer markets. The
MAX7033 consists of a low-noise amplifier (LNA), a fully
differential image-rejection mixer, an on-chip phaselocked loop (PLL) with integrated voltage-controlled
oscillator (VCO), a 10.7MHz IF limiting amplifier stage
with received-signal-strength indicator (RSSI), and analog baseband data-recovery circuitry. The MAX7033
also has a discrete one-step automatic gain control
(AGC) that reduces the LNA gain by 35dB when the RF
input signal exceeds -62dBm. The AGC circuitry offers
an externally controlled hold feature.
The MAX7033 is available in a 28-pin TSSOP package
and is specified over the extended (-40°C to +105°C)
temperature range.
Features
♦ Optimized for 315MHz or 433MHz Band
♦ Operates from Single +3.3V or +5.0V Supplies
♦ High Dynamic Range with On-Chip AGC
♦ AGC Hold Circuit
♦ 1ms AGC Release Time
♦ Selectable Image-Rejection Center Frequency
♦ Selectable x64 or x32 fLO/f
XTAL
Ratio
♦ Low 5.2mA Operating Supply Current
♦ <3.5µA Low-Current Power-Down Mode for
Efficient Power Cycling
♦ 250µs Startup Time
♦ Built-In 44dB RF Image Rejection
♦ Better than -114dBm Receive Sensitivity
♦ -40°C to +105°C Operation
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
________________________________________________________________ Maxim Integrated Products 1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
XTAL2
SHDN
PDOUT
DATAOUT
V
DD5
DSP
AC
DFFB
OPP
DSN
DFO
IFIN2
IFIN1
XTALSEL
DV
DD
DGND
MIXOUT
IRSEL
AGND
MIXIN2
MIXIN1
AV
DD
LNAOUT
AGND
LNASRC
LNAIN
AV
DD
XTAL1
TSSOP
THIN QFN
TOP VIEW
MAX7033
32
313029
282726
LNASRC
LNAIN
AV
DD
XTAL1
XTAL2
SHDN
PDOUT
25 N.C.
9
101112
131415
MIXOUT
DGND
DV
DD
AC
N.C.
XTALSEL
IFIN1
16IFIN2
17
18
19
20
21
22
23
DFO
DSN
OPP
DFFB
N.C.
DSP
V
DD5
8
7
6
5
4
3
2
IRSEL
AGND
MIXIN2
MIXIN1
AV
DD
LNAOUT
AGND
MAX7033
1N.C.
24 DATAOUT
Pin Configurations
Ordering Information
Applications
19-3273; Rev 0; 5/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*Future product—contact factory for availability.
**EP = Exposed paddle.
Typical Application Circuit appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX7033EUI -40°C to +105°C 28 TSSOP
MAX7033ETJ* -40°C to +105°C 32 Thin QFN-EP**
Automotive Remote
Keyless Entry
Security Systems
Garage Door Openers
Home Automation
Remote Controls
Local Telemetry
Wireless Sensors
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS (+3.3V OPERATION)
(Typical Application Circuit, AVDD= DVDD= V
DD5
= +3.0V to +3.6V, no RF signal applied, TA= -40°C to +105°C, unless otherwise
noted. Typical values are at AV
DD
= DVDD= V
DD5
= +3.3V and TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
DD5
to AGND.......................................................-0.3V to +6.0V
AV
DD
to AGND......................................................-0.3V to +4.0V
DV
DD
to DGND......................................................-0.3V to +4.0V
AGND to DGND.....................................................-0.1V to +0.1V
IRSEL, DATAOUT, XTALSEL,
AC,
SHDN to AGND.............................-0.3V to (V
DD5
+ 0.3V)
All Other Pins to AGND............................-0.3V to (DV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
28-Pin TSSOP (derate 12.8mW/°C above +70°C) ..1025.6mW
32-Thin QFN (derate 21.3mW/°C above +70°C) ....1702.1mW
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering 10s)..................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
AV
DD
,
DV
DD
+3.3V nominal supply voltage 3.0 3.3 3.6 V
fRF = 315MHz 5.2
Supply Current I
DD
V
SHDN
= DV
DD
fRF = 433MHz 5.7
mA
fRF = 315MHz 2.6
Shutdown Supply Current I
SHDN
V
SHDN
= 0V,
V
XTALSEL
= 0V
f
RF
= 433MHz 3.5 8.0
µA
Input-Voltage Low V
IL
0.4 V
Input-Voltage High V
IH
DVDD -
0.4
V
Input Logic Current High I
IH
10 µA
fRF = 433MHz, V
IRSEL
= V
DD5
V
DD5
-
0.4
fRF = 375MHz, V
IRSEL
= V
DD5
/ 2 1.1
V
DD5
-
1.0
Image-Reject Select Voltage
(Note 2)
f
RF
= 315MHz, V
IRSEL
= 0V 0.4
V
DATAOUT Output-Voltage Low V
OL
I
SINK
= 10µA
V
DATAOUT Output-Voltage High V
OH
I
SOURCE
= 10µA
DV
DD
V
DC ELECTRICAL CHARACTERISTICS (+5.0V OPERATION)
(Typical Application Circuit, V
DD5
= +4.5V to +5.5V, no RF signal applied, TA= -40°C to +105°C, unless otherwise noted. Typical val-
ues are at V
DD5
= +5.0V and TA= +25°C.) (Note 1)
PARAMETER
CONDITIONS
UNITS
Supply Voltage V
DD5
+5.0V nominal supply voltage 4.5 5.0 5.5 V
fRF = 315MHz 5.2 6.4
Supply Current I
DD
V
SHDN
= V
DD5
fRF = 433MHz 5.7
mA
fRF = 315MHz 3.7
Shutdown Supply Current I
SHDN
V
SHDN
= 0V,
V
XTALSEL
= 0V
f
RF
= 433MHz 4.2 9.8
µA
Input-Voltage Low V
IL
0.4 V
6.23
6.88
0.125
SYMBOL
MIN TYP MAX
0.125
6.76
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (+5.0V OPERATION) (continued)
(Typical Application Circuit, V
DD5
= +4.5V to +5.5V, no RF signal applied, TA= -40°C to +105°C, unless otherwise noted. Typical val-
ues are at V
DD5
= +5.0V and TA= +25°C.) (Note 1)
PARAMETER
CONDITIONS
UNITS
Input-Voltage High V
IH
V
DD5
-
0.4
V
Input Logic Current High I
IH
15 µA
fRF = 433MHz, V
IRSEL
= V
DD5
V
DD5
-
0.4
fRF = 375MHz, V
IRSEL
= V
DD5
/ 2 1.1
V
DD5
-
1.5
Image-Reject Select Voltage
(Note 2)
f
RF
= 315MHz, V
IRSEL
= 0V 0.4
V
DATAOUT Output-Voltage Low V
OL
I
SINK
= 10µA
V
DATAOUT Output-Voltage High V
OH
I
SOURCE
= 10µA
V
DD5
V
AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, AVDD= DVDD= V
DD5
= +3.0V to +3.6V, all RF inputs are referenced to 50Ω, fRF= 315MHz, TA= -40°C
to +105°C, unless otherwise noted. Typical values are at AV
DD
= DVDD= V
DD5
= +3.3V and TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
Startup Time t
ON
Time for valid signal detection after V
SHDN
= DV
DD
µs
Receiver Input Frequency f
RF
450
MHz
Maximum Receiver Input Level Modulation depth >18dB 0
dBm
Average carrier power level
Sensitivity (Note 3)
Peak power level
dBm
LNA gain from low to high 8 dB
AGC Hysteresis
Switching time from low to high gain 1 ms
Manchester coded 33
Maximum Data Rate
NRZ coded 66
kbps
LNA IN HIGH-GAIN MODE
fRF = 433MHz
fRF = 375MHz
Input Impedance
fRF = 315MHz
1dB Compression Point
-22
dBm
Input-Referred 3rd-Order
Intercept
-12
dBm
LO Signal Feedthrough to
Antenna
-80
dBm
Output Impedance
Normalized to 50Ω 0.12 - j4.4
Noise Figure NF
LNA
3dB
SYMBOL
MIN TYP MAX
0.125
0.125
250
Z
IN_LNA
P1dB
IIP3
LNA
Z
OUT_LNA
Normalized to 50Ω
LNA
300
-120
-114
1 - j3.4
1 - j3.9
1 - j4.7
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, AVDD= DVDD= V
DD5
= +3.0V to +3.6V, all RF inputs are referenced to 50Ω, fRF= 315MHz, TA= -40°C
to +105°C, unless otherwise noted. Typical values are at AV
DD
= DVDD= V
DD5
= +3.3V and TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LNA IN LOW-GAIN MODE
fRF = 433MHz
fRF = 375MHz
Input Impedance
(Note 4)
f
RF
= 315MHz
1dB Compression Point
-10
dBm
Input-Referred 3rd-Order
Intercept
-7
dBm
LO Signal Feedthrough to
Antenna
-80
dBm
Output Impedance
Normalized to 50Ω 0.4
Noise Figure NF
LNA
3dB
Voltage-Gain Reduction AGC enabled (depends on tank Q) 35 dB
MIXER
Input Impedance
Normalized to 50Ω 0.25 - j2.4
Input-Referred 3rd-Order
Intercept
IIP3
MIX
-18
dBm
Output Impedance
Ω
Noise Figure NF
MIX
16 dB
fRF = 433MHz, V
IRSEL
= DV
DD
42
fRF = 375MHz, V
IRSEL
= DV
DD
/ 2 44
Image Rejection
(Not Including LNA Tank)
f
RF
= 315MHz, V
IRSEL
= 0V 44
dB
LNA in high-gain
mode
48
LNA/Mixer Voltage Gain 330Ω IF filter load
LNA in low-gain
mode
13
dB
INTERMEDIATE FREQUENCY (IF)
Input Impedance Z
IN_IF
Ω
Operating Frequency f
IF
Bandpass response
MHz
3dB Bandwidth 10
MHz
RSSI Linearity
dB
RSSI Dynamic Range 80 dB
P
RFIN
< -120dBm
RSSI Level
P
RFIN
> 0dBm, AGC enabled 2.2
V
LNA gain from low to high
AGC Threshold
LNA gain from high to low
V
DATA FILTER
Maximum Bandwidth 50 kHz
DATA SLICER
Comparator Bandwidth
kHz
Z
IN_LNA
P1dB
IIP3
Z
OUT_LNA
Z
IN_MIX
Z
OUT_MIX
Normalized to 50Ω
LNA
LNA
1 - j3.4
1 - j3.9
1 - j4.7
330
330
10.7
±0.5
1.15
1.39
1.98
100
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
_______________________________________________________________________________________ 5
Note 1: 100% tested at TA= +25°C. Guaranteed by design and characterization over temperature.
Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image-rejection setting is desired. Bypass
to AGND with a 1nF capacitor in a noisy environment.
Note 3: BER = 2 x 10
-3
, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz.
Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance includes the 15nH inductive degeneration con-
nected from the LNA source to ground. The equivalent input circuit is 50Ω in series with 2.2pF.
Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (f
RF
- 10.7MHz) / 64 for
XTALSEL = 0V, and (f
RF
- 10.7MHz) / 32 for XTALSEL = V
DD5
.
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, AVDD= DVDD= V
DD5
= +3.0V to +3.6V, all RF inputs are referenced to 50Ω, fRF= 315MHz, TA= -40°C
to +105°C, unless otherwise noted. Typical values are at AV
DD
= DVDD= V
DD5
= +3.3V and TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum Load Capacitance C
LOAD
10 pF
Output High Voltage
V
Output Low Voltage 0V
CRYSTAL OSCILLATOR
V
XTALSEL
= 0V
fRF = 433MHz
V
XTALSEL
= V
DD5
V
XTALSEL
= 0V
Crystal Frequency (Note 5) f
XTAL
fRF = 315MHz
V
XTALSEL
= V
DD5
MHz
Crystal Tolerance 50
ppm
Input Capacitance From each pin to ground 6.2 pF
Typical Operating Characteristics
(Typical Application Circuit , AVDD= DVDD= V
DD5
= +3.3V, fRF= 315MHz, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX7033 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.53.43.33.23.1
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
4.0
3.0 3.6
+85°C
+105°C
+25°C
-40°C
SUPPLY CURRENT
vs. RF FREQUENCY
MAX7033 toc02
RF FREQUENCY (MHz)
SUPPLY CURRENT (mA)
450400300 350
3.5
4.0
4.5
5.0
6.0
5.5
6.5
7.0
3.0
250 500
+105°C
+85°C
-40°C
+25°C
BIT-ERROR RATE
vs. PEAK RF INPUT POWER
MAX7033 toc03
PEAK RF INPUT POWER (dBm)
BIT-ERROR RATE (%)
-116-118-120-122-124-126-128
0.1
1
10
100
0.01
-130 -114
fRF = 433MHz
fRF = 315MHz
V
DD5
6.6128
13.2256
4.7547
9.5094
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Typical Application Circuit , AVDD= DVDD= V
DD5
= +3.3V, fRF= 315MHz, TA= +25°C, unless otherwise noted.)
SENSITIVITY vs. TEMPERATURE
MAX7033 toc04
TEMPERATURE (°C)
SENSITIVITY (dBm)
85603510-15
-122
-120
-118
-116
-114
-112
-110
-108
-124
-40 110
PEAK RF INPUT POWER
0.2% BER
IF BANDWIDTH = 280kHz
fRF = 433MHz
fRF = 315MHz
RSSI vs. RF INPUT POWER
MAX7033 toc05
RF INPUT POWER (dBm)
RSSI (V)
-20-40-60-80-100-120
1.2
1.4
1.6
1.8
2.0
2.2
2.4
1.0
-140 0
IF BANDWIDTH = 280kHz
VAC = DV
DD
VAC = 0V
RSSI AND DELTA
vs. IF INPUT POWER
MAX7033 toc06
IF INPUT POWER (dBm)
RSSI (V)
-10-30-50-70
1.2
1.4
1.6
1.8
2.0
2.2
2.4
DELTA (%)
1.0
-90 10
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
-3.5
DELTA
RSSI
LNA/MIXER VOLTAGE GAIN
vs. IF FREQUENCY
MAX7033 toc07
IF FREQUENCY (MHz)
SYSTEM GAIN (dB)
252015105
5
15
25
35
45
55
65
-5
030
UPPER
SIDEBAND
49dB IMAGE
REJECTION
LOWER
SIDEBAND
FROM RFIN
TO MIXOUT
f
RF
= 315MHz
IMAGE REJECTION
vs. RF FREQUENCY
MAX7033 toc08
RF FREQUENCY (MHz)
IMAGE REJECTION (dB)
460440420400380360340320300
35
40
45
50
55
30
280 480
fRF = 375MHz
fRF = 315MHz
fRF = 433MHz
IMAGE REJECTION
vs. TEMPERATURE
MAX7033 toc09
TEMPERATURE (°C)
IMAGE REJECTION (dB)
603510-15
41.0
41.5
42.0
42.5
43.0
43.5
44.0
44.5
45.0
40.5
-40 85
fRF = 375MHz
fRF = 315MHz
fRF = 433MHz
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
_______________________________________________________________________________________ 7
NORMALIZED IF GAIN
vs. IF FREQUENCY
MAX7033 toc10
IF FREQUENCY (MHz)
NORMALIZED IF GAIN (dB)
10
-25
-20
-15
-10
-5
0
5
-30
1 100
S11 LOG MAGNITUDE PLOT OF RFIN
MAX7033 toc11
FREQUENCY (MHz)
S
11
MAGNITUDE (dB)
900800600 700200 300 400 500100
-40
-30
-20
-10
0
10
20
30
40
50
-50
0 1000
315MHz
-36dB
S11 SMITH CHART PLOT OF RFIN
MAX7033 toc12
500MHz
200MHz
315MHz
WITH INPUT
MATCHING
REGULATOR VOLTAGE
vs. REGULATOR CURRENT
MAX7033 toc13
REGULATOR CURRENT (mA)
REGULATOR VOLTAGE (V)
5040302010
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
1.7
060
-40°C
+25°C
+85°C
+105°C
PHASE NOISE
vs. OFFSET FREQUENCY
MAX7033 toc14
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
1M100k10k1k100
-120
-100
-80
-60
-40
-20
0
-140
10 10M
fRF = 315MHz
PHASE NOISE
vs. OFFSET FREQUENCY
MAX7033 toc15
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
1M100k10k1k100
-120
-100
-80
-60
-40
-20
0
-140
10 10M
fRF = 433MHz
Typical Operating Characteristics (continued)
(Typical Application Circuit , AVDD= DVDD= V
DD5
= +3.3V, fRF= 315MHz, TA= +25°C, unless otherwise noted.)
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
8 _______________________________________________________________________________________
Pin Description
PIN
TSSOP
NAME FUNCTION
1 29 XTAL1 Crystal Input 1 (See the Phase-Locked Loop section)
2, 7 4, 30 AV
DD
Positive Analog Supply Voltage. For +5V operation, AVDD is connected to an on-chip +3.2V
low-dropout regulator. Both AV
DD
pins must be externally connected to each other. Bypass
each pin to AGND with a 0.01µF capacitor as close to the pin as possible (see the Typical
Application Circuit).
3 31 LNAIN Low-Noise Amplifier Input (See the Low-Noise Amplifier section)
432
Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground
to set the LNA input impedance (see the Low-Noise Amplifier section).
5, 10 2, 7 AGND Analog Ground
63
Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter (see the Low-
Noise Amplifier section).
85
1st Differential Mixer Input. Connect to LC tank filter from LNAOUT.
96
2nd Differential Mixer Input. Connect through a 100pF capacitor to AVDD side of the LC tank.
11 8 IRSEL
Image-Rejection Select. Set V
IRSEL
= 0V to center image rejection at 315MHz. Leave IRSEL
unconnected to center image rejection at 375MHz. Set V
IRSEL
= V
DD5
to center image
rejection at 433MHz.
12 9
330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
13 10 DGND Digital Ground
14 11 DV
DD
Positive Digital Supply Voltage. Connect to AVDD. Bypass to DGND with a 0.01µF capacitor
as close to the pin as possible.
15 12 AC
Automatic Gain Control. See Figure 1. Internally pulled down to AGND with a 100kΩ resistor.
16 14
Crystal Divider Ratio Select. Drive XTALSEL low to select divider ratio of 64, or drive
XTALSEL high to select divider ratio of 32.
17 15 IFIN1
1st Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a
1500pF capacitor as close to the pin as possible.
18 16 IFIN2
2nd Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a
10.7MHz bandpass filter.
19 17 DFO Data Filter Output
20 18 DSN Negative Data Slicer Input
21 19 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter
22 20 DFFB Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
23 22 DSP Positive Data Slicer Input
24 23 V
DD5
+5V Supply Voltage. For +5V operation, V
DD5
is the input to an on-chip voltage regulator
whose +3.2V output drives AV
DD
.
25 24
Digital Baseband Data Output
26 26
Peak-Detector Output
THIN QFN
LNASRC
LNAOUT
MIXIN1
MIXIN2
MIXOUT
XTALSEL
DATAOUT
PDOUT
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
_______________________________________________________________________________________ 9
Functional Diagram
LNAOUT MIXIN1 MIXIN2
0˚
90˚
IFIN1MIXOUT IFIN2
RSSI
R
DF2
100kΩ
R
DF1
100kΩ
DIVIDE
BY 64
VCO
LOOP
FILTER
PHASE
DETECTOR
CRYSTAL
DRIVER
POWER-
DOWN
IF LIMITING
AMPS
14
LNASRC
DATA
SLICER
DATA
FILTER
Q
∑
I
AUTOMATIC
GAIN
CONTROL
IMAGE
REJECTION
3.2V REG
24
2, 7
IRSEL
13
5, 10
AV
DD
V
DD5
DV
DD
DGND
AGND
LNAIN
3
XTALSEL16XTAL11XTAL2
28
SHDN27DATAOUT
25
DSN20DSP23DFO
19
PDOUT26OPP
21
DFFB
22
4 15 6 8 9 11 12 17 18
AC
÷2
÷1
MAX7033
LNA
28-PIN TSSOP
PACKAGE
Pin Description (continued)
PIN
TSSOP
NAME FUNCTION
27 27 SHDN
Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND
with a 100kΩ resistor.
28 28 XTAL2
Crystal Input 2. Can also be driven with an external reference oscillator. (See the Crystal
Oscillator section.)
—
1, 13, 21,
25
N.C No Connection
Detailed Description
The MAX7033 CMOS superheterodyne receiver and a
few external components provide the complete receive
chain from the antenna to the digital output data.
Depending on signal power and component selection,
data rates as high as 33kbps Manchester (66kbps
NRZ) can be achieved.
The MAX7033 is designed to receive binary ASK data
modulated in the 300MHz to 450MHz frequency range.
ASK modulation uses a difference in amplitude of the
carrier to represent logic 0 and logic 1 data.
For operation with a single +3.0V to +3.6V supply voltage,
connect AV
DD
, DVDD, and V
DD5
to the supply voltage.
For operation with a single +4.5V to +5.5V supply voltage, connect V
DD5
to the supply voltage. An on-chip
voltage regulator drives one of the AVDDpins to
approximately +3.2V. For proper operation, DVDDand
both AVDDpins must be connected together. Bypass
DVDDand both AVDDpins to AGND with 0.01µF
capacitors placed as close to the pins as possible.
Low-Noise Amplifier
The LNA is an nMOS cascode amplifier with off-chip
inductive degeneration, with a 3.0dB noise figure and
an IIP3 of -12dBm. The gain and noise figures are
dependent on both the antenna matching network at
the LNA input and the LC tank network between the
LNA output and the mixer inputs.
THIN QFN
The off-chip inductive degeneration is achieved by
connecting an inductor from LNASRC to AGND. This
inductor sets the real part of the input impedance at
LNAIN, allowing for a more flexible input impedance
match, such as a typical PC board trace antenna. A
nominal value for this inductor with a 50Ω input impedance is 15nH, but is affected by PC board trace.
The LC tank filter connected to LNAOUT comprises L3
and C2 (see the Typical Application Circuit). Select L3
and C2 to resonate at the desired RF input frequency.
The resonant frequency is given by:
where:
L
TOTAL
= L3 + L
PARASITICS
.
C
TOTAL
= C2 + C
PARASITICS
.
L
PARASITICS
and C
PARASITICS
include inductance and
capacitance of the PC board traces, package pins,
mixer input impedance, LNA output impedance, etc.
These parasitics at high frequencies cannot be
ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation should be
done to optimize the center frequency of the tank.
Automatic Gain Control
When the AC pin is low, the automatic gain-control
(AGC) circuit monitors the RSSI output. As the RSSI
output reaches 1.98V, which corresponds to RF input
level of -62dBm, the AGC switches on the LNA gain
reduction resistor. The resistor reduces the LNA gain
by 35dB, thereby reducing the RSSI output by about
500mV. The LNA resumes high-gain mode when the
RSSI level drops back below 1.39V (approximately
-70dBm at RF input) for 1ms. The AGC has a hysteresis
of 8dB. With the AGC function, the MAX7033 can reliably produce an ASK output for RF input levels up to
0dBm with modulation depth of 18dB.
When the AC pin is high and SHDN goes high, the
AGC circuit is disabled and the LNA is always in highgain mode. The AGC function can be resumed by
bringing the AC pin low when SHDN is high.
The MAX7033 features an AGC lock function that is
asserted when the level at the AC pin transitions from
low to high while SHDN is high. Locking the AGC locks
the LNA in the current gain state. As shown in Figure 1,
the AGC lock function can be enabled or disabled as
long as the SHDN pin is high. Changing the state of AC
when SHDN is low has no effect.
Mixer
A unique feature of the MAX7033 is the integrated
image rejection of the mixer. This device eliminates the
need for a costly front-end SAW filter for most applications. Advantages of not using a SAW filter are
increased sensitivity, simplified antenna matching, less
board space, and lower cost.
The mixer cell is a pair of double balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz IF from a low-side injected LO (i.e., f
LO
= fRF-
f
IF
). The image-rejection circuit then combines these
signals to achieve 44dB of image rejection. Low-side
f
LC
RF
TOTAL TOTAL
=
×
1
2π
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
10 ______________________________________________________________________________________
AGC
LOCK
AGC
UNLOCK
AGC
LOCK
AGC
UNLOCK
NO
EFFECT
NO
EFFECT
SHDN
PIN
AC PIN
V
IL
V
IH
V
IH
V
IL
NO
EFFECT
AGC ENABLED
AGC
ENABLED
AGC
DISABLED
AGC
DISABLED
Figure 1. AGC Lock Activation Cycles
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
______________________________________________________________________________________ 11
COMPONENT VALUE FOR fRF = 433MHz VALUE FOR fRF = 315MHz DESCRIPTION
L1 56nH 120nH TOKO LL1608-FH
L2 15nH 15nH Murata LQP11A
L3 15nH 27nH Murata LQP11A
C1 100pF 100pF 5%
C2 2pF 4pF ± 0.1pF
C3 100pF 100pF 5%
C4 100pF 100pF 5%
C5 1500pF 1500pF 10%
C6 220pF 220pF 5%
C7 470pF 470pF 5%
C8 0.47µF 0.47µF 20%
C9 220pF 220pF 10%
C10 0.01µF 0.01µF 20%
C11 0.01µF 0.01µF 20%
C12 15pF 15pF Depends on XTAL
C13 15pF 15pF Depends on XTAL
R1 5.1kΩ 5.1kΩ 5%
X1 6.5984MHz 4.7547MHz —
X2 10.7MHz ceramic filter 10.7MHz ceramic filter Murata SFECV10.7 series
injection is required due to the on-chip image-rejection
architecture. The IF output is driven by a source follower biased to create a driving-point impedance of 330Ω;
this provides a good match to the off-chip 330Ω ceramic IF filter.
The IRSEL pin is a logic input that selects one of the
three possible image-rejection frequencies. When V
IRSEL
= 0V, the image rejection is tuned to 315MHz. V
IRSEL
=
V
DD5
/ 2 tunes the image rejection to 375MHz, and
V
IRSEL
= V
DD5
tunes the image rejection to 433MHz. The
IRSEL pin is internally set to V
DD5
/ 2 (image rejection at
375MHz) when it is left unconnected, thereby eliminating
the need for an external V
DD5
/ 2 voltage.
Phase-Locked Loop
The PLL block contains a phase detector, charge
pump, integrated loop filter, VCO, asynchronous 64x
clock divider, and crystal oscillator driver. Besides the
crystal, this PLL does not require any external components. The VCO generates a low-side LO. The relationship between the RF, IF, and reference frequencies is
given by:
where:
M = 1 (V
XTALSEL
= V
DD5
) or 2 (V
XTALSEL
= 0V)
To allow the smallest possible IF bandwidth (for best sensitivity), minimize the tolerance of the reference crystal.
Intermediate Frequency and RSSI
The IF section presents a differential 330Ω load to pro-
vide matching for the off-chip ceramic filter. The six
internal AC-coupled limiting amplifiers produce an
overall gain of approximately 65dB, with a bandpass-filter-type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz.
The RSSI circuit demodulates the IF by producing a DC
output proportional to the log of the IF signal level, with
a slope of approximately 14.2mV/dB (see the Typical
Operating Characteristics).
Applications Information
Crystal Oscillator
The crystal oscillator in the MAX7033 is designed to
present a capacitance of approximately 3pF between
the XTAL1 and XTAL2. If a crystal designed to oscillate
with a different load capacitance is used, the crystal is
pulled away from its stated operating frequency, introducing an error in the reference frequency. Crystals
f
ff
M
REF
RF IF
=×-32
Table 1. Component Values for Typical Application Circuit
designed to operate with higher differential load capacitance always pull the reference frequency higher. For
example, a 4.7547MHz crystal designed to operate
with a 10pF load capacitance oscillates at 4.7563MHz
with the MAX7033, causing the receiver to be tuned to
315.1MHz rather than 315.0MHz, an error of about
100kHz, or 320ppm.
In actuality, the oscillator pulls every crystal. The crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
where:
fP is the amount the crystal frequency pulled in ppm.
CMis the motional capacitance of the crystal.
C
CASE
is the case capacitance.
C
SPEC
is the specified load capacitance.
C
LOAD
is the actual load capacitance.
When the crystal is loaded as specified, i.e., C
LOAD
=
C
SPEC
, the frequency pulling equals zero.
It is possible to use an external reference oscillator in
place of a crystal to drive the VCO. AC-couple the external oscillator to XTAL2 with a 1000pF capacitor. Drive
XTAL2 with a signal level of approximately -10dBm. ACcouple XTAL1 to ground with a 1000pF capacitor.
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external
capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency should be set
to approximately 1.5 times the fastest expected data
rate from the transmitter. Keeping the corner frequency
near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity.
The configuration shown in Figure 2 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of C5 and C6, use the following equations, along
with the coefficients in Table 2:
where f
C
is the desired 3dB corner frequency.
For example, to choose a Butterworth filter response
with a corner frequency of 5kHz:
Choosing standard capacitor values changes C5 to
470pF and C6 to 220pF, as shown in the Typical
Application Circuit.
Data Slicer
The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. One input is supplied by the data
C
k kHz
pF
C
k kHz
pF
5
1 000
1 414 100 3 14 5
450
6
1 414
4 100 3 14 5
225
.
..
.
.
=
()( )()()
≈
=
()( )( )( )
≈
Ω
Ω
C
b
akf
C
a
kf
C
C
5
100
6
4 100
=
()()()
=
()()()
π
π
f
C
CCCC
P
M
CASE LOAD CASE LOAD
=
++
⎛
⎝
⎜
⎞
⎠
⎟
×
2
11
10
6
-
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
12 ______________________________________________________________________________________
RSSI
R
DF1
100kΩ
R
DF2
100kΩ
C5
19
DFO
21
OPP
22
DFFB
C6
MAX7033
Figure 2. Sallen-Key Lowpass Data Filter
Table 2. Coefficents to Calculate C5 and C6
FILTER TYPE a b
Butterworth (Q = 0.707) 1.414 1.000
Bessel (Q = 0.577) 1.3617 0.618
filter output. Both comparator inputs are accessible offchip to allow for different methods of generating the
slicing threshold, which is applied to the second comparator input.
The suggested data slicer configuration uses a resistor
(R1) connected between DSN and DSP with a capacitor (C4) from DSN to DGND (Figure 3). This configuration averages the analog output of the filter and sets the
threshold to approximately 50% of that amplitude. With
this configuration, the threshold automatically adjusts
as the analog signal varies, minimizing the possibility
for errors in the digital data. The values of R1 and C4
affect how fast the threshold tracks to the analog amplitude. Be sure to keep the corner frequency of the RC
circuit much lower than the lowest expected data rate.
Note that a long string of zeros or ones can cause the
threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an
equal number of zeros and ones, is used.
To prevent continuous toggling of DATAOUT in the
absence of an RF signal due to noise, add hysteresis to
the data slicer as shown in Figure 4.
Peak Detector
The peak-detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor provides a path for the capacitor to discharge, allowing the
peak detector to dynamically follow peak changes of
the data-filter output voltage. For faster data slicer
response, use the circuit shown in Figure 5.
Layout Considerations
A properly designed PC board is an essential part of
any RF/microwave circuit. On high-frequency inputs
and outputs, use controlled-impedance lines and keep
them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are on the
order of λ/10 or longer act as antennas.
Keeping the traces short also reduces parasitic inductance. Generally, 1in of a PC board trace adds about
20nH of parasitic inductance. The parasitic inductance
can have a dramatic effect on the effective inductance
of a passive component. For example, a 0.5in trace
connecting a 100nH inductor adds an extra 10nH of
inductance or 10%.
To reduce the parasitic inductance, use wider traces
and a solid ground or power plane below the signal
traces. Also, use low-inductance connections to ground
on all GND pins, and place decoupling capacitors
close to all VDDconnections.
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
______________________________________________________________________________________ 13
DATA
SLICER
R1
25
DATAOUT
20
DSN
19
DFO
23
DSP
C4
MAX7033
Figure 3. Generating Data Slicer Threshold
DATA
SLICER
R3
R1
R2
R4
25
DATAOUT
*OPTIONAL
23
DSP
19
DFO
20
DSN
C4
MAX7033
Figure 4. Generating Data Slicer Hysteresis
DATA
SLICER
25kΩ
25
DATAOUT
20
DSN
19
DFO
26
PDOUT
23
DSP
MAX7033
47nF
Figure 5. Using PDOUT for Faster Startup
Chip Information
TRANSISTOR COUNT: 3208
PROCESS: CMOS
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
14 ______________________________________________________________________________________
Typical Application Circuit
28
C13
L1
C11
C1
C2
L2
L3
C3
C4
+3.3V
RF INPUT
+3.3V
+3.3V
C12
X1
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MAX7033
DV
DD
IF FILTER
COMPONENT VALUES
IN TABLE 1
X2
GND
IN OUT
DGND
MIXOUT
IRSEL
AGND
MIXIN2
MIXIN1
AV
DD
LNAOUT
C9
C10
AGND
LNASRC
LNAIN
AV
DD
XTAL1 XTAL2
TO/FROM µP
POWER-DOWN
DATA OUT
SHDN
PDOUT
DATAOUT
V
DD5
DSP
AC
DFFB
C8
R1
R2
R3
C7
C6C5
OPP
DSN
DFO
IFIN2
IFIN1
XTALSEL
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
______________________________________________________________________________________ 15
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
TSSOP4.40mm.EPS
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
QFN THIN.EPS
D2
(ND-1) X e
e
D
C
PIN # 1
I.D.
(NE-1) X e
E/2
E
0.08 C
0.10 C
A
A1 A3
DETAIL A
0.15
C B
0.15 C A
E2/2
E2
0.10 M C A B
PIN # 1 I.D.
b
0.35x45∞
L
D/2
D2/2
L
C
L
C
e e
L
CC
L
k
k
LL
E
1
2
21-0140
PACKAGE OUTLINE
16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
DETAIL B
L
L1
e
COMMON DIMENSIONS
3.353.15
T2855-1 3.25 3.353.15 3.25
MAX.
3.20
EXPOSED PAD VARIATIONS
3.00T2055-2 3.10
D2
NOM.MIN.
3.203.00 3.10
MIN.E2NOM. MAX.
NE
ND
PKG.
CODES
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3 AND T2855-6.
NOTES:
SYMBOL
PKG.
N
L1
e
E
D
b
A3
A
A1
k
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
JEDEC
T1655-1
3.203.00 3.10 3.00 3.10 3.20
0.70 0.800.75
4.90
4.90
0.25
0.250--
4
WHHB
4
16
0.350.30
5.10
5.105.00
0.80 BSC.
5.00
0.05
0.20 REF.
0.02
MIN. MAX.NOM.
16L 5x5
3.10
T3255-2
3.00
3.20
3.00 3.10 3.20
2.70
T2855-2 2.60 2.602.80 2.70 2.80
E
2
2
21-0140
PACKAGE OUTLINE
16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
L
0.30 0.500.40
---
---
WHHC
20
5
5
5.00
5.00
0.30
0.55
0.65 BSC.
0.45
0.25
4.90
4.90
0.25
0.65
--
5.10
5.10
0.35
20L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-1
28
7
7
5.00
5.00
0.25
0.55
0.50 BSC.
0.45
0.25
4.90
4.90
0.20
0.65
--
5.10
5.10
0.30
28L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-2
32
8
8
5.00
5.00
0.40
0.50 BSC.
0.30
0.25
4.90
4.90
0.50
--
5.10
5.10
32L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
-
40
10
10
5.00
5.00
0.20
0.50
0.40 BSC.
0.40
0.25
4.90
4.90
0.15
0.60
5.10
5.10
0.25
40L 5x5
0.20 REF.
0.75
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
0.20 0.25 0.30
-
0.35 0.45
0.30 0.40 0.50
DOWN
BONDS
ALLOWED
NO
YES3.103.00 3.203.103.00 3.20T2055-3
3.103.00 3.203.103.00 3.20T2055-4
T2855-3 3.15 3.25 3.35 3.15 3.25 3.35
T2855-6 3.15 3.25 3.35 3.15 3.25 3.35
T2855-4 2.60 2.70 2.80 2.60 2.70 2.80
T2855-5 2.60 2.70 2.80 2.60 2.70 2.80
T2855-7 2.60 2.70
2.80
2.60 2.70 2.80
3.20
3.00 3.10T3255-3 3.203.00 3.10
3.203.00 3.10T3255-4 3.203.00 3.10
3.403.20 3.30T4055-1 3.20 3.30 3.40
NO
NO
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
3.203.00T1655-2 3.10 3.00 3.10 3.20 YES
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