Rainbow Electronics MAX7030 User Manual

General Description

The MAX7030 crystal-based, fractional-N transceiver is
designed to transmit and receive ASK/OOK data at fac­tory-preset carrier frequencies of 315MHz, 345MHz†, or

433.92MHz with data rates up to 33kbps (Manchester
encoded) or 66kbps (NRZ encoded). This device gen­erates a typical output power of +10dBm into a 50Ω
load, and exhibits typical sensitivity of -114dBm. The
MAX7030 features separate transmit and receive pins
(PAOUT and LNAIN) and provides an internal RF switch
that can be used to connect the transmit and receive
pins to a common antenna.

The MAX7030 transmit frequency is generated by a 16­bit, fractional-N, phase-locked loop (PLL), while the
receiver’s local oscillator (LO) is generated by an inte­ger-N PLL. This hybrid architecture eliminates the need
for separate transmit and receive crystal reference
oscillators because the fractional-N PLL is preset to be

10.7MHz above the receive LO. Retaining the fixed-N
PLL for the receiver avoids the higher current-drain
requirements of a fractional-N PLL and keeps the
receiver current drain as low as possible. All frequency­generation components are integrated on-chip, and
only a crystal, a 10.7MHz IF filter, and a few discrete
components are required to implement a complete
antenna/digital data solution.

The MAX7030 is available in a small, 5mm x 5mm, 32­pin thin QFN package, and is specified to operate over
the automotive -40°C to +125°C temperature range.

†

Consult factory for availability.

Applications

2-Way Remote Keyless Entry

Security Systems

Home Automation

Remote Controls

Remote Sensing

Smoke Alarms

Garage Door Openers

Local Telemetry Systems

Features

♦ +2.1V to +3.6V or +4.5V to +5.5V Single-Supply

Operation

♦ Single-Crystal Transceiver

♦ Factory-Preset Frequency (No Serial Interface

Required)

♦ ASK/OOK Modulation
♦ +10dBm Output Power into 50Ω Load

♦ Integrated TX/RX Switch

♦ Integrated Transmit and Receive PLL, VCO, and

Loop Filter

♦ > 45dB Image Rejection

♦ Typical RF Sensitivity*: -114dBm

♦ Selectable IF Bandwidth with External Filter

♦ < 12.5mA Transmit-Mode Current

♦ < 6.7mA Receive-Mode Current

♦ < 800nA Shutdown Current

♦ Fast-On Startup Feature, <250µs

♦ Small, 32-Pin, Thin QFN Package

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3706; Rev 0; 5/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART

TEMP RANGE

PIN-PACKAGE

PKG

CODE

MAX7030_ATJ

T3255-3

Product Selector Guide

PART

CARRIER FREQUENCY (MHz)

MAX7030LATJ 315

MAX7030MATJ 345

MAX7030HATJ 433.92

*0.2% BER, 4kbps Manchester-encoded data, 280kHz IF BW

**EP = Exposed paddle.

Note: The MAX7030 is available with factory-preset operating
frequencies. See the Product Selector Guide for complete part
numbers.

Pin Configuration, Typical Application Circuit, and
Functional Diagram appear at end of data sheet.

-40°C to +125°C 32 Thin QFN-EP**

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

HVINto GND..........................................................-0.3V to +6.0V

PAV

DD

, AVDD, DVDDto GND ................................-0.3V to +4.0V

ENABLE, T/

R, DATA, AGC0, AGC1,

AGC2 to GND .......................................-0.3V to (HV

IN

+ 0.3V)

All Other Pins to GND...............................-0.3V to (_V

DD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)
32-Pin Thin QFN (derate 21.3mW/°C

above +70°C).............................................................1702mW

Operating Temperature Range .........................-40°C to +125°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

DC ELECTRICAL CHARACTERISTICS

(Typical Application Circuit, 50Ω system impedance, AVDD= DVDD= HVIN= PAVDD= +2.1V to +3.6V, fRF= 315MHz, 345MHz, or

433.92MHz, T

A

= -40°C to +125°C, unless otherwise noted. Typical values are at AVDD= DVDD= HVIN= PAVDD= +2.7V, TA= +25°C,

unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

UNITS

Supply Voltage (3V Mode) V

DD

HVIN, PAVDD, AVDD, and DVDD connected
to power supply

2.1 2.7 3.6 V

Supply Voltage (5V Mode) HV

IN

PAVDD, AVDD, and DVDD unconnected
from HV

IN

, but connected together

4.5 5.0 5.5 V

fRF = 315MHz 3.5 5.4

Transmit mode, PA off,
V

DATA

at 0% duty

cycle (Note 2)

f

RF

= 434MHz 4.3 6.7

fRF = 315MHz 7.6

Transmit mode, V

DATA

at 50% duty cycle
(Notes 3, 4)

f

RF

= 434MHz 8.4

fRF = 315MHz

Transmit mode, V

DATA

at 100% duty cycle
(Note 2)

f

RF

= 434MHz

6.1 7.9

6.4 8.3

mA

Deep-sleep
(3V mode)

0.8 8.8

TA < +85°C,
typ at +25°C
(Note 4)

Deep-sleep
(5V mode)

2.4

µA

6.4 8.2

6.7 8.4

mA

Deep-sleep
(3V mode)

8.0

Supply Current I

DD

TA < +125°C,
typ at +125°C
(Note 2)

Deep-sleep
(5V mode)

µA

Voltage Regulator V

REG

HVIN = 5V, I

LOAD

= 15mA 3.0 V

DIGITAL I/O

Input-High Threshold V

IH

(Note 2)

V

Input-Low Threshold V

IL

(Note 2)

0.1 x
V

SYMBOL

MIN TYP MAX

Receiver 315MHz

Receiver 434MHz

Receiver 315MHz

Receiver 434MHz

11.6 19.1

12.4 20.4

0.9 x
HV

14.9 39.3

IN

12.3

13.6

10.9

34.2

HV

IN

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(Typical Application Circuit, 50Ω system impedance, PAVDD= AVDD= DVDD= HVIN= +2.1V to +3.6V, fRF= 315MHz, 345MHz, or

433.92MHz, T

A

= -40°C to +125°C, unless otherwise noted. Typical values are at PAVDD= AVDD= DVDD= HVIN= +2.7V, TA= +25°C,

unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

GENERAL CHARACTERISTICS

Frequency Range

MHz

Maximum Input Level P

RFIN

0

dBm

fRF = 315MHz (Note 6) 32

Transmit Efficiency 100% Duty
Cycle

f

RF

= 434MHz (Note 6) 30

%

fRF = 315MHz (Note 6) 24

Transmit Efficiency 50% Duty
Cycle

f

RF

= 434MHz (Note 6) 22

%

ENABLE or T/R transition low to high,
transmitter frequency settled to within
50kHz of the desired carrier

ENABLE or T/R transition low to high,
transmitter frequency settled to within 5kHz
of the desired carrier

Power-On Time t

ON

ENABLE transition low to high, or T/R
transition high to low, receiver startup time
(Note 5)

µs

RECEIVER

Sensitivity

0.2% BER, 4kbps Manchester
data rate, 280kHz IF BW,
average RF power

dBm

Image Rejection 46 dB

POWER AMPLIFIER

TA = +25°C (Note 4) 4.6
TA = +125°C, PAVDD = AVDD = DVDD =
HV

IN

= +2.1V (Note 2)

3.9 6.7

Output Power P

OUT

TA = -40°C, PAVDD = AVDD = DVDD =
HV

IN

= +3.6V (Note 4)

dBm

Modulation Depth 82 dB

Maximum Carrier Harmonics With output-matching network -40 dBc

Reference Spur -50 dBc

DC ELECTRICAL CHARACTERISTICS (continued)

(Typical Application Circuit, 50Ω system impedance, AVDD= DVDD= HVIN= PAV

DD

=

+2.1V to +3.6V, fRF= 315MHz, 345MHz, or

433.92MHz, T

A

= -40°C to +125°C, unless otherwise noted. Typical values are at AVDD= DVDD= HVIN= PAV

DD

=

+2.7V, T

A

= +25°C,

unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Pulldown Sink Current

20 µA

Output-Low Voltage V

OL

I

SINK

= 500µA

V

Output-High Voltage V

OH

I

SOURCE

= 500µA H V

IN

- 0.26 V

AGC0-2, ENABLE, T/R, DATA (HVIN = 5.5V)

0.15

315/345/

433.92

315MHz -114

434MHz -113

200

350

250

10.0 15.5

13.1 15.8

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(Typical Application Circuit, 50Ω system impedance, PAVDD= AVDD= DVDD= HVIN= +2.1V to +3.6V, fRF= 315MHz, 345MHz, or

433.92MHz, T

A

= -40°C to +125°C, unless otherwise noted. Typical values are at PAVDD= AVDD= DVDD= HVIN= +2.7V, TA= +25°C,

unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

UNITS

PHASE-LOCKED LOOP

Transmit VCO Gain K

VCO

MHz/V

10kHz offset, 200kHz loop BW -68

Transmit PLL Phase Noise

1MHz offset, 200kHz loop BW -98

dBc/Hz

Receive VCO Gain

MHz/V

10kHz offset, 500kHz loop BW -80

Receive PLL Phase Noise

1MHz offset, 500kHz loop BW -90

dBc/Hz

Transmit PLL

Loop Bandwidth

Receive PLL

kHz

Reference Frequency Input Level

0.5 V

P-P

LOW-NOISE AMPLIFIER/MIXER (Note 8)

fRF = 315MHz

LNA Input Impedance Z

INLNA

fRF = 434MHz

fRF = 315MHz 50

High-gain state

f

RF

= 434MHz 45

fRF = 315MHz 13

Voltage-Conversion Gain

Low-gain state

f

RF

= 434MHz 9

dB

High-gain state -42

Input-Referred, 3rd-Order
Intercept Point

IIP3

Low-gain state -6

dBm

Mixer-Output Impedance

Ω

LO Signal Feedthrough to
Antenna

dBm

RSSI

Input Impedance

Ω

Operating Frequency f

IF

MHz

3dB Bandwidth 10 MHz

Gain 15

mV/dB

ANALOG BASEBAND

Maximum Data-Filter Bandwidth 50 kHz

Maximum Data-Slicer Bandwidth

kHz

Maximum Peak-Detector
Bandwidth

50 kHz

Manchester coded 33

Maximum Data Rate

Nonreturn to zero (NRZ) 66

kbps

SYMBOL

MIN TYP MAX

340

340

200

500

Normalized to 50Ω

1 - j4.7

1- j3.3

330

-100

330

10.7

100

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

_______________________________________________________________________________________ 5

AC ELECTRICAL CHARACTERISTICS (continued)

(Typical Application Circuit, 50Ω system impedance, PAVDD= AVDD= DVDD= HVIN= +2.1V to +3.6V, fRF= 315MHz, 345MHz, or

433.92MHz, T

A

= -40°C to +125°C, unless otherwise noted. Typical values are at PAVDD= AVDD= DVDD= HVIN= +2.7V, TA= +25°C,

unless otherwise noted.) (Note 1)

Note 1:

Supply current, output power, and efficiency are greatly dependent on board layout and PAOUT match.

Note 2: 100% tested at T

A

= +125°C. Guaranteed by design and characterization overtemperature.

Note 3: 50% duty cycle at 10kHz ASK data (Manchester coded).
Note 4: Guaranteed by design and characterization. Not production tested.
Note 5: Time for final signal detection; does not include baseband filter settling.
Note 6: Efficiency = P

OUT

/ (VDDx IDD).

Note 7: Dependent on PC board trace capacitance.
Note 8: Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 12nH

inductive degeneration from the LNA source to ground. The impedance at 434MHz includes a 10nH induc­tive degeneration connected from the LNA source to ground. The equivalent input circuit is 50Ω in series
with ~2.2pF. The voltage conversion is measured with the LNA input-matching inductor, the degeneration
inductor, and the LNA/mixer tank in place, and does not include the IF filter insertion loss.

Typical Operating Characteristics

(Typical Operating Circuit, PAVDD= AVDD= DVDD= HVIN= +3.0V, fRF= 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded,

0.2% BER, T

A

= +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX7030 toc01

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

3.33.02.72.4

5.8

6.0

6.2

6.4

6.6

6.8

7.0

5.6

2.1 3.6

+85°C

+125°C

+25°C

-40°C

SUPPLY CURRENT vs. RF FREQUENCY

MAX7030 toc02

RF FREQUENCY (MHz)

SUPPLY CURRENT (mA)

425400325 350 375

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.0
300 450

+85°C

+125°C

+25°C

-40°C

DEEP-SLEEP CURRENT vs. TEMPERATURE

MAX7030 toc03

TEMPERATURE (°C)

DEEP-SLEEP CURRENT (µA)

1108535 60-10-15

2

4

6

8

10

12

14

16

18

0

-40

VCC = +3.6V

VCC = +3.0V

VCC = +2.1V

RECEIVER

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CRYSTAL OSCILLATOR

Crystal Frequency f

XTAL

(f

RF

-10.7)

/ 24

MHz

Maximum Crystal Inductance 50 mH

Frequency Pulling by V

DD

2

ppm/V

Crystal Load Capacitance (Note 7) 4.5 pF

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL

6 _______________________________________________________________________________________

BIT-ERROR RATE

vs. AVERAGE INPUT POWER

MAX7030 toc04

AVERAGE INPUT POWER (dBm)

BIT-ERROR RATE (%)

-113-115-117-119

0.1

1

10

100

0.01

-121 -111

fRF = 434MHz

fRF = 315MHz

0.2% BER

SENSITIVITY vs. TEMPERATURE

TEMPERATURE (°C)

SENSITIVITY (dBm)

11085603510-15

-117

-114

-111

-108

-105

-102

-120

-40

MAX7030 toc05

fRF = 434MHz

fRF = 315MHz

RSSI vs. RF INPUT POWER

MAX7030 toc06

RF INPUT POWER (dBm)

RSSI (V)

-10-30-70 -50-90-110

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0

-130 10

LOW-GAIN MODE

HIGH-GAIN MODE

AGC SWITCH
POINT

AGC HYSTERESIS: 3dB

RSSI AND DELTA vs. IF INPUT POWER

MAX7030 toc07

IF INPUT POWER (dBm)

RSSI (V)

-10-30-50-70

0.3

0.6

0.9

1.2

1.5

1.8

2.1

0

-90 10

-2.5

-1.5

-0.5

0.5

1.5

2.5

3.5

-3.5

DELTA (%)

RSSI

DELTA

SYSTEM GAIN vs. IF FREQUENCY

MAX7030 toc08

IF FREQUENCY (MHz)

SYSTEM GAIN (dBm)

252015105

-10

0

10

20

30

40

50

-20
030

LOWER SIDEBAND

UPPER SIDEBAND

FROM RFIN

TO MIXOUT

f

RF

= 434MHz

48dB IMAGE

REJECTION

IMAGE REJECTION vs. TEMPERATURE

MAX7030 toc09

TEMPERATURE (°C)

IMAGE REJECTION (dB)

11085603510-15

44

46

48

42

-40

fRF = 433MHz

fRF = 315MHz

S11 SMITH PLOT OF R

FIN

MAX7030 toc12

433MHz

500MHz

400MHz

NORMALIZED IF GAIN vs. IF FREQUENCY

MAX7030 toc10

IF FREQUENCY (MHz)

NORMALIZED IF GAIN (dB)

10

-16

-12

-8

-4

0

-20
1 100

S11 vs. RF FREQUENCY

MAX7030 toc11

RF FREQUENCY (MHz)

S11 (dB)

450400350300250

-18

-12

-6

0

-24
200 500

433.92MHz

Typical Operating Characteristics (continued)

(Typical Operating Circuit, PAVDD= AVDD= DVDD= HVIN= +3.0V, fRF= 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded,

0.2% BER, TA= +25°C, unless otherwise noted.)

RECEIVER

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

_______________________________________________________________________________________ 7

INPUT IMPEDANCE

vs. INDUCTIVE DEGENERATION

MAX7030 toc14

INDUCTIVE DEGENERATION (nH)

REAL IMPEDANCE (Ω)

10

30

40

50

60

70

80

90

20

IMAGINARY IMPEDANCE (Ω)

-210

-200

-190

-180

-170

-160

-150

-220

1 100

fRF = 434MHz

IMAGINARY

IMPEDANCE

REAL IMPEDANCE

PHASE NOISE vs. OFFSET FREQUENCY

MAX7030 toc15

OFFSET FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

1M100k10k1k

-110

-100

-90

-80

-70

-60

-50

-120
100 10M

fRF = 315MHz

PHASE NOISE vs. OFFSET FREQUENCY

MAX7030 toc16

OFFSET FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

-110

-100

-90

-80

-70

-60

-50

-120

fRF = 433MHz

1M100k10k1k100 10M

Typical Operating Characteristics (continued)

(Typical Operating Circuit, PAVDD= AVDD= DVDD= HVIN= +3.0V, fRF= 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded,

0.2% BER, TA= +25°C, unless otherwise noted.)

RECEIVER

INPUT IMPEDANCE

vs. INDUCTIVE DEGENERATION

MAX7030 toc13

INDUCTIVE DEGENERATION (nH)

REAL IMPEDANCE (Ω)

10

30

40

50

60

70

80

90

20

IMAGINARY IMPEDANCE (Ω)

-280

-270

-260

-250

-240

-230

-220

-290

1 100

fRF = 315MHz

IMAGINARY

IMPEDANCE

REAL IMPEDANCE

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(Typical Operating Circuit, PAVDD= AVDD= DVDD= HVIN= +3.0V, fRF= 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded,

0.2% BER, TA= +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX7030 toc17

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

3.33.02.72.4

10

12

14

16

8

2.1 3.6

fRF = 315MHz
PA ON
WITHOUT ENVELOPE SHAPING

TA = +85°C

TA = +125°C

TA = -40°C

TA = +25°C

SUPPLY CURRENT (mA)

2.5

3.0

3.5

4.0

5.0

4.5

5.5

6.0

2.0

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX7030 toc18

SUPPLY VOLTAGE (V)

3.33.02.72.42.1 3.6

fRF = 315MHz
PA OFF

TA = +85°C

TA = +125°C

TA = -40°C

TA = +25°C

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX7030 toc19

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

3.33.02.72.4

11

13

15

17

9

2.1 3.6

fRF = 434MHz
PA ON
WITHOUT ENVELOPE SHAPING

TA = +85°C

TA = +125°C

TA = -40°C

TA = +25°C

SUPPLY CURRENT (mA)

3.0

3.5

4.0

5.0

4.5

5.5

6.0

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX7030 toc20

SUPPLY VOLTAGE (V)

3.33.02.72.42.1 3.6

fRF = 434MHz
PA OFF

TA = +85°C

TA = +125°C

TA = -40°C

TA = +25°C

SUPPLY CURRENT vs. OUTPUT POWER

AVERAGE OUTPUT POWER (dBm)

62-10 -6 -2

5

6

7

8

9

10

11

12

4

-14 10

MAX7030 toc21

SUPPLY CURRENT (mA)

fRF = 315MHz
PA ON
ENVELOPE SHAPING ENABLED

PA ON

50% DUTY CYCLE

SUPPLY CURRENT vs. OUTPUT POWER

AVERAGE OUTPUT POWER (dBm)

62-10 -6 -2

5

6

7

8

9

10

11

12

13

14

-14 10

MAX7030 toc22

SUPPLY CURRENT (mA)

fRF = 434MHz
PA ON
ENVELOPE SHAPING ENABLED

PA ON

50% DUTY CYCLE

SUPPLY CURRENT AND OUTPUT POWER

vs. EXTERNAL RESISTOR

MAX7030 toc23-1

EXTERNAL RESISTOR (Ω)

SUPPLY CURRENT (mA)

1k1001 10

4

6

8

10

12

14

16

18

2

0.1 10k

-12

-8

-4

0

4

8

12

16

-16

OUTPUT POWER (dBm)

fRF = 315MHz
PA ON

POWER

CURRENT

SUPPLY CURRENT AND OUTPUT POWER

vs. EXTERNAL RESISTOR

MAX7030 toc23-2

EXTERNAL RESISTOR (Ω)

SUPPLY CURRENT (mA)

1k1001 10

4

6

8

10

12

14

16

18

2

0.1 10k

-12

-8

-4

0

4

8

12

16

-16

OUTPUT POWER (dBm)

fRF = 433MHz
PA ON

POWER

CURRENT

TRANSMITTER

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

_______________________________________________________________________________________ 9

OUTPUT POWER vs. SUPPLY VOLTAGE

MAX7030 24-1

SUPPLY VOLTAGE (V)

OUTPUT POWER (dBm)

3.33.02.72.4

6

8

10

12

14

4

2.1 3.6

fRF = 315MHz
PA ON
ENVELOPE SHAPING DISABLED

TA = -40°C

TA = +25°C

TA = +125°C

TA = +85°C

OUTPUT POWER vs. SUPPLY VOLTAGE

MAX7030 24-2

SUPPLY VOLTAGE (V)

OUTPUT POWER (dBm)

3.33.02.72.4

6

8

10

12

14

4

2.1 3.6

fRF = 315MHz
PA ON
ENVELOPE SHAPING ENABLED

TA = +125°C

TA = +25°C

TA = -40°C

TA = +85°C

OUTPUT POWER vs. SUPPLY VOLTAGE

MAX7030 25-1

SUPPLY VOLTAGE (V)

OUTPUT POWER (dBm)

3.33.02.72.4

6

8

10

12

14

4

2.1 3.6

fRF = 434MHz
PA ON
ENVELOPE SHAPING DISABLED

TA = +85°C

TA = +125°C

TA = +25°C

TA = -40°C

OUTPUT POWER vs. SUPPLY VOLTAGE

MAX7030 25-2

SUPPLY VOLTAGE (V)

OUTPUT POWER (dBm)

3.33.02.72.4

6

8

10

12

14

2.1 3.6

fRF = 434MHz
PA ON
ENVELOPE SHAPING ENABLED

TA = +85°C

TA = +125°C

TA = +25°C

TA = -40°C

EFFICIENCY vs. SUPPLY VOLTAGE

MAX7030 toc26

SUPPLY VOLTAGE (V)

EFFICIENCY (%)

3.33.02.72.4

25

30

35

40

20

2.1 3.6

TA = +85°C

TA = +125°C

TA = +25°C

TA = -40°C

fRF = 315MHz
PA ON

EFFICIENCY vs. SUPPLY VOLTAGE

MAX7030 toc27

SUPPLY VOLTAGE (V)

EFFICIENCY (%)

3.33.02.72.4

25

30

35

40

20

2.1 3.6

TA = +85°C

TA = +125°C

TA = +25°C

TA = -40°C

fRF = 434MHz
PA ON

EFFICIENCY vs. SUPPLY VOLTAGE

MAX7030 toc28

SUPPLY VOLTAGE (V)

EFFICIENCY (%)

3.33.02.72.4

15

20

25

30

10

2.1 3.6

TA = +85°C

TA = +125°C

TA = +25°C

TA = -40°C

fRF = 315MHz
50% DUTY CYCLE

EFFICIENCY vs. SUPPLY VOLTAGE

MAX7030 toc29

SUPPLY VOLTAGE (V)

EFFICIENCY (%)

3.33.02.72.4

20

25

30

15

2.1 3.6

TA = +85°C

TA = +125°C

TA = +25°C

TA = -40°C

fRF = 434MHz
50% DUTY CYCLE

PHASE NOISE vs. OFFSET FREQUENCY

MAX7030 toc30

OFFSET FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

1M100k10k1k

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-140
100 10M

fRF = 315MHz

Typical Operating Characteristics (continued)

(Typical Operating Circuit, PAVDD= AVDD= DVDD= HVIN= +3.0V, fRF= 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded,

0.2% BER, TA= +25°C, unless otherwise noted.)

TRANSMITTER

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL

10 ______________________________________________________________________________________

PHASE NOISE vs. OFFSET FREQUENCY

MAX7030 toc31

OFFSET FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-140

fRF = 434MHz

1M100k10k1k100 10M

REFERENCE SPUR MAGNITUDE

vs. SUPPLY VOLTAGE

MAX7030 toc32

SUPPLY VOLTAGE (V)

REFERENCE SPUR MAGNITUDE (dBc)

3.33.02.72.4

-65

-60

-55

-50

-45

-40

-70

2.1 3.6

434MHz

315MHz

-8

-6

-4

-2

0

2

4

6

8

10

-10

FREQUENCY STABILITY

vs. SUPPLY VOLTAGE

MAX7030 toc33

SUPPLY VOLTAGE (V)

FREQUENCY STABILITY (ppm)

3.33.02.72.42.1 3.6

fRF = 434MHz

fRF = 315MHz

Typical Operating Characteristics (continued)

(Typical Operating Circuit, PAVDD= AVDD= DVDD= HVIN= +3.0V, fRF= 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded,

0.2% BER, TA= +25°C, unless otherwise noted.)

TRANSMITTER

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

______________________________________________________________________________________ 11

Pin Description

PIN NAME FUNCTION

1 PAV

DD

Power-Amplifier Supply Voltage. Bypass to GND with 0.01µF and 220pF capacitors placed as close
to the pin as possible.

2 ROUT

Envelope-Shaping Output. ROUT controls the power-amplifier envelope’s rise and fall times. Connect
ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as
close to the inductor as possible with 680pF and 220pF capacitors, as shown in the Typical
Application Circuit.

3 TX/RX1

Transmit/Receive Switch Throw. Drive T/R high to short TX/RX1 to TX/RX2. Drive T/R low to disconnect
TX/RX1 from TX/RX2. Functionally identical to TX/RX2.

4 TX/RX2 Transmit/Receive Switch Pole. Typically connected to ground. See the Typical Application Circuit.

5 PAOUT

Power-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope
shaping is desired), which can be part of the output-matching network to an antenna.

6AV

DD

Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in 5V operation.
Bypass AV

DD

to GND with a 0.1µF and 220pF capacitor placed as close to the pin as possible.

7 LNAIN Low-Noise Amplifier Input. Must be AC-coupled.

8 LNASRC

Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set
the LNA input impedance.

9 LNAOUT

Low-Noise Amplifier Output. Must be connected to AV

DD

through a parallel LC tank filter. AC-couple

to MIXIN+.

10 MIXIN+ Noninverting Mixer Input. Must be AC-coupled to the LNA output.

11 MIXIN-

Inverting Mixer Input. Bypass to AVDD with a capacitor as close to the LNA LC tank filter as possible.

12 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz filter.
13 IFIN- Inverting 330Ω IF Limiter-Amplifier Input. Bypass to GND with a capacitor.

14 IFIN+ Noninverting 330Ω IF Limiter-Amplifier Input. Connect to the output of the 10.7MHz IF filter.
15 PDMIN Minimum-Level Peak Detector for Demodulator Output
16 PDMAX Maximum-Level Peak Detector for Demodulator Output
17 DS- Inverting Data Slicer Input
18 DS+ Noninverting Data Slicer Input
19 OP+ Noninverting Op-Amp Input for the Sallen-Key Data Filter
20 DF Data-Filter Feedback Node. Input for the feedback capacitor of the Sallen-Key data filter.

21, 25 N.C. No Connection. Do not connect to this pin.

22 T/R

Transmit/Receive. Drive high to put the device in transmit mode. Drive low or leave unconnected to
put the device in receive mode. It is internally pulled down.

23 ENABLE

Enable. Drive high for normal operation. Drive low or leave unconnected to put the device into shut­down mode.

24 DATA Receiver Data Output/Transmitter Data Input

26 DV

DD

Digital Power-Supply Voltage. Bypass to GND with a 0.01µF and 220pF capacitor placed as close to
the pin as possible.

27 HV

IN

High-Voltage Supply Input. For 3V operation, connect HVIN to AVDD, DVDD, and PAVDD. For 5V
operation, connect only HV

IN

to 5V. Bypass HVIN to GND with a 0.01µF and 220pF capacitor placed

as close to the pin as possible.

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL

12 ______________________________________________________________________________________

Detailed Description

The MAX7030 315MHz, 345MHz, and 433.92MHz
CMOS transceiver and a few external components pro­vide a complete transmit and receive chain from the
antenna to the digital data interface. This device is
designed for transmitting and receiving ASK data. All
transmit frequencies are generated by a fractional-N­based synthesizer, allowing for very fine frequency
steps in increments of f

XTAL

/ 4096. The receive LO is
generated by a traditional integer-N-based synthesizer.
Depending on component selection, data rates as high
as 33kbps (Manchester encoded) or 66kbps (NRZ
encoded) can be achieved.

Receiver

Low-Noise Amplifier (LNA)

The LNA is a cascode amplifier with off-chip inductive
degeneration that achieves approximately 30dB of volt­age gain that is dependent on both the antenna-match­ing network at the LNA input and the LC tank network
between the LNA output and the mixer inputs.

The off-chip inductive degeneration is achieved by
connecting an inductor from LNASRC to AGND. This
inductor sets the real part of the input impedance at
LNAIN, allowing for a more flexible match for low-input
impedances such as a PC board trace antenna. A
nominal value for this inductor with a 50Ω input imped­ance is 12nH at 315MHz and 10nH at 434MHz, but the
inductance is affected by PC board trace length.
LNASRC can be shorted to ground to increase sensitiv­ity by approximately 1dB, but the input match must
then be reoptimized.

The LC tank filter connected to LNAOUT consists of L5
and C9 (see the Typical Application Circuit). Select L5
and C9 to resonate at the desired RF input frequency.
The resonant frequency is given by:

where L

TOTAL

= L5 + L

PARASITICS

and C

TOTAL

= C9 +

C

PARASITICS

.

L

PARASITICS

and C

PARASITICS

include inductance and
capacitance of the PC board traces, package pins,
mixer-input impedance, LNA-output impedance, etc.
These parasitics at high frequencies cannot be
ignored, and can have a dramatic effect on the tank fil­ter center frequency. Lab experimentation should be
done to optimize the center frequency of the tank. The
total parasitic capacitance is generally between 5pF
and 7pF.

Automatic Gain Control (AGC)

When the AGC is enabled, it monitors the RSSI output.
When the RSSI output reaches 1.28V, which corre­sponds to an RF input level of approximately -55dBm,
the AGC switches on the LNA gain-reduction attenua­tor. The attenuator reduces the LNA gain by 36dB,
thereby reducing the RSSI output by about 540mV to
740mV. The LNA resumes high-gain mode when the
RSSI output level drops back below 680mV (approxi­mately -59dBm at the RF input) for a programmable
interval called the AGC dwell time (see Table 1). The
AGC has a hysteresis of approximately 4dB. With the
AGC function, the RSSI dynamic range is increased,
allowing the MAX7030 to reliably produce an ASK out­put for RF input levels up to 0dBm with a modulation
depth of 18dB. AGC is not required and can be dis­abled (see Table 1).

f

LC

TOTAL TOTAL

=

×

1

2π

Pin Description (continued)

PIN NAME FUNCTION

28 AGC2 AGC Enable/Dwell Time Control 2 (MSB). See Table 1. Bypass to GND with a 10pF capacitor.

29 AGC1 AGC Enable/Dwell Time Control 1. See Table 1. Bypass to GND with a 10pF capacitor.

30 AGC0 AGC Enable/Dwell Time Control 0 (LSB). See Table 1. Bypass to GND with a 10pF capacitor.

31 XTAL1 Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference.

32 XTAL2 Crystal Input 2. XTAL2 can be driven from an external AC-coupled reference.

EP GND Exposed Paddle. Solder evenly to the board’s ground plane for proper operation.

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

______________________________________________________________________________________ 13

AGC Dwell-Time Settings

The AGC dwell timer holds the AGC in low-gain state
for a set amount of time after the power level drops
below the AGC switching threshold. After that set
amount of time, if the power level is still below the AGC
threshold, the LNA goes into high-gain state. This is
important for ASK since the modulated data may have
a high level above the threshold and low level below
the threshold, which without the dwell timer would
cause the AGC to switch on every bit.

The MAX7030 uses the three AGC control pins (AGC0,
AGC1, AGC2) to set seven user-controlled, dwell-timer
settings. The AGC dwell time is dependent on the crys­tal frequency and the bit settings of the AGC control
pins. To calculate the dwell time, use the following
equation:

where K is an odd integer in decimal from 11 to 23, deter­mined by the control pin settings shown in Table 1.

To calculate the value of K, use the following equation
and use the next integer higher than the calculated
result:

K ≥ 3.3 x log10(Dwell Time x f

XTAL

)

For Manchester Code (50% duty cycle), set the dwell
time to at least twice the bit period. For nonreturn-to­zero (NRZ) data, set the dwell to greater than the peri­od of the longest string of zeros or ones. For example,
using Manchester Code at 315MHz (f

XTAL

=

12.679MHz) with a data rate of 2kbps (bit period =
250µs), the dwell time needs to be greater than 500µs:

K ≥ 3.3 x log10(500µs x 12.679) ≈ 12.546

Choose the AGC pin settings for K to be the next odd­integer value higher than 12.546, which is 13. This says
that AGC1 is set high and AGC0 and AGC2 are set low.

Mixer

A unique feature of the MAX7030 is the integrated
image rejection of the mixer. This eliminates the need
for a costly front-end SAW filter for many applications.
The advantage of not using a SAW filter is increased
sensitivity, simplified antenna matching, less board
space, and lower cost.

The mixer cell is a pair of double-balanced mixers that
perform an IQ downconversion of the RF input to the

10.7MHz intermediate frequency (IF) with low-side
injection (i.e., f

LO

= fRF- fIF). The image-rejection circuit
then combines these signals to achieve a typical 46dB
of image rejection over the full temperature range. Low­side injection is required as high-side injection is not
possible due to the on-chip image rejection. The IF out­put is driven by a source follower, biased to create a
driving impedance of 330Ω to interface with an off-chip
330Ω ceramic IF filter. The voltage-conversion gain dri­ving a 330Ω load is approximately 20dB. Note that the
MIXIN+ and MIXIN- inputs are functionally identical.

Integer-N Phase-Locked Loop (PLL)

The MAX7030 utilizes a fixed-integer-N PLL to generate
the receive LO. All PLL components, including the loop
filter, voltage-controlled oscillator, charge pump, asyn­chronous 24x divider, and phase-frequency detector
are integrated internally. The loop bandwidth is approx­imately 500kHz. The relationship between RF, IF, and
reference frequencies is given by:

f

REF

= (f

RF

- fIF) / 24

Dwell Time

f

K

XTAL

=

2

AGC2

DESCRIPTION

000AGC disabled, high gain selected

001 K = 11

010 K = 13

011 K = 15

100 K = 17

101 K = 19

110 K = 21

111 K = 23

Table 1. AGC Dwell Time Settings for

MAX7030

AGC1 AGC0

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL

14 ______________________________________________________________________________________

Intermediate Frequency (IF)

The IF section presents a differential 330Ω load to pro-
vide matching for the off-chip ceramic filter. The internal
six AC-coupled limiting amplifiers produce an overall
gain of approximately 65dB, with a bandpass filter type
response centered near the 10.7MHz IF frequency with
a 3dB bandwidth of approximately 10MHz. For ASK
data, the RSSI circuit demodulates the IF to baseband
by producing a DC output proportional to the log of the
IF signal level with a slope of approximately 15mV/dB.

Data Filter

The data filter for the demodulated data is implemented
as a 2nd-order, lowpass, Sallen-Key filter. The pole
locations are set by the combination of two on-chip
resistors and two external capacitors. Adjusting the
value of the external capacitors changes the corner fre­quency to optimize for different data rates. Set the cor­ner frequency in kHz to approximately 3 times the
fastest expected Manchester data rate in kbps from the
transmitter (1.5 times the fastest expected NRZ data
rate). Keeping the corner frequency near the data rate
rejects any noise at higher frequencies, resulting in an
increase in receiver sensitivity.

The configuration shown in Figure 1 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very-flat-amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of the capacitors, use the following equations,
along with the coefficients in Table 2:

where f

C

is the desired 3dB corner frequency.

For example, choose a Butterworth filter response with
a corner frequency of 5kHz:

Choosing standard capacitor values changes CF1to
470pF and C

F2

to 220pF. In the Typical Application Circuit,

C

F1

and CF2are named C16 and C17, respectively.

Data Slicer

The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. The threshold voltage is set by the
voltage on the DS- pin, which is connected to the nega­tive input of the data slicer comparator.

Numerous configurations can be used to generate the
data-slicer threshold. For example, the circuit in Figure
2 shows a simple method using only one resistor and
one capacitor. This configuration averages the analog
output of the filter and sets the threshold to approxi­mately 50% of that amplitude. With this configuration,
the threshold automatically adjusts as the analog signal
varies, minimizing the possibility for errors in the digital
data. The values of R and C affect how fast the thresh­old tracks the analog amplitude. Be sure to keep the
corner frequency of the RC circuit much lower (about
10 times) than the lowest expected data rate.

With this configuration, a long string of NRZ zeros or
ones can cause the threshold to drift. This configuration
works best if a coding scheme, such as Manchester
coding, which has an equal number of zeros and ones,
is used.

Figure 3 shows a configuration that uses the positive and

negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.

C

k kHz

pF

C

k kHz

pF

FF1

2

1 000

1 414 100 3 14 5

450

1 414

4 100 3 14 5

225

=≈

=≈

.

(. )( )( . )( )

.

()( )(. )( )

Ω

Ω

C

b

ak f

C

a

kf

F

c

F

c

1

2

100

4 100

=

Ω

=

Ω

()()()

()()()

π

π

MAX7030

RSSI

100kΩ

C

F2

C

F1

100kΩ

DFOP+DS+

Figure 1. Sallen-Key Lowpass Data Filter

FILTER TYPE a b

Butterworth
(Q = 0.707)

1.414 1.000

Bessel

(Q = 0.577)

1.3617 0.618

Table 2. Coefficients to Calculate CF1
and CF2

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

______________________________________________________________________________________ 15

Peak Detectors

The maximum peak detector (PDMAX) and minimum
peak detector (PDMIN), with resistors and capacitors
shown in Figure 3, create DC output voltages equal to
the high- and low-peak values of the filtered demodulat­ed signal. The resistors provide a path for the capaci­tors to discharge, allowing the peak detectors to
dynamically follow peak changes of the data filter out­put voltages.

The maximum and minimum peak detectors can be
used together to form a data slicer threshold voltage at
a value midway between the maximum and minimum
voltage levels of the data stream (see the Data Slicer
section and Figure 3). Set the RC time constant of the
peak detector combining network to at least 5 times the
data period.

If there is an event that causes a significant change in
the magnitude of the baseband signal, such as an AGC
gain-switch or a power-up transient, the peak detectors
may “catch” a false level. If a false peak is detected,
the slicing level is incorrect. The MAX7030 peak detec­tors correct these problems by temporarily tracking the
incoming baseband filter voltage when an AGC state
switch occurs, or forcing the peak detectors to track the
baseband filter output voltage until all internal circuits
are stable following an enable pin low-to-high transition
and also T/R pin high-to-low transition. The peak detec­tors exhibit a fast attack/slow decay response. This fea­ture allows for an extremely fast startup or AGC
recovery.

Transmitter

Power Amplifier (PA)

The PA of the MAX7030 is a high-efficiency, open­drain, class-C amplifier. The PA with proper output­matching network can drive a wide range of antenna
impedances, which includes a small-loop PC board

trace and a 50Ω antenna. The output-matching network
for a 50Ω antenna is shown in the Typical Application
Circuit. The output-matching network suppresses the
carrier harmonics and transforms the antenna imped­ance to an optimal impedance at PAOUT (pin 5). The
optimal impedance at PAOUT is 250Ω.

When the output-matching network is properly tuned,
the PA transmits power with a high overall efficiency of
up to 32%. The efficiency of the PA itself is more than
46%. The output power is set by an external resistor at
PAOUT, and is also dependent on the external antenna
and antenna-matching network at the PA output.

Envelope Shaping

The MAX7030 features an internal envelope-shaping
resistor, which connects between the open-drain output
of the PA and the power supply (see the Typical
Application Circuit). The envelope-shaping resistor
slows the turn-on/turn-off of the PA in ASK mode, and
results in a smaller spectral width of the modulated PA
output signal.

Fractional-N Phase-Locked Loop (PLL)

The MAX7030 utilizes a fully integrated, fractional-N,
PLL for its transmit frequency synthesizer. All PLL com­ponents, including the loop filter, are integrated inter­nally. The loop bandwidth is approximately 200kHz.

Power-Supply Connections

The MAX7030 can be powered from a 2.1V to 3.6V sup­ply or a 4.5V to 5.5V supply. If a 4.5V to 5.5V supply is
used, then the on-chip linear regulator reduces the 5V
supply to the 3V needed to operate the chip.

To operate the MAX7030 from a 3V supply, connect
PAVDD, AVDD, DVDD, and HVINto the 3V supply. When
using a 5V supply, connect the supply to HVINonly and

MAX7030

C

PDMAX PDMIN

R

C

R

DATA

SLICER

DATA

PEAK

DET

PEAK

DET

Figure 3. Generating Data-Slicer Threshold Using the Peak
Detectors

MAX7030

C

DS- DS+

R

DATA

SLICER

DATA

Figure 2. Generating Data-Slicer Threshold Using a Lowpass
Filter

connect AVDD, PAVDD, and DVDDtogether. In both
cases, bypass DVDD, HVIN, and PAVDDto GND with

0.01µF and 220pF capacitors and bypass AVDDto
GND with 0.1µF and 220pF capacitors. Bypass T/R,
ENABLE, DATA, and AGC0-2 with 10pF capacitors to
GND. Place all bypass capacitors as close to the
respective pins as possible.

Transmit/

Receive

Antenna Switch

The MAX7030 features an internal SPST RF switch that,
when combined with a few external components, allows
the transmit and receive pins to share a common
antenna (see the Typical Application Circuit). In receive
mode, the switch is open and the power amplifier is
shut down, presenting a high impedance to minimize
the loading of the LNA. In transmit mode, the switch
closes to complete a resonant tank circuit at the PA
output and forms an RF short at the input to the LNA. In
this mode, the external passive components couple the
output of the PA to the antenna and protect the LNA
input from strong transmitted signals.

The switch state is controlled by the T/R pin (pin 22).
Drive T/R high to put the device in transmit mode; drive
T/R low to put the device in receive mode.

Crystal Oscillator (XTAL)

The XTAL oscillator in the MAX7030 is designed to pre­sent a capacitance of approximately 3pF between the
XTAL1 and XTAL2 pins. In most cases, this corre­sponds to a 4.5pF load capacitance applied to the
external crystal when typical PC board parasitics are
added. It is very important to use a crystal with a

load capacitance that is equal to the capacitance of
the MAX7030 crystal oscillator plus PC board para­sitics. If a crystal designed to oscillate with a different

load capacitance is used, the crystal is pulled away
from its stated operating frequency, introducing an
error in the reference frequency. Crystals designed to
operate with higher differential load capacitance
always pull the reference frequency higher.

In actuality, the oscillator pulls every crystal. The crys­tal’s natural frequency is really below its specified fre­quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.

Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:

where:

fpis the amount the crystal frequency is pulled in ppm.

Cmis the motional capacitance of the crystal.

C

CASE

is the case capacitance.

C

SPEC

is the specified load capacitance.

C

LOAD

is the actual load capacitance.

When the crystal is loaded as specified, i.e.,
C

LOAD

= C

SPEC

, the frequency pulling equals zero.

f

C

CC CC

x

P

m

CASE LOAD CASE SPEC

=

+

−
+











2

11

10

6

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL

16 ______________________________________________________________________________________

32

31

30

29

28

27

26

9

10

11

12

13

14

15

18192021222324

7654321

MAX7030

THIN QFN

TOP VIEW

ROUT

PAV

DD

TX/RX1

TX/RX2

PAOUT

AV

DD

LNAIN

8

LNASRC

XTAL2

XTAL1

AGC0

AGC1

AGC2

HV

IN

DV

DD

25

N.C.

DATA

ENABLE

T/R

N.C.

DF

OP+

DS+17DS-

PDMIN

IFIN+

16

PDMAX

IFIN-

MIXOUT

MIXIN-

MIXIN+

LNAOUT

Pin Configuration

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

______________________________________________________________________________________ 17

COMPONENT

VALUE FOR

433.92MHz RF

VALUE FOR

315MHz RF

DESCRIPTION

C1 220pF 220pF 10%

C2 680pF 680pF 10%

C3 6.8pF 12pF 5%

C4 6.8pF 10pF 5%

C5 10pF 22pF 5%

C6 220pF 220pF 10%

C7 0.1µF 0.1µF 10%

C8 100pF 100pF 5%

C9 1.8pF 2.7pF ±0.1pF

C10 100pF 100pF 5%

C11 220pF 220pF 10%

C12 100pF 100pF 5%

C13 1500pF 1500pF 10%

C14 0.047µF 0.047µF 10%

C15 0.047µF 0.047µF 10%

C16 470pF 470pF 10%

C17 220pF 220pF 10%

C18 220pF 220pF 10%

C19 0.01µF 0.01µF 10%

C20 100pF 100pF 5%

C21 100pF 100pF 5%

C22 220pF 220pF 10%

C23 0.01µF 0.01µF 10%

C24 0.01µF 0.01µF 10%

L1 22nH 27nH Coilcraft 0603CS

L2 22nH 30nH Coilcraft 0603CS

L3 22nH 30nH Coilcraft 0603CS

L4 10nH 12nH Coilcraft 0603CS

L5 16nH 30nH Murata LQW18A

L6 68nH 100nH Coilcraft 0603CS
R1 100kΩ 100kΩ 5%
R2 100kΩ 100kΩ 5%
R3 0Ω 0Ω —

Y1 17.63416MHz 12.67917MHz Crystal, 4.5pF load capacitance

Y2 10.7MHz ceramic filter 10.7MHz ceramic filter Murata SFECV10.7 series

Table 3. Component Values for Typical Application Circuit

Note: Component values vary depending on PC board layout.

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL

18 ______________________________________________________________________________________

1

2

3

4

5

6

7

8

C8

L3

C6

910

11

C10

C12

C9

12

L5

C11

13

IN OUTGND

14

15

16

Y2

C13

17

18

19

20

21

22

23

24

C17

R1

25262728293032 31

AGC1

AGC0

MAX7030

3.0V

C23

V

DD

V

DD

PAV

DD

ROUT

TX/RX1

TX/RX2

PAOUT

AV

DD

LNAIN

LNASRC

LNAOUT

MIXIN+

MIXIN-

IFIN+

IFIN-

PDMIN

PDMAX

MIXOUT

DS-

DS+

OP+

DF

N.C.

T/R

ENABLE

DATA

N.C.

DV

DD

HVIN

AGC2

AGC1

AGC0

XTAL1

XTAL2

AGC2

C20

C21

Y1

L4

C14

C15

DATA

ENABLE

C16

TRANSMIT/
RECEIVE

C22

C5

C4

C18

C19

C7

L1

L2

C1C2

R2

R3*

*OPTIONAL POWER-ADJUST RESISTOR

C24

EXPOSED

PADDLE

C3

L6

V

DD

V

DD

V

DD

Typical Application Circuit

Chip Information

PROCESS: CMOS

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

______________________________________________________________________________________ 19

LNA

90°

0°

RSSI

IF LIMITING

AMPS

100kΩ

100kΩ

DATA FILTER

7

8

9 10 11 12

14

13

20

19

RX

DATA

18

15

16

17

30

29

28

24

23

22

DIGITAL LOGIC

31

32

CRYSTAL

OSCILLATOR

27

3.0V

REGULATOR

6

26

PA

MAX7030

5

12

RX VCO

RX

FREQUENCY

DIVIDER

PHASE

DETECTOR

CHARGE

PUMP

LOOP FILTER

TX

FREQUENCY

DIVIDER

∆Σ

MODULATOR

Σ

I

Q

TX VCO

EXPOSED

PADDLE

LNAIN

LNASRC

TX/RX1 TX/RX2

XTAL1

XTAL2

HV

IN

AV

DD

ROUT PAV

DD

PAOUT T/R DVDDENABLE

DATA

AGC2

AGC1

AGC0

DS-

PDMAX

PDMIN

DS+

OP+

DF

IFIN+ IFIN-MIXOUT

MIXIN-MIXIN+LNAOUT

3

4

Functional Diagram

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL

MAX7030

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

QFN THIN.EPS

D2

(ND-1) X e

e

D

C

PIN # 1
I.D.

(NE-1) X e

E/2

E

0.08 C

0.10 C

A

A1

A3

DETAIL A

E2/2

E2

0.10 M C A B

PIN # 1 I.D.

b

0.35x45°

D/2

D2/2

L

C

L

C

e e

L

CC

L

k

LL

DETAIL B

L

L1

e

XXXXX

MARKING

H

1

2

21-0140

PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm

-DRAWING NOT TO SCALE-

L

e/2

COMMON DIMENSIONS

3.353.15T2855-1 3.25 3.353.15 3.25

MAX.

3.20

EXPOSED PAD VARIATIONS

3.00T2055-2 3.10

D2

NOM.MIN.

3.203.00 3.10

MIN.E2NOM. MAX.

NE

ND

PKG.
CODES

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN

0.25 mm AND 0.30 mm FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3, AND T2855-6.

NOTES:

SYMBOL

PKG.

N

L1

e

E

D

b

A3

A

A1

k

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

JEDEC

T1655-1 3.203.00 3.10 3.00 3.10 3.20

0.70 0.800.75

4.90

4.90

0.25

0.250--

4

WHHB

4

16

0.350.30

5.10

5.105.00

0.80 BSC.

5.00

0.05

0.20 REF.

0.02

MIN. MAX.NOM.

16L 5x5

3.10

T3255-2

3.00

3.20

3.00 3.10 3.20

2.70

T2855-2 2.60 2.602.80 2.70 2.80

L

0.30 0.500.40

---

---

WHHC

20

5

5

5.00

5.00

0.30

0.55

0.65 BSC.

0.45

0.25

4.90

4.90

0.25

0.65

--

5.10

5.10

0.35

20L 5x5

0.20 REF.

0.75

0.02

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

---

WHHD-1

28

7

7

5.00

5.00

0.25

0.55

0.50 BSC.

0.45

0.25

4.90

4.90

0.20

0.65

--

5.10

5.10

0.30

28L 5x5

0.20 REF.

0.75

0.02

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

---

WHHD-2

32

8

8

5.00

5.00

0.40

0.50 BSC.

0.30

0.25

4.90

4.90

0.50

--

5.10

5.10

32L 5x5

0.20 REF.

0.75

0.02

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

0.20 0.25 0.30

DOWN
BONDS
ALLOWED

NO

YES3.103.00 3.203.103.00 3.20T2055-3

3.103.00 3.203.103.00 3.20T2055-4

T2855-3 3.15 3.25 3.35 3.15 3.25 3.35

T2855-6 3.15 3.25 3.35 3.15 3.25 3.35

T2855-4 2.60 2.70 2.80 2.60 2.70 2.80

T2855-5 2.60 2.70 2.80 2.60 2.70 2.80

T2855-7 2.60 2.70

2.80

2.60 2.70 2.80

3.203.00 3.10T3255-3 3.203.00 3.10

3.203.00 3.10T3255-4 3.203.00 3.10

NO

NO
NO

NO

NO

NO

NO

NO

YES
YES

YES

YES

3.203.00T1655-2 3.10 3.00 3.10 3.20 YES
NO3.203.103.003.10T1655N-1 3.00 3.20

3.353.15T2055-5 3.25 3.15 3.25 3.35

YES

3.35

3.15T2855N-1 3.25 3.15 3.25 3.35

NO

3.35

3.15T2855-8 3.25 3.15 3.25 3.35

YES

3.203.10T3255N-1 3.00

NO

3.203.103.00

L

0.40

0.40

**

**
**
**

**

**

**
**
**
**

**

**
**

**
**
**

**

**

**

SEE COMMON DIMENSIONS TABLE

±0.15

11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.

H

2

2

21-0140

PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm

-DRAWING NOT TO SCALE-

12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.

3.30T4055-1 3.20 3.40 3.20 3.30 3.40

**

YES

0.0500.02

0.600.40 0.50

10

-----

0.30

40
10

0.40 0.50

5.10

4.90 5.00

0.25 0.35 0.45

0.40 BSC.

0.15

4.90

0.250.20

5.00 5.10

0.20 REF.

0.70

MIN.

0.75 0.80

NOM.

40L 5x5

MAX.

13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.