The MAX6965 I2C™-compatible serial interfaced peripheral provides microprocessors with nine additional output ports. Each output is an open-drain current-sinking
output rated to 50mA at 7V. All outputs are capable of
driving LEDs, or providing logic outputs with external
resistive pullup up to 7V.
Eight-bit PWM current control is also integrated. Four of
the bits are global control and apply to all LED outputs
to provide coarse adjustment of current from fully off to
fully on with 14 intensity steps. Additionally each output
then has an individual 4-bit control, which further
divides the globally set current into 16 more steps.
Alternatively, the current control can be configured as a
single 8-bit control that sets all outputs at once.
Each output has independent blink timing with two blink
phases. LEDs can be individually set to be either on or off
during either blink phase, or to ignore the blink control.
The blink period is controlled by an external clock (up to
1kHz) on BLINK or by a register. The BLINK input can also
be used as a logic control to turn the LEDs on and off, or
as a general-purpose input (GPI).
The MAX6965 is controlled through a 2-wire I
2
C serial
interface, and can be configured to one of four I2C
addresses.
Applications
Features
♦ 400kbps, 2-Wire Serial Interface, 5.5V Tolerant
♦ 2V to 3.6V Operation
♦ Overall 8-Bit PWM LED Intensity Control
Global 16-Step Intensity Control
Plus Individual 16-Step Intensity Controls
♦ Two-Phase LED Blinking
♦ High Port Output Current—Each Port 50mA (max)
♦ RST Input Clears the Serial Interface and
Restores Power-Up Default State
♦ Outputs are 7V-Rated Open Drain
♦ Low Standby Current (1.2µA (typ), 3.3µA (max))
♦ Tiny 3mm x 3mm, Thin QFN Package
♦ -40°C to +125°C Temperature Range
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage (with respect to GND)
V+ .............................................................................-0.3V to +4V
SCL, SDA, AD0, BLINK, RST ...................................-0.3V to +6V
O0–O8 ......................................................................-0.3V to +8V
DC Current on O0 to O8 .....................................................55mA
DC Current on SDA.............................................................10mA
Maximum GND Current ....................................................190mA
Continuous Power Dissipation (T
A
= +70°C)
16-Pin QSOP (derate 8.3mW/°C over +70°C)..............666mW
16-Pin QFN (derate 14.7mW/°C over +70°C) ............1176mW
(Typical Operating Circuit, V+ = 2V to 3.6V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)
(Note 1)
Note 1: All parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 3: Guaranteed by design.
Note 4: C
b
= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x VDDand 0.7 x VDD.
Note 5: I
SINK
≤ 6mA. Cb= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x VDDand 0.7 x VDD.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
115BLINKInput Port. Configurable as blink control or general-purpose input.
216RST
31AD0
Reset Input. Active low clears the 2-wire interface and puts the device in same
condition as power-up reset.
Address Input. Sets device slave address. Connect to either GND, V+, SCL, or
SDA to give 4 logic combinations. See Table 1.
4–7, 9–132–5, 7–11O0–O8Output Ports. O0–O8 are open-drain outputs rated at 7V, 50mA.
86GNDGround. Do not sink more than 190mA into the GND pin.
1412SCLI2C-Compatible Serial Clock Input
1513SDAI2C-Compatible Serial Data I/O
1614V+Positive Supply Voltage. Bypass V+ to GND with a 0.047µF ceramic capacitor
—PADExposed PadExposed pad on packaged underside. Connect to GND.
SINK CURRENT vs. V
ONLY ONE OUTPUT LOADED
V+ = 2.7V
050
SINK CURRENT (mA)
V+ = 2V
OL
MAX6965 toc09
V+ = 3.6V
V+ = 3.3V
45403530252015105
MAX6965
Functional Overview
The MAX6965 is a general-purpose output (GPO)
peripheral that provides nine output ports, O0–O8, controlled through an I2C-compatible serial interface. All outputs sink loads up to 50mA connected to external
supplies up to 7V, independent of the MAX6965’s supply
voltage. The MAX6965 is rated for a ground current of
190mA, allowing all nine outputs to sink 20mA at the
same time. Figure 1 shows the output structure of the
MAX6965. The outputs default to logic high (high impedance unless external pullup resistors are used) on
power-up.
Output Control and LED Blinking
The blink phase 0 register sets the output logic levels of
the 8 outputs O0–O7 (Table 6). This register controls
the port outputs if the blink function is disabled. A duplicate register, the Blink Phase 1 register, is also used if
the blink function is enabled (Table 7). In blink mode,
the outputs can be flipped between using the blink
phase 0 register, and the blink phase 1 register using
hardware control (the BLINK input) and/or software
control (the blink flip flag in the configuration register)
(Table 4).
The 9th output, O8, is controlled through 2 bits in the
Configuration register, which provide the same static or
blink control as the other eight outputs (Table 4).
The logic level of the BLINK input may be read back
through the blink status bit in the configuration register
(Table 4). The BLINK input, therefore, may be used as
a general-purpose logic input (GPI port) if the blink
function is not required.
PWM Intensity Control
The MAX6965 includes an internal oscillator, nominally
32kHz, to generate PWM timing for LED intensity control. PWM intensity control can be enabled on an output-by-output basis, allowing the MAX6965 to provide
any mix of PWM LED drives and glitch-free logic outputs (Table 8). PWM can be disabled entirely, in which
case all outputs are static and the MAX6965 operating
current is lowest because the internal oscillator is
turned off.
PWM intensity control uses a 4-bit master control and 4
bits of individual control per output (Tables 11 and 12).
The 4-bit master control provides 16 levels of overall
intensity control, which applies to all PWM-enabled outputs. The master control sets the maximum pulse width
from 1/15 to 15/15 of the PWM time period. The individual settings comprise a 4-bit number, further reducing
the duty cycle to be from 1/16 to 15/16 of the time window set by the master control.
For applications requiring the same PWM setting for all
output ports, a single global PWM control can be used
instead of all the individual controls to simplify the control software and provide 240 steps of intensity control
(Tables 8 and 11).
The MAX6965 includes a register byte, which is available as general-user RAM (Table 2). This byte is reset
to the value 0xFF on power-up and when the RST input
is taken low (Table 3).
Standby Mode
When the serial interface is idle and the PWM intensity
control is unused, the MAX6965 automatically enters
standby mode. If the PWM intensity control is used, the
operating current is slightly higher because the internal
PWM oscillator is running. When the serial interface is
active, the operating current also increases because
the MAX6965, like all I2C slaves, has to monitor every
transmission.
Serial Interface
Serial Addressing
The MAX6965 operates as a slave that sends and
receives data through an I2C-compatible 2-wire interface. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and
from the MAX6965 and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX6965 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on SDA. The MAX6965 SCL line operates
only as an input. A pullup resistor, typically 4.7kΩ, is
required on SCL if there are multiple masters on the 2wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX6965
7-bit slave address plus R/W bit, a register address
byte, one or more data bytes, and finally a STOP condition (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX6965, the device generates the acknowledge bit because the MAX6965 is
the recipient. When the MAX6965 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Slave Address
The MAX6965 has a 7-bit long slave address (Figure 6).
The eighth bit following the 7-bit slave address is the
R/W bit. The R/W bit is low for a write command, high
for a read command.
The second (A5), third (A4), fourth (A3), sixth (A1), and
last (A0) bits of the MAX6965 slave address are always
1, 0, 0, 0, and 0. Slave address bits A6 and A2 are
selected by the address input AD0. AD0 can be connected to GND, V+, SDA, or SCL. The MAX6965 has
four possible slave addresses (Table 1), and therefore
a maximum of four MAX6965 devices can be controlled
independently from the same interface.
Message Format for Writing the MAX6965
A write to the MAX6965 comprises the transmission of
the MAX6965’s slave address with the R/W bit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte. The command
byte determines which register of the MAX6965 is to be
written to by the next byte, if received (Table 2). If a
STOP condition is detected after the command byte is
received, then the MAX6965 takes no further action
beyond storing the command byte.
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register of
the MAX6965 selected by the command byte (Figure 8).
If multiple data bytes are transmitted before a STOP condition is detected, these bytes are generally stored in
subsequent MAX6965 internal registers because the
command byte address autoincrements (Table 2). A
diagram of a write to the output ports registers (blink
phase 0 register or blink phase 1 register) is given in
Figure 10.
The MAX6965 is read using the MAX6965’s internally
stored command byte as an address pointer the same
way the stored command byte is used as an address
pointer for a write. The pointer autoincrements after
each data byte is read using the same rules as for a
write (Table 2). Thus, a read is initiated by first configuring the MAX6965’s command byte by performing a
write (Figure 7). The master can now read n consecutive bytes from the MAX6965 with the first data byte
being read from the register addressed by the initialized command byte. When performing read-after-write
verification, remember to reset the command byte’s
address because the stored command byte address
has been autoincremented after the write (Table 2).
If the MAX6965 is operated on a 2-wire interface with
multiple masters, a master reading the MAX6965 should
use a repeated start between the write, which sets the
MAX6965’s address pointer, and the read(s) that takes
the data from the location(s) (Table 2). This is because it
is possible for master 2 to take over the bus after master
1 has set up the MAX6965’s address pointer but before
master 1 has read the data. If master 2 subsequently
changes the MAX6965’s address pointer, then master
1’s delayed read can be from an unexpected location.
Command Address Autoincrementing
The command address stored in the MAX6965 circulates around grouped register functions after each data
byte is written or read (Table 2).
Device Reset
The reset input RST is an active-low input. When taken
low, RST clears any transaction to or from the MAX6965
on the serial interface and configures the internal registers to the same state as a power-up reset (Table 3).
The MAX6965 then waits for a START condition on the
serial interface.
Detailed Description
Initial Power-Up
On power-up, and whenever the RST input is pulled
low, all control registers are reset and the MAX6965
enters standby mode (Table 3). Power-up status makes
all outputs logic high (high impedance if external pullup
resistors are not fitted) and disables both the PWM
oscillator and blink functionality. The RST input can be
used as a hardware shutdown input, which effectively
turns off any LED (or other) loads and puts the device
into its lowest power condition.
Configuration Register
The configuration register is used to configure the PWM
intensity mode and blink behavior, operate the O8 output, and read back the BLINK input logic level (Table 4).
Blink Mode
In blink mode, the outputs can be flipped between
using either the blink phase 0 register or the blink
phase 1 register. Flip control is both hardware (the
BLINK input) and software control (the blink flip flag B
in the configuration register) (Table 4).
The blink function can be used for LED effects by programming different display patterns in the two sets of
output port registers, and using the software or hardware controls to flip between the patterns.
If the blink phase 1 register is written with 0xFF, then
the BLINK input can be used as a hardware disable to,
for example, instantly turn off an LED pattern programmed into the blink phase 0 register. This technique can be further extended by driving the BLINK
input with a PWM signal to modulate the LED current to
provide fading effects.
The blink mode is enabled by setting the blink enable
flag E in the configuration register (Table 4). When blink
mode is enabled, the state of the blink flip flag and
BLINK input are EXOR’ed to set the phase, and the outputs are set by either the blink phase 0 registers or the
blink phase 1 registers (Figure 11, Table 5).
The blink mode is disabled by clearing the blink enable
flag E in the configuration register (Table 4). When blink
mode is disabled, the state of the blink flip flag is
ignored, and the blink phase 0 registers alone control
the outputs.
The logic status of BLINK is made available as the readonly blink status flag blink in the configuration register
(Table 4). This flag allows BLINK to be used as an extra
general-purpose input (GPI) in applications not using the
blink function. When BLINK is going to be used as a GPI,
blink mode should be disabled by clearing the blink
enable flag E in the configuration register (Table 4).
Blink Phase Register
When the blink function is disabled, the blink phase
0 register sets the logic levels of the eight outputs
(O0 through O7) (Table 6). A duplicate register called
the blink phase 1 register is also used if the blink function is enabled (Table 7). A logic high sets the appropriate output high impedance, while a logic low makes
the port go low.
Reading a blink phase register reads the value stored
in the register, not the actual port condition. The port
output itself may or may not be at a valid logic level,
depending on the external load connected.
The 9th output, O8, is controlled through 2 bits in the
configuration register, which provide the same static or
blink control as the other eight output ports.
Set the master, O8 intensity register 0x0E to any value from 0x00 to 0x0F.
The global intensity G bit in the configuration register is don't care.
The output intensity registers 0x10 through 0x13 are don't care.
CODE
(hex)
0x01OP7OP6OP5OP4OP3OP2OP1OP0
CODE
(hex)
0x09OP7OP6OP5OP4OP3OP2OP1OP0
D7D6D5D4D3D2D1D0
D7D6D5D4D3D2D1D0
REGISTER DATA
REGISTER DATA
A mix of static and PWM outputs, with PWM
outputs using different PWM settings
A mix of static and PWM outputs, with PWM
outputs all using the same PWM setting
All outputs PWM using the same PWM
setting
Set the master, O8 intensity register 0x0E to any value from 0x10 to 0xFF.
Clear global intensity G bit to 0 in the configuration register to disable global intensity
control.
For the static outputs, set the output intensity value to 0xF.
For the PWM outputs, set the output intensity value in the range 0x0 to 0xE.
As above. Global intensity control cannot be used with a mix of static and PWM
outputs, so write the individual intensity registers with the same PWM value.
Set the master, O8 intensity register 0x0E to any value from 0x10 to 0xFF.
Set global intensity G bit to 1 in the configuration register to enable global intensity
control.
The master, O8 intensity register 0x0E is the only intensity register used.
The output intensity registers 0x10 through 0x13 are don't care.
The MAX6965 includes an internal oscillator, nominally
32kHz, to generate PWM timing for LED intensity control
or other applications such as PWM trim DACs. PWM can
be disabled entirely for all the outputs. In this case, all
outputs are static and the MAX6965 operating current is
lowest because the internal PWM oscillator is turned off.
The MAX6965 can be configured to provide any combination of PWM outputs and glitch-free logic outputs.
Each PWM output has an individual 4-bit intensity control (Table 12). When all outputs are to be used with the
same PWM setting, the outputs can be controlled
together instead of using the global intensity control
(Table 11). Table 8 shows how to set up the MAX6965
to suit a particular application.
PWM Timing
The PWM control uses a 240-step PWM period, divided
into 15 master intensity timeslots. Each master intensity
timeslot is divided further into 16 PWM cycles (Figure 12).
The master intensity operates as a gate, allowing the individual output settings to be enabled from 1 to 15 timeslots
per PWM period (Figures 13, 14, and 15) (Table 11).
Each output’s individual 4-bit intensity control only
operates during the number of timeslots gated by the
master intensity. The individual controls provide 16
intensity settings from 1/16 through 16/16 (Table 12).
Figures 16, 17, and 18 show examples of individual
intensity control settings. The highest value an individual or global setting can be set to is 16/16. This setting
forces the output to ignore the master control, and follow the logic level set by the appropriate blink phase
register bit. The output becomes a glitch-free static output with no PWM.
Using PWM Intensity Controls with Blink Disabled
When blink is disabled (Table 5), the blink phase 0 register specifies each output’s logic level during the PWM ontime (Table 6). The effect of setting an output’s blink
phase 0 register bit to 0 or 1 is shown in Table 9. With its
output bit set to zero, an LED can be controlled with 16
intensity settings from 1/16th duty through fully on, but
cannot be turned fully off using the PWM intensity control.
With its output bit set to 1, an LED can be controlled with
16 intensity settings from fully off through 15/16th duty.
Using PWM Intensity Controls with Blink Enabled
When blink is enabled (Table 5), the blink phase 0 register and blink phase 1 register specify each output’s logic
level during the PWM on-time during the respective blink
phases (Tables 6 and 7). The effect of setting an output’s
blink phase register bit to 0 or 1 is shown in Table 10.
LEDs can be flipped between either directly on and off,
or between a variety of high/low PWM intensities.
The 4 bits used for output O8’s PWM individual intensity
setting also double as the global intensity control
(Table 11). Global intensity simplifies the PWM settings
when the application requires them all to be the same,
such as for backlight applications, by replacing the
nine individual settings with one setting. Global intensity is enabled with the global intensity flag G in the configuration register (Table 4). When global PWM control
is used, the 4 bits of master intensity and 4 bits of O8
intensity effectively combine to provide an 8-bit, 240step intensity control applying to all outputs.
It is not possible to apply global PWM control to a subset of the ports, and use the others as logic outputs. To
mix static logic outputs and PWM outputs, individual
PWM control must be selected (Table 8).
Applications Information
Output Level Translation
The open-drain output architecture allows the ports to
level translate the outputs to higher or lower voltages
than the MAX6965 supply. An external pullup resistor
can be used on any output to convert the high-impedance logic-high condition to a positive voltage level.
The resistor can be connected to any voltage up to 7V.
For interfacing CMOS inputs, a pullup resistor value of
220kΩ is a good starting point. Use a lower resistance
to improve noise immunity, in applications where power
consumption is less critical, or where a faster rise time
is needed for a given capacitive load.
Driving LED Loads
When driving LEDs, a resistor in series with the LED
must be used to limit the LED current to no more than
50mA. Choose the resistor value according to the following formula:
R
LED
= (V
SUPPLY
- V
LED
- VOL) / I
LED
where:
R
LED
is the resistance of the resistor in series with the
LED (Ω).
V
SUPPLY
is the supply voltage used to drive the LED (V).
V
LED
is the forward voltage of the LED (V).
VOLis the output low voltage of the MAX6964 when
sinking I
LED
(V).
I
LED
is the desired operating current of the LED (A).
For example, to operate a 2.2V red LED at 14mA from a
5V supply, R
The MAX6965 can be used to drive loads drawing more
than 50mA, like relays and high-current white LEDs, by
paralleling outputs. Use at least one output per 50mA of
load current; for example, a 6V 330mW relay draws 55mA
and needs two paralleled outputs to drive it. Ensure that
the paralleled outputs chosen are controlled by the same
blink phase register, i.e., select outputs from the O0
through O7 range. This way, the paralleled outputs are
turned on and off together. Do not use output O8 as part of
a load-sharing design. O8 cannot be switched at the same
time as any of the other outputs because it is controlled by
a different register.
The MAX6965 must be protected from the negative
voltage transient generated when switching off inductive loads, such as relays, by connecting a reversebiased diode across the inductive load (Figure 19). The
peak current through the diode is the inductive load’s
operating current.
Power-Supply Considerations
The MAX6965 operates with a power-supply voltage of
2V to 3.6V. Bypass the power supply to GND with at
least 0.047µF as close to the device as possible.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
C
L
- A -
0.10
D2
D
D/2
E/2
E
- B -
C
L
C
0.08
C
A
A2
A1
L
(NE - 1) X e
C
L
e
D2/2
e
b
0.10 M C A B
k
(ND - 1) X e
C
L
e
E2/2
E2
L
L
12x16L QFN THIN.EPS
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
21-0136
REV.DOCUMENT CONTROL NO.APPROVAL
1
C
2
MAX6965
9-Output LED Driver with Intensity Control
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
EXPOSED PAD VARIATIONS
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0136
REV.
2
C
2
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