Rainbow Electronics MAX6902 User Manual

General Description

The MAX6902 SPI™-compatible real-time clock con­tains a real-time clock/calendar and 31 x 8 bits of static
random-access memory (SRAM). The real-time
clock/calendar provides seconds, minutes, hours, day,
date, month, year, and century information. A time/date
programmable polled ALARM is included in the
MAX6902. The end-of-the-month date is automatically
adjusted for months with fewer than 31 days, including
corrections for leap year up to the year 2100. The clock
operates in either the 24hr or 12hr format with an
AM/PM indicator. The MAX6902 operates with a supply
voltage of +2V to +5.5V, is available in the ultra-small
8-pin TDFN package, and works over the -40°C to
+85°C industrial temperature range.

Applications

Point-of-Sale Equipment

Intelligent Instruments

Fax Machines

Battery-Powered Products

Portable Instruments

Features

♦ Real-Time Clock Counts Seconds, Minutes, Hours,

Day of Week, Date of Month, Month, Year, and Century

♦ Leap-Year Compensation Valid up to Year 2100
♦ +2V to +5.5V Wide Operating Voltage Range
♦ SPI Interface: 4MHz at 5V; 1MHz at 2V
♦ 31 x 8-Bit SRAM for Scratchpad Data Storage
♦ Uses Standard 32.768kHz, 12.5pF Watch Crystal
♦ Low Timekeeping Current (400nA at 2V)
♦ Single-Byte or Multiple-Byte (Burst Mode) Data

Transfer for Read or Write of Clock Registers or
SRAM

♦ Ultra-Small 8-Pin 3mm x 3mm x 0.8mm TDFN

Package

♦ Programmable Time/Date Polled ALARM Function
♦ No External Crystal Bias Resistors or Capacitors

Required

MAX6902

SPI-Compatible RTC in a TDFN

________________________________________________________________ Maxim Integrated Products 1

Pin Configuration

Ordering Information

Typical Operating Circuit

19-2134; Rev 1; 7/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

I2C is a trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed
Associated Companies, conveys a license under the Philips I

2

C Patent rights to use these components in an I2C system provided that

the system conforms to the I

2

C Standard Specification as defined by Philips.

SPI is a trademark of Motorola, Inc.

Related Real-Time Clock Products

TEMP

PART

MAX6902ETA-T -40°C to +85°C 8 TDFN AGT

RANGE

PIN­PACKAGE

TOP

MARK

PART

MAX6900 I2C™ compatible 31 ✕ 8 ——6 TDFN

MAX6901 3 Wire 31 ✕ 8 Polled 32kHz 8 TDFN

MAX6902 SPI compatible 31 ✕ 8 Polled — 8 TDFN

+3.3V

µc

SERIAL

INTERFACE

+3.3V

0.1µF

6

V

CC

8

GND
4

X1

7

X2

MAX6902

1

SCLK

5

CS

2

DOUT

3

DIN

SRAM

32.768kHz
CRYSTAL

ALARM

FUNCTION

TOP VIEW

OUTPUT

FREQUENCY

1

SCLK

2

3

DIN

4

PACKAGE

87X1

MAX6902

TDFN

X2DOUT

V

6

CC

5

CSGND

PIN-

MAX6902

SPI-Compatible RTC in a TDFN

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC= +2.0V to +5.5V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VCCto GND..............................................................-0.3V to +6V

All Other Pins to GND ................................-0.3V to (VCC+ 0.3V)

Current into Any Pin..........................................................±20mA

Rate of Rise, VCC............................................................100V/µs

Continuous Power Dissipation (T

A

= +70°C)

8-Pin TDFN (derate 24.4mW/°C above +70°C) ..........1951.0mW

Junction Temperature .....................................................+150°C

Storage Temperature Range…………………… -65°C to +150°C

ESD Protection (all pins, Human Body Model) ..................2000V

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating Voltage
Range

Active Supply
Current (Note 2)

Timekeeping Supply
Current (Note 3)

SPI DIGITAL INPUTS (SCLK, DIN, CS)

Input High Voltage V

Input Low Voltage V

Input Leakage

Input Capacitance 10 pF

SPI DIGITAL OUTPUTS (DOUT)

Output Capacitance 15 pF

Output Low Voltage V

Output High Voltage V

V

CC

I

I

I

CC

TK

IH

IL

IL

OL

OH

VCC = +2V 0.3

VCC = +5V 1.1

VCC = +2V 0.4 0.8

VCC = +5V 1.3 2.2

VCC = +2V 1.4

VCC = +5V 2.2

VCC = +2V 0.6

VCC = +5V 0.8

VIN = 0 to V

VCC = +2.0V, I

VCC = +5.0V, I

VCC = +2.0V, I

VCC = +5.0V, I

CC

= 1.5mA 0.4

SINK

= 4mA 0.4

SINK

= -0.4mA 1.8

SOURCE

= -1mA 4.5

SOURCE

2 5.5 V

-10 10 nA

mA

µA

V

V

V

V

MAX6902

SPI-Compatible RTC in a TDFN

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(VCC= +2.0V to +5.5V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Figure 5,
Notes 1, 4)

Note 1: All parameters are 100% tested at TA= +25°C. Limits over temperature are guaranteed by design and characterization and

not production tested.

Note 2: I

CC

is specified with DOUT open, CS = DIN = GND, SCLK = 4MHz at VCC= +5V; SCLK = 1MHz at VCC= +2.0V.

Note 3: Timekeeping current is specified with CS = V

CC

, SCLK = DIN = GND, DOUT = 100kΩ to GND.

Note 4: All values referred to V

IH

min and VILmax levels.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OSCILLATOR

X1 to Ground
Capacitance

X2 to Ground
Capacitance

SPI SERIAL TIMING

Maximum Input Rise
Time

Maximum Input Fall
Time

Output Rise Time t

Output Fall Time t

SCLK Period t

SCLK High Time t

SCLK Low Time t

SCLK Fall to DOUT
Valid

DIN to SCLK Setup
Time

DIN to SCLK Hold
Time

SCLK Rise to CS
Rise Hold Time

CS High Pulse Width t

CS High to DOUT

High Impedance

CS to SCLK Setup
Time

t

rIN

t

fIN

rOUT

fOUT

CP

CH

CL

t

DO

t

DS

t

DH

t

CSH

CSW

t

CSZ

t

CSS

DIN, SCLK, CS 2 µs

DIN, SCLK, CS 2 µs

DOUT, C

DOUT, C

VCC = +2V 1000

VCC = +5V 238

C

LOAD

= 100pF 10 ns

LOAD

= 100pF 10 ns

LOAD

100 ns

100 ns

= 100pF 100 ns

100 ns

2ns

2ns

200 ns

100 ns

25 pF

25 pF

ns

100 ns

MAX6902

Detailed Description

The MAX6902 is a real-time clock/calendar with an SPI­compatible interface and 31 x 8 bits of SRAM. It pro­vides seconds, minutes, hours, day of the week, date of
the month, month, and year information, held in seven 8­bit timekeeping registers (Functional Diagram). An on­chip 32.768kHz oscillator circuit requires only a single
external crystal to operate. Table 1 specifies the para­meters for the external crystal, and Figure 1 shows a
functional schematic of the oscillator circuit. The
MAX6902’s register addresses and definitions are
described in Figure 2 and in Table 2. Time and calendar
data are stored in the registers in binary-coded decimal
(BCD) format. A polled alarm function is included for
scheduled timing of user-defined times or intervals.

Table 1. Acceptable Quartz Crystal
Parameters

SPI-Compatible RTC in a TDFN

4 _______________________________________________________________________________________

Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

Pin Description

Figure 1. Crystal Oscillator Circuit Schematic

10.0

TIMEKEEPING CURRENT

vs. SUPPLY VOLTAGE

MAX6902 toc01

PIN NAME FUNCTION

1 SCLK

2 DOUT SPI Data Output

3 DIN SPI Data Input

4 GND Ground

5 CS

6V

7 X2 External 32.768kHz Crystal

8 X1 External 32.768kHz Crystal

Serial Clock Input. SPI clock for DIN and
DOUT data transfers.

Chip Select Input. Active low for valid data
transfers.

Power-Supply Pin. Bypass VCC to GND

CC

with a 0.1µF capacitor.

1.0

SUPPLY CURRENT (µA)

0.1

2.0 3.5 4.02.5 3.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)

PARAMETER SYMBOL MIN TYP MAX UNITS

Frequency f 32.768 kHz

Equivalent
Series
Resistance
(ESR)

Parallel Load
Capacitance

Q Factor Q 40,000 60,000

R

S

C

L

40 60 kΩ

11.2 12.5 13.7 pF

MAX6902

25pF

X1 X2

EXTERNAL

CRYSTAL

25pF

MAX6902

SPI-Compatible RTC in a TDFN

_______________________________________________________________________________________ 5

Figure 2. Register Address Definition (Sheet 1 of 3)

REGISTER ADDRESS REGISTER DEFINITION

FUNCTION A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 D6 D5 D4 D3 D2 D1 D0

CLOCK

SECONDS RD 0000001 00-59

/W *POR STATE 0 000 0000

MINUTES RD 0000011 00-59

/W *POR STATE 0 0 0 0 0 0 0 0

HOURS RD 0000101 00-23 12/24

/W 01-12 1/0

*POR STATE 0 0 00 0 0 0 0

01-28/29

DATE RD 0000111

/W *POR STATE 0 0 000001

MONTH RD 0001001 01-12 0 0 0 10M 1 MONTH

/W *POR STATE 0 0 0 00001

01-30

0-31

0 10 SEC 1 SEC

ALM
OUT

0 0 10 DATE 1 DATE

10 MIN 1 MIN

10

HR

A/P

0/1

10

HR

0

1 HR

DAY RD 0001011 01-07 0 0 0 0 0 WEEK DAY

/W *POR STATE 0 0 0 0 0 001

YEAR RD 0001101 00-99 10 YEAR 1 YEAR

/W *POR STATE 0 1 1 1 0000

CONTROL RD 0001111 WP 0 0 0 0 0 0 0

/W *POR STATE 0 0 0 0 0 0 0 0

CENTURY RD 0010011 00-99 1000 YEAR 100 YEAR

/W *POR STATE 0 0 0 1 1001

Note: *POR STATE d efi nes p ow er - on r eset state of r eg i ster contents.

MAX6902

SPI-Compatible RTC in a TDFN

6 _______________________________________________________________________________________

Figure 2. Register Address Definition (Sheet 2 of 3)

REGISTER ADDRESS REGISTER DEFINITION

FUNCTION A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 D6 D5 D4 D3 D2 D1 D0

ALARM

CONFIG

RESERVED RD 0010111 0 0 0 0 0 1 1 1

Do not write

to this location.

ALARM

THRESHOLDS

SECONDS RD 0011001 00-59

MINUTES RD 0011011 00-59 0 10 MIN 1 MIN

HOURS RD 0011101 00-23 12/24

DATE RD 0011111

RD 0010101

/W *POR STATE 0 0 0 0 0 0 0 0

/W *POR STATE 00000111

/W *POR STATE 0 11 1 11 1 1

/W *POR STATE 0 111111 1

/W 01-12 1/0

*POR STATE 1 0 111111

01-28/29

01-30
01-31

/W *POR STATE 0 0 111111

0

0 10 SEC 1 SEC

0 0 10 DATE 1 DATE

0

YEAR

10HR10

A/P

0/1

DAY

MONTH

HR

DATE

HOUR

1 HR

MINUTE

SECOND

MONTH RD 0100001 01-12 0 0 0 10M 1 MONTH

/W *POR STATE 0 0 0 11111

DAY RD 0100011 01-07 0 0 0 0 0 WEEK DAY

/W *POR STATE 0 0 0 0 0 11 1

YEAR RD 0100101 00-99 10 YEAR 1 YEAR

/W *POR STATE 1 1 1 1 1 1 1 1

CLOCK

BURST

RD 0111111

/W

MAX6902

SPI-Compatible RTC in a TDFN

_______________________________________________________________________________________ 7

Figure 2. Register Address Definition (Sheet 3 of 3)

Table 2. Register Address and Description

REGISTER ADDRESS REGISTER DEFINITION

FUNCTION A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 D6 D5 D4 D3 D2 D1 D0

RAM

RAM 0 RD 1 0 0 0 0 0 1 RAM DATA 0 xxxxxxxx

/W

••

••

••

RAM 30 RD 1 1 1 1 1 0 1 RAM DATA 30 xxxxxxxx

/W

RAM BURST RD 1111111

/W

Note: *POR STATE defines power-on reset state of register contents.

••

••

••

WRITE (HEX) READ (HEX) DESCRIPTION POR CONTENTS (HEX)

01 81 Seconds 00

03 83 Minutes 00

05 85 Hours 00

07 87 Date 01

09 89 Month 01

0B 8B Day 01

0D 8D Year 70

0F 8F Control 00

13 93 Century 19

15 95 Alarm Configuration 00

17 97 Reserved 07

19 99 Seconds Alarm Threshold 7F

1B 9B Minutes Alarm Threshold 7F

1D 9D Hours Alarm Threshold BF

1F 9F Date Alarm Threshold 3F

21 A1 Month Alarm Threshold 1F

23 A3 Day Alarm Threshold 07

25 A5 Year Alarm Threshold FF

3F BF Clock Burst Not applicable

MAX6902

SPI-Compatible RTC in a TDFN

8 _______________________________________________________________________________________

Table 2. Register Address and Description (continued)

WRITE (HEX) READ (HEX) DESCRIPTION POR CONTENTS (HEX)

41 C1 RAM 0 Indeterminate

43 C3 RAM 1 Indeterminate

45 C5 RAM 2 Indeterminate

47 C7 RAM 3 Indeterminate

49 C9 RAM 4 Indeterminate

4B CB RAM 5 Indeterminate

4D CD RAM 6 Indeterminate

4F CF RAM 7 Indeterminate

51 D1 RAM 8 Indeterminate

53 D3 RAM 9 Indeterminate

55 D5 RAM 10 Indeterminate

57 D7 RAM 11 Indeterminate

59 D9 RAM 12 Indeterminate

5B DB RAM 13 Indeterminate

5D DD RAM 14 Indeterminate

5F DF RAM 15 Indeterminate

61 E1 RAM 16 Indeterminate

63 E3 RAM 17 Indeterminate

65 E5 RAM 18 Indeterminate

67 E7 RAM 19 Indeterminate

69 E9 RAM 20 Indeterminate

6B EB RAM 21 Indeterminate

6D ED RAM 22 Indeterminate

6F EF RAM 23 Indeterminate

71 F1 RAM 24 Indeterminate

73 F3 RAM 25 Indeterminate

75 F5 RAM 26 Indeterminate

77 F7 RAM 27 Indeterminate

79 F9 RAM 28 Indeterminate

7B FB RAM 29 Indeterminate

7D FD RAM 30 Indeterminate

7F FF RAM Burst Not applicable

MAX6902

SPI-Compatible RTC in a TDFN

_______________________________________________________________________________________ 9

Command and Control

Address/Command Byte

Each data transfer into or out of the MAX6902 is initiated
by an Address/Command byte. The Address/Command
byte specifies which registers are to be accessed, and
if the access is a read or a write. Figure 2 shows the
Address/Command bytes and their associated regis­ters, and Table 2 lists the hex codes for all read and
write operations. The Address/Command bytes are
input MSB (bit 7) first. Bit 7 specifies a write (logic 0) or
read (logic 1). Bit 6 specifies register data (logic 0) or
RAM data (logic 1). Bits 5–1 specify the designated reg­ister to be written or read. The LSB (bit 0) must be logic

1. If the LSB is a zero, writes to the MAX6902 are dis­abled.

Clock Burst Mode

Sending the Clock Burst Address/Command (3Fh for
Write and BFh for Read), specifies burst-mode opera­tion. In this mode, multiple bytes are read or written
after a single Address/Command. The first seven
clock/calendar registers (Seconds, Minutes, Hours,
Date, Month, Day, and Year) and the Control register
are consecutively read or written, starting with the MSB
of the Seconds register. When writing to the clock reg­isters in burst mode, all seven clock/calendar registers
and the Control register must be written in order for the
data to be transferred. See Example: Setting the Clock
with a Burst Write.

RAM Burst Mode

Sending the RAM Burst Address/Command (F7h for
Write, FFh for Read) specifies burst-mode operation. In
this mode, the 31 RAM locations can be consecutively
read or written, starting at 41h for Writes, and C1h for
Reads. A Burst Read outputs all 31 bytes of RAM.
When writing to RAM in burst mode, it is not necessary
to write all 31 bytes for the data to transfer; each com­plete byte written is transferred to RAM. When reading
from RAM, data are output until all 31 bytes have been
read, or until CS is driven high.

Setting the Clock

Writing to the Timekeeping Registers

The time and date are set by writing to the timekeeping
registers (Seconds, Minutes, Hours, Date, Month, Day,
Year, and Century). During a write operation, an input
buffer accepts the new time data while the timekeeping
registers continue to increment normally, based on the
crystal counter. The buffer also keeps the timekeeping
registers from changing as the result of an incomplete
write operation, and collision-detection circuitry
ensures that a Time Write does not occur coincident

with a Seconds register increment. The updated time
data are loaded into the timekeeping registers after the
rising edge of CS, at the end of the SPI write operation.
An incomplete write operation aborts the update proce­dure, and the contents of the input buffer are discard­ed. The timekeeping registers reflect the new time
beginning with the first Seconds register increment
after the rising edge of CS.

Although both Single Writes and Burst Writes are possi­ble, the best way to write to the timekeeping registers is
with a Burst Write. With a Burst Write, the main time­keeping registers (Seconds, Minutes, Hours, Date,
Month, Day, Year) and the Control register are written
sequentially following the Address/Command byte.
They must be written as a group of eight registers, with
8 bits each, for proper execution of the Burst Write
function. All seven timekeeping registers are simultane­ously loaded into the clock counters by the rising edge
of CS, at the end of the SPI write operation. For a nor­mal burst data transfer, the worst-case error that can
occur between the actual time and the written time
update is 1s.

If single write operations are used to enter data into the
timekeeping registers, error checking is required. If not
writing to the Seconds register, begin by reading the
Seconds register and save it as initial-seconds. Then
write to the required timekeeping registers, and finally
read the Seconds register again (final-seconds). Check
to see that final-seconds is equal to initial-seconds. If
not, repeat the write process. If writing to the Seconds
register, update the Seconds register first, and then
read it back and store its value (initial-seconds).
Update the remaining timekeeping registers and then
read the Seconds register again (final-seconds). Check
to see that final-seconds is equal to initial-seconds. If
not, repeat the write process.

Note: After writing to any time or date register, no read
or write operations are allowed for 45µs.

AM/PM and 12Hr/24Hr Mode

Bit 7 of the Hours register selects 12hr or 24hr mode.
When high, 12hr mode is selected. In 12hr mode, bit 5 is
the AM/PM bit, logic high for PM. In 24hr mode, bit 5 is
the second 10hr bit, logic high for hours 20 through 23.

Write-Protect Bit

Bit 7 of the Control register is the Write-Protect bit.
When high, the Write-Protect bit prevents write opera­tions to all registers except itself. After initial settings
are written to the timekeeping registers, set the Write­Protect bit to logic 1 to prevent erroneous data from
entering the registers during power glitches or inter­rupted serial transfers. The lower 7 bits (bits 0–6) are

MAX6902

SPI-Compatible RTC in a TDFN

10 ______________________________________________________________________________________

unusable, and always read zero. Any data written to
bits 0–6 are ignored. Bit 7 must be set to zero before a
single write to the clock, before a write to RAM, or dur­ing a Burst Write to the clock.

Example: Setting the Clock

with a Burst Write

To set the clock to 10:11:31PM, Thursday July 4th,
2002 with a burst write operation, write 3Fh as the
Address/Command byte, followed by 8 bytes, 31h, 11h,
B0h, 04h, 07h, 05h, 02h, and 00h (Figure 2). 3Fh is the
Clock Burst Write Address/Command. The first byte,
31h, sets the Seconds register to 31. The second byte,
11h, sets the Minutes register to 11. The third byte,
B0h, sets the Hours register to 12hr mode, and 10PM.
The fourth byte, 04h, sets the Date register (day of the
month) to the 4th. The fifth byte, 07h, sets the Month
register to July. The sixth byte, 05h, sets the Day regis­ter (day of the week) to Thursday. The seventh byte,
02h, sets the Year register to 02. The eighth byte, 00h,
clears the Write-Protect bit of the Control register to
allow writing to the MAX6902. The Century register is
not accessed with a Burst Write and therefore must be
written to separately to set the century to 20. Note the
Century register corresponds to the thousand and hun­dred digits of the current year and defaults to 19.

Reading the Clock

Reading the Timekeeping Registers

The main timekeeping registers (Seconds, Minutes,
Hours, Date, Month, Day, Year) can be read with either
Single Reads or a Burst Read. In the MAX6902, a latch
buffers each clock counter’s data. Clock counter data
are latched by the SPI Read Command (on the falling
edge of SCLK, after the Address/Command byte has
been sent by the master to read a timekeeping regis­ter). Collision-detection circuitry ensures that this does
not happen coincident with a Seconds counter incre­ment to ensure accurate time data are being read. The
clock counters continue to count and keep accurate
time during the read operation.

The simplest way to read the timekeeping registers is to
use a Burst Read. In a Burst Read, the main timekeep­ing registers (Seconds, Minutes, Hours, Date, Month,
Day, Year), and the Control register are read sequen­tially, in the order listed with the Seconds register first.
They are read out as a group of eight registers, with 8
bits each. All timekeeping registers (except Century)
are latched upon the receipt of the Burst Read com­mand. The worst-case error between the “actual” time
and the “read” time is 1s for a normal data transfer.

The timekeeping registers may also be read using
Single Reads. If Single Reads are used, it is necessary
to do some error checking on the receiving end,
because it is possible that the clock counters could
change during the Read operations, and report inaccu­rate time data. The potential for error is when the
Seconds register increments before all the registers are
read. For example, suppose a carry of 13:59:59 to
14:00:00 occurs during single read operations. The net
data read could be 14:59:59, which is erroneous. To
prevent errors from occurring with single read opera­tions, read the Seconds register first (initial-seconds)
and store this value for future comparison. After the
remaining timekeeping registers have been read,
reread the Seconds register (final-seconds). Check that
the final-seconds value equals the initial-seconds
value. If not, repeat the entire Single Read process.
Using Single Reads at a 100kHz serial speed, it takes
under 2.5ms to read all seven of the timekeeping regis­ters, including two reads of the Seconds register.

Example: Reading the Clock

with a Burst Read

To read the time with a Burst Read, send BFh as the
Address/Command byte. Then clock out 8 bytes,
Seconds, Minutes, Hours, Date of the month, Month,
Day of the week, Year, and finally the Control byte. All
data are output MSB first. Decode the required informa­tion based on the register definitions listed in Figure 2.

Using the Alarm

A polled alarm function is available by reading the ALM
OUT bit. The ALM OUT bit is D7 of the Minutes timekeep­ing register. A logic 1 in ALM OUT indicates the Alarm
function is triggered. There are eight registers associated
with the alarm function—seven programmable Alarm
Threshold registers and one programmable Alarm
Configuration register. The Alarm Configuration register
determines which Alarm Threshold registers are com­pared to the timekeeping registers, and the ALM OUT bit
sets if the compared registers are equal. Figure 2 shows
the function of each bit of the Alarm Configuration regis­ter. Placing a logic 1 in any given bit of the Alarm
Configuration register enables the respective alarm func­tion. For example, if the Alarm Configuration register is set
to 0000 0011, ALM OUT is set when both the minutes and
seconds indicated in the Alarm Threshold registers match
the respective timekeeping registers. Once set, ALM OUT
stays high until it is cleared by reading or writing to the
Alarm Configuration register, or by reading or writing to
any of the Alarm Threshold registers. The Alarm
Configuration register is written with address 15h, and
read with address 95h.

MAX6902

SPI-Compatible RTC in a TDFN

______________________________________________________________________________________ 11

Using the On-Board RAM

The static RAM is 31 x 8 bits addressed consecutively
in the RAM Address/Command space. Table 2 details
the specific hex Address/Commands for Reads and
Writes to each of the 31 locations of RAM. The contents
of the RAM are static and remain valid for VCCdown to
2V. All RAM data are lost if power is cycled. The Write­Protect Bit (bit 7 of the Control register), when high, dis­allows any writes to RAM.

SPI-Compatible Serial

Interface

Interface the MAX6902 with a microcontroller using a
serial, 4-wire, SPI interface. SPI is a synchronous bus
for address and data transfer, and is used with
Motorola or other microcontrollers that have an SPI
port. Four connections are required for the interface:
DOUT (Serial Data Out); DIN (Serial Data In); SCLK
(Serial Clock); and CS (Chip Select). In an SPI applica­tion, the MAX6902 acts as a slave device and the
microcontroller acts as the master. CS is asserted low
by the microcontroller to initiate a transfer, and
deasserted high to terminate a transfer. DIN transfers
input data from the microcontroller to the MAX6902.
DOUT transfers output data from the MAX6902 to the
microcontroller. A shift clock, SCLK, is used to synchro­nize data movement between the microcontroller and
the MAX6902. SCLK, which is generated by the micro­controller, is active only during address and data trans­fer to any device on the SPI bus. The inactive clock
polarity is usually programmable on the microcontroller
side of the SPI interface. In the MAX6902, input data
are latched on the positive edge, and output data are

shifted out on the negative edge. There is one clock
cycle for each bit transferred. Address and data bits
are transferred in groups of eight.

The SPI protocol allows for one of four combinations of
serial clock phase and polarity from the microcontroller,
through a 2-bit selection in its SPI Control register. The
clock polarity is specified by the CPOL Control bit,
which selects active-high or active-low clock, and has
no significant effect on the transfer format. The Clock
Phase Control bit, CPHA, selects one of two different
transfer formats. The clock phase and polarity must be
identical for the master and the slave. For the
MAX6902, set the control bits to CPHA = 1 and CPOL =

1. This configures the system for data to be launched
on the negative edge of SCLK and sampled on the
positive edge. With CPHA equal to 1, CS can remain
low between successive data byte transfers, allowing
burst-mode data transfers to occur.

Address and data bytes are shifted MSB first into DIN
of the MAX6902, and out of DOUT. Data are shifted out
at the negative edge of SCLK, and shifted in or sam­pled at the positive edge of SCLK. Any transfer
requires an Address/Command byte followed by one or
more bytes of data. Data are transferred out of DOUT
for a read operation, and into DIN for a write operation.
DOUT transmits data only after an Address/Command
byte specifies a read operation; otherwise, it is high
impedance.

Data Transfer Write timing is shown in Figure 3. Data
Transfer Read timing is shown in Figure 4. Detailed
Read and Write Timing is shown in Figure 5.

Figure 3a. Single Write

* R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0.

CS

SCLK

DIN

0 R* A5 A4 A3 A2 A1 1 D7 D6 D5 D4 D3 D2 D1 D0

ADDRESS/COMMAND BYTE DATA BYTE

DOUT

HIGH IMPEDANCE; NO ACTIVITY ON DOUT LINE DURING WRITES.

MAX6902

SPI-Compatible RTC in a TDFN

12 ______________________________________________________________________________________

Figure 3b. Burst Write

Figure 4a. Single Read

Figure 4b. Burst Read

CS

SCLK

DIN

1 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2

ADDRESS/COMMAND BYTE** DATA BYTE 1 DATA BYTE N

DOUT

* R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0.
** ONLY ONE ADDRESS/COMMAND BYTE IS REQUIRED PER BURST TRANSACTION.

CS

SCLK

DIN

DOUT

* R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0.

HIGH IMPEDANCE; NO ACTIVITY ON DOUT LINE DURING WRITES.

1R*

A5 A4 A3 A2 A1

ADDRESS/COMMAND BYTE

HIGH IMPEDANCE

D1 D00R*

1

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE

CS

SCLK

DIN

1R*

DOUT

* R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0.
** ONLY ONE ADDRESS/COMMAND BYTE IS REQUIRED PER BURST TRANSACTION.

111111

ADDRESS/COMMAND BYTE**

HIGH IMPEDANCE

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE 1

D7 D6 D5 D4 D3 D2

DATA BYTE N

D1 D0

MAX6902

SPI-Compatible RTC in a TDFN

______________________________________________________________________________________ 13

Chip Select

CS serves two functions. First, CS turns on the control
logic that allows access to the Shift register for
Address/Command and data transfer. Second, CS pro­vides a method of terminating either single-byte or mul­tiple-byte data transfers. All data transfers are initiated
by driving CS low. If CS is high, then DOUT is high
impedance.

Serial Clock

A clock cycle on SCLK is a rising edge followed by a
falling edge. For data input, data must be valid at DIN
before the rising edge of the clock. For data outputs, bits
are valid on DOUT after the falling edge of the clock.

Data Input (Single-Byte Write)

Following the eight SCLK cycles that input a Single-Byte
Write Address/Command, data bits are input on the ris­ing edges of the next eight SCLK cycles. Additional
SCLK cycles are ignored. Input data MSB first.

Data Input (Burst Write)

Following the eight SCLK cycles that input a Burst-Write
Address/Command, data bits are input on the rising
edges of the following SCLK cycles. The number of
clock cycles depends on whether the timekeeping reg­isters or RAM are being written. A Clock Burst Write
requires 1 Address/Command byte, 7 timekeeping data
bytes, and 1 Control register byte. A Burst Write to RAM
may be terminated after any complete data byte by dri­ving CS high. Input data MSB first (Figure 3).

Data Output (Single-Byte Read

and Burst Read)

A read from the MAX6902 is initiated by an
Address/Command Write from the microcontroller (mas­ter) to the MAX6902 (slave). The Address/Command
Write portion of the data transfer is clocked into the
MAX6902 on rising clock edges. Following the eighth
falling clock edge of SCLK, after tDO(Figure 4) data
begins to be output on DOUT of the MAX6902. Data
bytes are output MSB first. Additional SCLK cycles
transmit additional data bits, as long as CS remains low.
This permits continuous burst-mode read capability.

Applications Information

Crystal Selection

The MAX6902 is designed to use a standard

32.768kHz watch crystal. Table 1 details the recom­mended crystal requirements. Some suggested crys­tals are listed in Table 3. In addition to the specified
SMT devices, some of the listed manufacturers also
offer other package options.

Frequency Stability and Temperature

Timekeeping accuracy of the MAX6902 is dependent
on the frequency stability, of the external crystal. To
determine frequency stability, use the parabolic curve
in Figure 6 and the following equations:

where:
∆f = change in frequency from +25°C (Hz)

f = nominal crystal frequency (Hz)

Figure 5. SPI Bus Timing Diagrams

CS

t

t

CSS

SCLK

t

DS

DIN

DOUT

D7 D6 D5 D0

t

CH

t

CL

DH

t

CSH

t

CP

t

CSZ

D7 D0

t

DO

t

CSW

∆ffk= (T - T)

2

0

MAX6902

SPI-Compatible RTC in a TDFN

14 ______________________________________________________________________________________

k = parabolic curvature constant (-0.035 ±0.005ppm/°C

2

for 32.768kHz watch crystals)

T0= turnover temperature (+25°C ±5°C for 32.768kHz
watch crystals)

T = temperature of interest (°C)

For example: What is the worst-case change in oscilla­tor frequency from +25°C ambient to +45°C ambient?

What is the worst-case timekeeping error per second?
Error due to temperature drift:

Error due to 25°C initial crystal tolerance of ±20ppm:

Total timekeeping error per second:

After 1 month that translates to:

Total worst-case timekeeping error at the end of 1
month at 45°C is about 120s or 2min (assumes negligi­ble parasitic layout capacitance).

Oscillator Start Time

The MAX6902 oscillator typically takes 5s to 10s to
begin oscillating. To ensure the oscillator is operating
correctly, the software should validate proper time­keeping. This is accomplished by reading the Seconds
register. Any reading of 1s or more from the POR value
of zero seconds is a validation of proper startup.

Table 3. 32.768kHz Surface-Mount Watch Crystals

Figure 6. Typical Temperature Curve for 32.768kHz Watch
Crystal

MANUFACTURER

Abracon Corporation ABS25-32.768-12.5-B-2-T -40°C to +85°C 12.5 ±20
Caliber Electronics AWS2A-32.768KHz, AWS2B-32.768KHz -20°C to +70°C 12.5 ±20
ECS INC International ECS-.327-12.5-17 -10°C to +60°C 12.5 ±20
Fox Electronics FSM327 -40°C to +85°C 12.5 ±20
M-tron SX2010/ SX2020 -20°C to +75°C 12.5 ±20
Raltron RSE-32.768-12.5-C-T -10°C to +60°C 12.5 ±20
SaRonix 32S12A -40°C to +85°C 12.5 ±20

∆fHz

=× ××

32 768 1 10

drift

.()

×

20 0 8192

(.

()-0.04ppm/ C

oo

C - 45 C) -

2

MANUFACTURER

o

=

PART NO.

2-6

Hz

TEMP.

RANGE

-40 -20 0 20 40 60 80 100

0

-50

-100

f (ppm)

-150

-200

CL (pF)

TEMPERATURE (°C)

+25°C

FREQUENCY
TOLERANCE

(ppm)

∆∆

tff s

=+

1 32 768 1 1

//,/

()

drift drift

∆

tHzHzs

drift

∆∆

tff s

initial initial

∆

fHz Hz

initial

∆

ts

initial

∆∆∆

ttt

total drift initial

∆

tssssss

total

[]

[]

{}

1 32 768 0 32 768 1 1

/, /, /

=

()

[]

[]

{}

=

0 000025

./

=+

1 32 768 1 1

//,/

()

[]

[]

{}

=×××

32 768 1 10 0 65536

,().

1 32 768 0 6 32 768 1 1

/, /, /

=

()

[]

[]

{}

=

0 000020

./

=+
=+=

0 000025 0 000020 0 000045

./././

- .8192 - s

ss

-20ppm

()

- . 5536 -

ss

-s

-s

∆t day

-6

=

-250
TYPICAL TEMPERATURE CHARACTERISTICS

(k = -0.035 ppm/°C

=

()

=120.528s



31 24 60 60






hr

day hr

min










2

; TO = +25°C)













min

s



(0.000045s/s)




Timekeeping Current

When DOUT is high impedance (CS = high or during a
DIN transfer segment), there is a potential for increased
timekeeping current (up to 100x) if DOUT is allowed to
float. If minimum timekeeping current is desired, then
ensure DOUT is not allowed to float. The microcon­troller port pin attached to DOUT could be configured
as an input with a weak pullup. An alternate solution is
to use a 100kΩ, or less, pulldown or pullup resistor (for
microcontroller port pins with ≤1µA input leakage).

Timekeeping Current—Backup Battery

Systems

Often a real-time clock (RTC) is operated in a system
with a backup battery. A microprocessor supervisory
circuit with backup battery switchover, or other switch­ing arrangement, is used to switch power from VCCto
V

BATT

when VCCfalls below a set threshold. Most of
these systems leave only the RTC and some SRAM to
run from V

BATT

. The microcontroller that communicates
with the RTC is powered only from VCC. When the
microcontroller is put into reset, its ports typically
become high impedance. This essentially floats DIN,
CS, DOUT, and SCLK. There is a potential for
increased timekeeping current (up to x100) as VCCfalls
through the linear region of the gates for DIN, CS,
DOUT, and SCLK. Duration of this effect depends on
the discharge rate of VCC. To minimize current draw
from V

BATT

in such systems, ensure that VCCfalls

rapidly at power down. One option is a VCCdischarge
resistor of 100kΩ or less from VCCto ground. This also
ensures sufficient impedance, back through the micro­controller’s ESD protection, on VCCwhen it is gone to
keep DIN, CS, DOUT, and SCLK from floating, which
can cause excessive timekeeping current. Alternately,
a 100kΩ pulldown (for microcontroller port pins with
≤1µA input leakage) on each pin (DIN, CS, DOUT, and
SCLK) ensures that timekeeping current specifications
are met during the power switchover.

Power-On Reset

The MAX6902 contains an integral POR circuit that
ensures all registers are reset to a known state on
power-up. Once VCCrises above 1.6V (typ), the POR
circuit releases the registers for normal operation. When
VCCdrops to less than 1.6V (typ), the MAX6902 resets
all register contents to the POR defaults (Figure 2).

RESERVED Register

Address/Command 17h is reserved for factory testing
ONLY. Do not write to this register. If inadvertent writes
are done to this register, cycle power to the MAX6902.

Power-Supply Considerations

For most applications, a 0.1µF capacitor from VCCto
GND provides adequate bypassing for the MAX6902. A
series resistor can be added to the supply line for oper­ation in extremely harsh or noisy environments.

PC Board Layout Considerations

The MAX6902 uses a very-low-current oscillator to mini­mize supply current. This causes the oscillator pins, X1
and X2, to be relatively high impedance. Exercise care
to prevent unwanted noise pickup.

Connect the 32.768kHz crystal directly across X1 and X2
of the MAX6902. To eliminate unwanted noise pickup,
design the PC board using these guidelines (Figure 7):

1) Place the crystal as close to X1 and X2 as possible
and keep the trace lengths short.

2) Place a guard ring around the crystal, X1 and X2
traces (where applicable), and connect the guard
ring to GND; keep all signal traces away from
beneath the crystal, X1, and X2.

3) Finally, an additional local ground plane can be
added under the crystal on an adjacent PC board
layer. The plane should be isolated from the regular
PC board ground plane, and tied to ground at the
MAX6902 ground pin.

4) Restrict the plane to be no larger than the perimeter of
the guard ring. Do not allow this ground plane to con­tribute significant capacitance between X1 and X2.

Chip Information

TRANSISTOR COUNT: 26,418

PROCESS: CMOS

MAX6902

SPI-Compatible RTC in a TDFN

______________________________________________________________________________________ 15

MAX6902

SPI-Compatible RTC in a TDFN

16 ______________________________________________________________________________________

Figure 7. MAX6902 Crystal PC Board Layout

GROUND PLANE

VIA CONNECTION

*

0.1µF

SM CAP

GUARD RING

PLANE

V

CC

VIA CONNECTION

*

GROUND PLANE
VIA CONNECTION

*

**

GROUND PLANE

VIA CONNECTION

**

SM WATCH CRYSTAL

**

*

*

LAYER 1 TRACE

*

*

*

MAX6902

*
*

**

LAYER 2 LOCAL GROUND PLANE

**

CONNECT ONLY TO PIN 4
GROUND PLANE VIA

*

*

MAX6902

SPI-Compatible RTC in a TDFN

______________________________________________________________________________________ 17

Functional Diagram

VCC

GND

SCLK

DIN

DOUT

CS

X1
X2

OSCILLATOR

32.768kHz

INPUT SHIFT

REGISTERS

DIVIDER

CONTROL

LOGIC

ADDRESS
REGISTER

31x 8

RAM

1Hz

SECONDS

MINUTES

HOURS

DATE

MONTH

DAY

YEAR

CONTROL

CENTURY

ALARM
CONFIG

RESERVED

ALARM

THRESHOLDS

CLOCK
BURST

RAM

BURST

ALARM OUT

ALARM

CONTROL

LOGIC

MAX6902

SPI-Compatible RTC in a TDFN

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages

.)

PIN 1
INDEX
AREA

D

E

A

A2

b

E2

DETAIL A

e

D2

C0.35

L

PIN 1 ID

1N1

[(N/2)-1] x e

REF.

6, 8, &10L, QFN THIN.EPS

A

NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY

COMMON DIMENSIONS

MIN. MAX.

SYMBOL

0.70 0.80

A

2.90 3.10

D

E

2.90 3.10

0.00 0.05

A1

L

0.20 0.40

k

0.25 MIN.

A2 0.20 REF.

PACKAGE VARIATIONS

PKG. CODE

T633-1 1.50–0.10D22.30–0.10

N

6

1.50–0.10

E2

2.30–0.10T833-1 8

A1

L

0.95 BSCeMO229 / WEEA

0.65 BSC

JEDEC SPEC

MO229 / WEEC

C

L

e

0.40–0.05b1.90 REF

0.25–0.05 2.00 REFMO229 / WEED-30.50 BSC1.50–0.10 2.30–0.1010T1033-1

k

C
L

e

DALLAS

SEMICONDUCTOR

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE, 6, 8 & 10L,
TDFN, EXPOSED PAD, 3x3x0.80 mm

APPROVAL

[(N/2)-1] x e

1.95 REF0.30–0.05

DOCUMENT CONTROL NO. REV.

21-0137 D

L

1

2

DALLAS

SEMICONDUCTOR

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE, 6, 8 & 10L,

TDFN, EXPOSED PAD, 3x3x0.80 mm

DOCUMENT CONTROL NO.APPROVAL

21-0137

REV.

2

2

D