Rainbow Electronics MAX66120 User Manual

General Description

The MAX66120 combines 1024 bits of user EEPROM, a 64-bit unique identifier (UID), and a 13.56MHz ISO 15693 RF interface in a plastic key fob. The memory is organized as 16 blocks of 8 bytes plus two more blocks for data and control registers. Each block has a userreadable write-cycle counter. Four adjacent user EEPROM blocks form a memory page (pages 0 to 3). Memory protection features are write protection and EPROM emulation, which the user can set for each individual memory page. The MAX66120 supports all ISO 15693-defined data rates, modulation indices, subcarrier modes, the selected state, application family identifier (AFI), data storage format identifier (DSFID), and the Option_flag bit for read operations. Memory write access is accomplished through standard ISO 15693 memory and control function commands.

Applications

Driver Identification (Fleet Application)

Access Control

Asset Tracking

Features

♦ Fully Compliant with ISO 15693 and ISO 18000-3

Mode 1 Standard

♦ 13.56MHz ±7kHz Carrier Frequency

♦ 1024-Bit User EEPROM with Block Lock Feature,

Write-Cycle Counter, and Optional EPROMEmulation Mode

♦ 64-Bit UID

♦ Read and Write (64-Bit Block)

♦ Supports AFI and DSFID Function

♦ 10ms Programming Time

♦ To Fob: 10% or 100% ASK Modulation Using 1/4

(26kbps) or 1/256 (1.6kbps) Pulse-Position Coding

♦ From Fob: Load Modulation Using Manchester

Coding with 423kHz and 484kHz Subcarrier in Low (6.6kbps) or High (26kbps) Data-Rate Mode

♦ 200,000 Write/Erase Cycles (Minimum)

♦ 40-Year Data Retention (Minimum)

♦ Compatible with Existing 1Kb ISO 15693 Products

on the Market

♦ Supports the Option_Flag for Read Operations

♦ Powered Entirely Through the RF Field

♦ Operating Temperature: -25°C to +50°C

MAX66120

ISO 15693-Compliant 1Kb Memory Fob

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Maxim Integrated Products

Ordering Information

Typical Operating Circuit

19-5623; Rev 0; 11/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Denotes a lead(Pb)-free/RoHS-compliant package.

PART TEMP RANGE PIN-PACKAGE

MAX66120K-000AA+ -25°C to +50°C Key Fob

Key Fob Mechanical Drawing appears at end of data sheet.

EVALUATION KIT

AVAILABLE

13.56MHz READER

TX_OUT

TRANSMITTER

RX_IN

MAGNETIC COUPLING

ANTENNA

MAX66120

IC LOAD

SWITCHED

LOAD

MAX66120

ISO 15693-Compliant 1Kb Memory Fob

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(TA= -25°C to +50°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 1: System requirement. Note 2: Guaranteed by simulation; not production tested. Note 3: Write-cycle endurance is degraded as T

increases. Not 100% production tested; guaranteed by reliability monitor sampling.

Note 4: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data

sheet limit at operating temperature range is established by reliabiliity testing.

Note 5: Production tested at 13.56MHz only. Note 6: Measured from the time at which the incident field is present with strength greater than or equal to H

(MIN)

to the time at which the MAX66120’s internal power-on reset signal is deasserted and the device is ready to receive a command frame. Not characterized or production tested; guaranteed by simulation only.

Maximum Incident Magnetic Field Strength ..........141.5dBµA/m

Operating Temperature Range ...........................-25°C to +50°C

Relative Humidity ..............................................(Water Resistant)

Storage Temperature Range ...............................-25°C to +50°C

Detailed Description

The MAX66120 combines 1024 bits of user EEPROM, 128 bits of user and control registers, a 64-bit unique identifier (UID), and a 13.56MHz ISO 15693 RF interface in a single key fob. The memory is organized as 18 blocks of 8 bytes each. Each block has a user-readable write-cycle counter. Four adjacent user EEPROM blocks form a memory page (pages 0 to 3). Memory protection features include write protection and EPROM emulation, which the user can set for each individual memory page. The memory of the MAX66120 is accessed through the standard ISO 15693 memory and control function commands. The data rate can be as high as 26.69kbps. The MAX66120 supports AFI and DSFID. Applications of the MAX66120 include driver identification (fleet application), access control, and asset tracking.

Overview

Figure 1 shows the relationships between the major control and memory sections of the MAX66120. The device has three main data components: 1) 64-bit UID,

2) four 256-bit pages of user EEPROM, and 3) two 8byte blocks of user and control registers. Figure 2 shows the applicable ISO 15693 commands and their purpose. The network function commands allow the master to identify all slaves in its range and to change their state, e.g., to select one for further communication. The protocol required for these network function commands is described in the

Network Function

Commands

section. The memory and control functions access the memory of the MAX66120 for reading and writing. The protocol for these memory and control function commands is described in the

Memory and

Control Function Commands

section. All data is read and written least significant bit (LSb) first, starting with the least significant byte (LSB).

EEPROM

Programm ing Time t

Endurance N

Data Retention t

RF INTERFACE

Carrier Frequency f

Activation Field Strength H

Write Fie ld Strength HWR At 25°C (Note 2) 122.4 dBμA/m

Maximum Field Strength H

Power-Up Time t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PROG

CYCLE

RET

MIN

MAX

POR

(Note 2) 9 10 ms

At +25°C (Note 3) 200,000 Cycles

(Note 4) 40 Years

(Notes 1, 5) 13.553 13.560 13.567 MHz

At 25°C (Note 2) 122.0 dBμA/m

At 25°C (Note 2) 137.5 dBμA/m

(Notes 2, 6) 1.0 m s

MAX66120

ISO 15693-Compliant 1Kb Memory Fob

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Figure 1. Block Diagram

Parasite Power

As a wireless device, the MAX66120 is not connected to any power source. It gets the energy for operation from the surrounding RF field, which must have a minimum strength as specified in the

Electrical

Characteristics

table.

Unique Identification Number (UID)

Each MAX66120 contains a factory-programmed and locked identification number that is 64 bits long (Figure 3). The lower 36 bits are the serial number of the chip. The next 8 bits store the device feature code, which is 02h. Bits 45 to 48 are 0h. The code in

Figure 2. ISO 15693 Commands Overview

MSb LSb

64 57 56 49 48 45 44 37 36 1

E0h 2Bh 0h FEATURE CODE (02h) 36-BIT IC SERIAL NUMBER

Figure 3. 64-Bit UID

COMMAND TYPE:

NETWORK

FUNCTION COMMANDS

INTERNAL SUPPLY

VOLTAGE

REGULATOR

FRONT-

END

DATA

MODULATION

ISO 15693

FRAME

FORMATTING

AND

ERROR

DETECTION

MEMORY AND

FUNCTION

CONTROL

BLOCK

MAX66120

AVAILABLE COMMANDS: DATA FIELD AFFECTED:

INVENTORY STAY QUIET SELECT RESET TO READY

UID, AFI, DSFID, ADMINISTRATIVE DATA UID UID UID

UID

USER

EEPROM

GET SYSTEM INFORMATION WRITE SINGLE BLOCK LOCK BLOCK READ SINGLE BLOCK

MEMORY AND CONTROL

FUNCTION COMMANDS

READ MULTIPLE BLOCKS CUSTOM READ BLOCK

WRITE AFI LOCK AFI WRITE DSFID LOCK DSFID

UID, AFI, DSFID, CONSTANTS UID, DATA OF SELECTED MEMORY BLOCK, APPLICABLE PROTECTION CONTROL REGISTER UID, APPLICABLE PROTECTION CONTROL REGISTER UID, SELECTED MEMORY BLOCK, APPLICABLE PROTECTION CONTROL REGISTER UID, SELECTED MEMORY BLOCK, APPLICABLE PROTECTION CONTROL REGISTER MFGCODE, UID, SELECTED MEMORY BLOCK, APPLICABLE PROTECTION CONTROL REGISTER, INTEGRITY BYTES UID, AFI BYTE UID, AFI LOCK BYTE UID, DSFID BYTE UID, DSFID LOCK BYTE

MAX66120

ISO 15693-Compliant 1Kb Memory Fob

4 _______________________________________________________________________________________

Figure 4. Memory Map

bit locations 49 to 56 identifies the chip manufacturer, according to ISO/IEC 7816-6/AM1. This code is 2Bh for Maxim. The code in the upper 8 bits is E0h. The UID is read accessible through the Inventory and Get System Information commands.

Detailed Memory Description

The memory of the MAX66120 is organized as 18 blocks of 8 bytes each. Figure 4 shows the memory map. The first 16 blocks (block numbers 00h to 0Fh in hexadecimal counting) are the user EEPROM, the area for application-specific data. Four adjacent blocks are also referred to as a page. Blocks 00h to 03h are page 0, blocks 04h to 07h are page 1, blocks 08h to 0Bh are page 2, and blocks 0Ch to 0Fh are page 3.

Block 10h provides storage for user-programmable parameters that are defined by the ISO 15693 standard. These are AFI and DSFID. The remaining bytes (U1 to U6) are not defined by the communication standard; the application software can use them, e.g., for

proprietary markings. Block 11h contains control bytes that determine the operation of the individual pages (EPROM-emulation mode or write protection of individual blocks), or to write protect U1 to U4, the AFI, and the DSFID byte. The S-Lock byte, if programmed to a suitable code, only protects itself from future changes. The self-protection feature can be used to permanently mark the fob as being “special,” as defined by the application. Table 1 illustrates the relationship between the controlling register in block 11h and the memory area affected. Tables 2 and 3 specify the code assignments to achieve the protection.

Besides the storage for 8 data bytes, each memory block has 2 integrity bytes, which are not memory mapped. The integrity bytes function as a MAX66120maintained, 16-bit write-cycle counter. Having reached its maximum value of 65,535, the write-cycle counter stops incrementing, but does not prevent additional write cycles to the memory block. The integrity bytes can be read through the Custom Read Block command.

BLOCK

NUMBER

00h Page 0 User EEPROM R/(W) Write-Cycle Counter

01h Page 0 User EEPROM R/(W) Write-Cycle Counter

02h Page 0 User EEPROM R/(W) Write-Cycle Counter

03h Page 0 User EEPROM R/(W) Write-Cycle Counter

04h Page 1 User EEPROM R/(W) Write-Cycle Counter

05h Page 1 User EEPROM R/(W) Write-Cycle Counter

06h Page 1 User EEPROM R/(W) Write-Cycle Counter

07h Page 1 User EEPROM R/(W) Write-Cycle Counter

08h Page 2 User EEPROM R/(W) Write-Cycle Counter

09h Page 2 User EEPROM R/(W) Write-Cycle Counter

0Ah Page 2 User EEPROM R/(W) Write-Cycle Counter

0Bh Page 2 User EEPROM R/(W) Write-Cycle Counter

0Ch Page 3 User EEPROM R/(W) Write-Cycle Counter

0Dh Page 3 User EEPROM R/(W) Write-Cycle Counter

0Eh Page 3 User EEPROM R/(W) Write-Cycle Counter

0Fh Page 3 User EEPROM R/(W) Write-Cycle Counter

10h U1 U2 U3 U4 AFI DSFID U5 U6 Write-Cycle Counter

11h BP1 BP2 BP3 BP4 U-Lock AFI-Lock

01234567LSBMSB

DATA BYTE NUMBER

(SEQUENCE LEFT TO RIGHT AS WRITTEN TO OR READ FROM DEVICE)

DSFID-

Lock

INTEGRITY BYTES

S-Lock Write-Cycle Counter

MAX66120

ISO 15693-Compliant 1Kb Memory Fob

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Table 1. Memory Protection Matrix

Legend for Table 1:

Table 2. BP1 to BP4 Protection Code Assignments

If programmed to a locking (protecting) code, the controlling register irreversibly protects itself from further changes. See Tables 2

and 3 for additional details.

Note: Do not program the upper nibble of BP4 to 9 or 5, because this blocks the read access to blocks 0Ch to 0Fh.

CONTROLLING

BP1 E, W — — — — — — —

BP2 — E, W — — — — — —

BP3 — — E, W — — — — —

BP4 — — — E, W — — — —

U-Lock — — — — W — — —

AFI-Loc k — — — — — W — —

DSFID-Lock — — — — — — W —

S-Lock — — — — — — — W

BLOCKS

00h TO 03h

BLOCKS

04h TO 07h

BLOCKS

08h TO 0Bh

AFFECTED MEMORY AREA

BLOCKS

0Ch TO 0Fh

U1 TO U4 AFI DSFID S-LOCK

CODE DESCRIPTION

E ERPOM-Emulation Mode

W Write Protection

CODE DESCRIPTION

00000000b (00h)

00001010b (0Ah)

1010<b3><b2><b1><b0>b (Axh)

Unlocked (factory default)

EPROM-Emulation Mode (irreversible) BP1: blocks 00h to 03h BP2: blocks 04h to 07h BP3: blocks 08h to 0Bh BP4: bloc ks 0Ch to 0Fh

Write-Protect Block Mode. Once set to Ah, the upper nibble cannot be changed to any other value (irreversible). The bits of the lower nibble can still be changed only from 0 (unlocked) to 1 (locked) to write protect blocks individually. b0: block 00h (BP1), block 04h (BP2), block 08h (BP3), block 0Ch (BP4) b1: block 01h (BP1), block 05h (BP2), block 09h (BP3), block 0Dh (BP4) b2: block 02h (BP1), block 06h (BP2), block 0Ah (BP3), block 0Eh (BP4) b3: block 03h (BP1), block 07h (BP2), block 0Bh (BP3), block 0Fh (BP4)

MAX66120

ISO 15693-Compliant 1Kb Memory Fob

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ISO 15693 Communication

Concept

The communication between the master and the MAX66120 (slave) is based on the exchange of data packets. The master initiates every transaction; only one side (master or slaves) transmits information at any time. Each data packet begins with a start-of-frame (SOF) pattern and ends with an end-of-frame (EOF) pattern. A data packet with at least 3 bytes between SOF and EOF is called a frame (Figure 5). The last 2 bytes of an ISO 15693 frame are an inverted 16-bit

CRC of the preceding data generated according to the CRC-16-CCITT polynomial. This CRC is transmitted with the LSB first. For more details on the CRC-16-CCITT, refer to ISO 15693 Part 3, Annex C.

For transmission, the frame information is modulated on a carrier frequency, which is 13.56MHz for ISO 15693. The subsequent paragraphs are a concise description of the required modulation and coding. For full details including graphics of the data coding schemes and SOF/EOF timing, refer to ISO 15693-2, Sections 7.2,

7.3, and 8.

Table 3. Protection Code Assignments for U-Lock, AFI-Lock, DSFID-Lock, S-Lock

Figure 5. ISO 15693 Frame Format

Figure 6. Downlink Modulation (e.g., Approximately 100% Amplitude Modulation)

CODE DESCRIPTION

00000000b (00h)

10101010b (AAh)

All other codes Unlocked

SOF 1 OR MORE DATA BYTES CRC (LSB) CRC (MSB) EOF

Unlocked (factory default)

Locked (irreversible)

CARRIER

AMPLITUDE

100%

TIME

MAX66120

ISO 15693-Compliant 1Kb Memory Fob

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The path from master to slave uses amplitude modula- tion (Figure 6); the modulation index can be either in the range of 10% to 30% or 100% (ISO 15693-2, Section 7.1). The standard defines two pulse-position coding schemes that must be supported by a compliant device. Scheme A uses the “1 out of 256” method (Figure 7), where the transmission of 1 byte takes

4.833ms, equivalent to a data rate of 1655bps. The location of a modulation notch during the 4.833ms conveys the value of the byte. Scheme B uses the “1 out of 4” method (Figure 8), where the transmission of 2 bits takes 75.52µs, equivalent to a data rate of 26,484bps. The location of a modulation notch during the 75.52µs conveys the value of the 2 bits. A byte is transmitted as a concatenation of four 2-bit transmissions, with the least significant 2 bits of the byte being transmitted first. The transmission of the SOF pattern takes the same time as transmitting 2 bits in Scheme B. The SOF pattern has two modulation notches, which makes it distinct from any 2-bit pattern. The position of the second notch tells whether the frame uses the “1 out of 256” or “1 out of 4” coding scheme (Figures 9 and 10, respectively). The transmission of the EOF pattern takes 37.76µs; the EOF is the same for both coding schemes and has one modulation notch (Figure 11).

The path from slave to master uses one or two subcarriers, as specified by the Subcarrier_flag bit in the request data packet. The standard defines two data rates for the response, low (approximately 6600bps) and high (approximately 26,500bps). The Data_rate_flag bit in the

request data packet specifies the response data rate. The data rate varies slightly depending on the use of one or two subcarriers. The LSb is transmitted first. A compliant device must support both subcarrier modes and data rates.

In the single subcarrier case, the subcarrier frequency is 423.75kHz. One bit is transmitted in 37.76µs (high data rate) or 151µs (low data rate). The modulation is the on/off key. For a logic 0, the subcarrier is on during the first half of the bit transmission time and off for the second half. For a logic 1, the subcarrier is off during the first half of the bit transmission time and on for the second half. See Figure 12 for more details.

In the two subcarrier cases, the subcarrier frequencies are 423.75kHz and 484.28kHz. The bit duration is the same as in the single subcarrier case. The modulation is equivalent to binary FM. For a logic 0, the lower subcarrier is on during the first half of the bit transmission time, switching to the higher subcarrier for the second half. For a logic 1, the higher subcarrier is on during the first half of the bit transmission time, switching to the lower subcarrier for the second half. See Figure 13 for details. The transmission of the SOF pattern takes the same time as transmitting 4 bits (approximately 151µs at a high data rate or approximately 604µs at a low data rate). The SOF is distinct from any 4-bit data sequence. The EOF pattern is equivalent to a SOF being transmitted backwards. The exact duration of the SOF and EOF varies slightly depending on the use of one or two subcarriers (see Figures 14 and 15, respectively).

Figure 7. Downlink Data Coding (Case “1 Out of 256”)

PULSE-

MODULATED

CARRIER

~ 9.44μs

~ 18.88μs

01234 . . . . .2

....... ........2

2 5

.....

5 2

~ 4.833ms

MAX66120

ISO 15693-Compliant 1Kb Memory Fob

8 _______________________________________________________________________________________

Figure 9. Downlink SOF for “1 Out of 256” Coding (Carrier Not Shown)

Figure 8. Downlink Data Coding (Case “1 Out of 4”) (Carrier Not Shown)

PULSE POSITION “00”

~ 9.44μs ~ 9.44μs

~ 75.52μs

PULSE POSITION “01” (1 = LSb)

~ 28.32μs

PULSE POSITION “10” (0 = LSb)

~ 47.20μs

PULSE POSITION “11”

~ 9.44μs

~ 75.52μs

~ 66.08μs

~ 75.52μs

~ 9.44μs

~ 37.76μs ~ 37.76μs

~ 9.44μs

+ 16 hidden pages