The MAX5974_ provide control for wide-input-voltage,
active-clamped, current-mode PWM, forward converters
in Power-over-Ethernet (PoE) powered device (PD) applications. The MAX5974A/MAX5974C are well-suited for
universal or telecom input range, while the MAX5974B/
MAX5974D also accommodate low input voltage down
to 10.5V.
The devices include several features to enhance supply
efficiency. The AUX driver recycles magnetizing current instead of wasting it in a dissipative clamp circuit.
Programmable dead time between the AUX and main
driver allows for zero-voltage switching (ZVS). Under lightload conditions, the devices reduce the switching frequency (frequency foldback) to reduce switching losses.
The MAX5974A/MAX5974B feature unique circuitry to
achieve output regulation without using an optocoupler,
while the MAX5974C/MAX5974D utilize the traditional
optocoupler feedback method. An internal error amplifier
with a 1% reference is very useful in nonisolated design,
eliminating the need for an external shunt regulator.
The devices feature a unique feed-forward maximum
duty-cycle clamp that makes the maximum clamp voltage during transient conditions independent of the line
voltage, allowing the use of a power MOSFET with lower
breakdown voltage. The programmable frequency dithering feature provides low-EMI, spread-spectrum operation.
The MAX5974_ are available in 16-pin TQFN-EP packages and are rated for operation over the -40°C to +85°C
temperature range.
NDRV, AUXDRV (pulsed for less than 100ns) .................. Q1A
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
+ 0.3V)
IN
ELECTRICAL CHARACTERISTICS
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), V
V
, VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, CIN = 1FF, TA = -40NC to +85NC,
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), V
V
, VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, CIN = 1FF, TA = -40NC to +85NC,
GND
unless otherwise noted. Typical values are at T
= +25NC.) (Note 2)
A
CS
= V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
AUXDRV DRIVER
Pulldown ImpedanceR
Pullup ImpedanceR
AUX-N
AUX-P
I
I
(sinking) = 50mA4.37.7
AUXDRV
(sourcing) = 25mA10.618.9
AUXDRV
Peak Sink Current0.5A
Peak Source Current0.3A
Fall Timet
Rise Timet
AUX-F
AUX-R
C
C
= 1nF24ns
AUXDRV
= 1nF45ns
AUXDRV
DEAD-TIME PROGRAMMING (DT)
DT Bias VoltageV
NDRV to AUXDRV Delay
(Dead Time)
DT
From NDRV falling
t
DT
to AUXDRV falling
AUXDRV rising to
NDRV rising
R
DT
R
DT
R
DT
R
DT
CURRENT-LIMIT COMPARATORS (CS)
Cycle-by-Cycle Peak
Current-Limit Threshold
V
CS-PEAK
= V
CSSC
= 10kI
= 100kI
= 10kI
= 100kI
= V
DITHER/SYNC
FB
= V
1.215V
40
300350410
40
310360420
375393410mV
FFB
= V
DCLMP
I
I
ns
ns
=
Cycle-by-Cycle Reverse
Current-Limit Threshold
Current-Sense Blanking Time
t
for Reverse Current Limit
Number of Consecutive Peak
Current-Limit Events to Hiccup
Current-Sense Leading-Edge
Blanking Time
Propagation Delay from
Comparator Input to NDRV
Minimum On-Timet
V
CS-REV
CS-BLANK-
REV
N
HICCUP
t
CS-BLANK
t
PDCS
ON-MIN
Turns AUXDRV off for the remaining
cycle if reverse current limit is exceeded
-118-100-88mV
From AUXDRV falling edge115ns
8Events
From NDRV rising edge115ns
From CS rising (10mV overdrive) to
NDRV falling (excluding leading-edge
35ns
blanking)
100150200ns
SLOPE COMPENSATION (CSSC)
Slope Compensation Current
Ramp Height
MAX5974A/MAX5974B/MAX5974C/MAX5974D
PWM COMPARATOR
Comparator Offset VoltageV
Current-Sense GainA
Current-Sense Leading-Edge
Blanking Time
Comparator Propagation Delayt
PWM-OS
CS-PWM
t
CSSC-BLANK
PWM
Current ramp’s peak added to CSSC
input per switching cycle
V
- V
COMP
DV
COMP
/DV
CSSC
CSSC
(Note 4)
475258
1.351.72V
3.13.333.6V/V
From NDRV rising edge115ns
Change in V
internal leading-edge blanking)
= 10mV (including
CSSC
150ns
FA
4
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), V
V
, VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, CIN = 1FF, TA = -40NC to +85NC,
GND
unless otherwise noted. Typical values are at T
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ERROR AMPLIFIER
FB Reference VoltageV
FB Input Bias CurrentI
Voltage GainA
Transconductanceg
Transconductance BandwidthBW
Source CurrentVFB = 1V, V
Sink CurrentV
FREQUENCY FOLDBACK (FFB)
V
Gain
-to-FFB Comparator
CSAVG
= +25NC.) (Note 2)
A
REF
FB
EAMP
M
10V/V
VFB when I
V
= 2.5V
COMP
VFB = 0 to 1.75V
Open loop (typical gain
= 1) -3dB frequency
= 1.75V, V
FB
COMP
COMP
COMP
= 0,
= V
CS
= 2.5V300375455
= 1V300375455
= V
CSSC
MAX5974A/
MAX5974B
MAX5974C/
MAX5974D
MAX5974A/
MAX5974B
MAX5974C/
MAX5974D
80dB
MAX5974A/
MAX5974B
MAX5974C/
MAX5974D
MAX5974A/
MAX5974B
MAX5974C/
MAX5974D
DITHER/SYNC
1.2021.2151.227
-250+250
-500+100
= V
= V
FB
FFB
1.51.521.54
1.82.553.2
1.82.663.5
2
30
= V
DCLMP
V
nA
mS
MHz
FA
FA
MAX5974A/MAX5974B/MAX5974C/MAX5974D
=
FFB Bias CurrentI
NDRV Switching Frequency
During Foldback
Note 2: All devices are 100% production tested at T
Note 3: See the Output Short-Circuit Protection with Hiccup Mode section.
Note 4: The parameter is measured at the trip point of latch with V
DV
CSSC
< 0.25V.
FFB
f
SW-FB
V
= 0V, VCS = 0V (not in FFB mode)263033
FFB
fSW/2kHz
= +25NC. Limits over temperature are guaranteed by design.