The MAX5971B is a single-port power controller designed
for use in IEEEM 802.3af/at-compliant power-sourcing
equipment (PSE). This device provides powered device
(PD) discovery, classification, current limit, and DC and
AC load-disconnect detections. The MAX5971B supports both fully automatic operation and software programmability, and features an integrated power MOSFET
and sense resistor. The device supports detection and
classification operation from a single 54V supply. In
addition, it supports 2-event classification and new Class
5 classification of high-power PDs. The MAX5971B provides up to 40W to a single port (Class 5 enabled) and
still provides high-capacitance detection for legacy PDs.
The device provides four operating modes to suit different system requirements. By default, auto mode allows
the device to operate automatically at its default settings
without any software. Semiautomatic mode automatically
detects and classifies a device connected to the port
after initial software activation, but does not power the
port until instructed to by software. Manual mode allows
total software control of the device and is useful for
system diagnostics. Shutdown mode terminates all port
activities and securely turns off power to the port.
The IC features an I2C-compatible, 2-wire serial interface, and is fully software-configurable and programmable. The device provides instantaneous readout of
port current through the I2C interface. The device’s
extensive programmability enhances system flexibility,
enables field diagnosis and allows for uses in other, non
standard applications.
The device provides input undervoltage lockout (UVLO),
input undervoltage detection, input overvoltage lockout,
overtemperature protection, output voltage slew-rate limit
during startup, and LED status indication. The MAX5971B
programmability includes startup timeout, overcurrent
timeout, and load-disconnect detection timeout.
The device is available in a space-saving, 28-pin TQFN
(5mm x 5mm) power package and is rated for the
extended (-40NC to +85NC) temperature range.
Applications
Single-Port PSE End-Point Applications
Single-Port PSE Power Injectors (Midspan Applications)
Switches/Routers
PSE Controller with I2C
Features
SIEEE 802.3af/at Compliant
SUp to 40W for Single-Port PSE Applications
SIntegrated Power MOSFET and Sense Resistor
SSupports 54V Single-Supply Operation
SPD Detection and Classification
SI2C-Compatible, 2-Wire Serial Interface
SInstantaneous Readout of Port Current Through
I2C Interface
SProgrammable Current Limit for Class 5 PDs
SHigh-Capacitance Detection for Legacy Devices
SSupports Both DC and AC Load Removal
Detections
SCurrent Foldback and Duty-Cycle-Controlled
Current Limit
SLED Indicator for Port Status
SDirect Fast-Shutdown Control Capability
SSpace-Saving, 28-Pin TQFN (5mm x 5mm) Power
Package
Ordering Information
PARTTEMP RANGEPIN-PACKAGE
MAX5971BETI+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
-40NC to +85NC
Typical Operating Circuit
-54V
V
V
LED
PWMEN
LEGACY
MIDSPAN
OSC
EN
AGND
EE
EE_DIG
MAX5971B
SDA SCL AD0INT
OUT
OUTP
DET
ILIM1
ILIM2
28 TQFN-EP*
PSE OUTPUT
MAX5971B
SERIAL INTERFACE
IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Single-Port, 40W, IEEE 802.3af/at,
PSE Controller with I2C
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to VEE, unless otherwise noted.)
AGND, DET, LED ..................................................-0.3V to +80V
OUT .......................................................-0.3V to (AGND + 0.3V)
OUTP ........................................................-6V to (AGND + 0.3V)
V
OSC .........................................................................-0.3V to +6V
EN, PWMEN, MIDSPAN, LEGACY, ILIM1, ILIM2 ....-0.3V to +4V
INT, AD0, SCL, SDA ................................................-0.3V to +6V
Maximum Current into INT and SDA ..................................80mA
MAX5971B
Maximum Current into LED ................................................40mA
Maximum Current into OUT ........................Internally Regulated
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
................................................................-0.3V to +0.3V
EE_DIG
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
- VEE = 32V to 60V, TA = -40NC to +85NC, all voltages are referenced to VEE, unless otherwise noted. Typical values are at
AGND
V
- VEE = +54V, TA = +25NC. Currents are positive when entering the pin and negative otherwise.) (Note 2)
Single-Port, 40W, IEEE 802.3af/at,
PSE Controller with I2C
ELECTRICAL CHARACTERISTICS (continued)
(V
- VEE = 32V to 60V, TA = -40NC to +85NC, all voltages are referenced to VEE, unless otherwise noted. Typical values are at
AGND
V
- VEE = +54V, TA = +25NC. Currents are positive when entering the pin and negative otherwise.) (Note 2)
AGND
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ADC PERFORMANCE (Power-On Mode)
Resolution9Bits
Range1.507A
LSB Step Size2.95mA
MAX5971B
Gain Error
ADC Absolute AccuracyI
Integral NonlinearityINL0.31.7LSB
Differential NonlinearityDNL0.31.7LSB
TIMING CHARACTERISTICS (For 2-Wire Fast Mode)
Serial Clock Frequencyf
Bus Free Time Between a STOP
and START Condition
Hold Time for a START Conditiont
Low Period of the SCL Clockt
High Period of the SCL Clockt
Setup Time for a Repeated
START Condition (Sr)
Data Hold Timet
Data in Setup Timet
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmittingt
Setup Time for STOP Conditiont
Capacitive Load for Each
Bus Line
SCL
t
BUF
HD,STA
LOW
HIGH
t
SU,STA
HD,DAT
SU,DAT
t
SU,STO
C
TA = +25NC
TA = -40NC to +85NC
= 400mA130136142LSB
OUT
1.3µs
0.6µs
1.3µs
0.6µs
0.6µs
0150ns
100ns
(Note 9)
R
(Note 9)250ns
F
(Note 9)400pF
B
20 +
0.1C
B
0.6µs
2
4
400kHz
300ns
%
Pulse Width of Spike Suppressedt
Note 2: This device is production tested at T
Note 3: Default thresholds are set by the classification result in auto mode. The thresholds are manually software programmable
through the ICUT Register (R2Ah[2:0]). If ILIM1 and ILIM2 are both unconnected, Class 5 detection is disabled. See the
Class 5 PD Classification section and Table 3 for details and settings.
Note 4: Default value. The AC load-disconnect threshold can be programmed through the AC_TH register (R23h[2:0]).
Note 5: Default value. The load-disconnect time, t
Note 6: R
Note 7: If Class 5 is enabled, this value is the classification current threshold from Class 4 to Class 5.
Note 8: Default values. The startup, fault, and restart timers can be programmed through the TSTART (R16h[5:4]), TFAULT
Note 9: Guaranteed by design. Not subject to production testing.
Single-Port, 40W, IEEE 802.3af/at,
PSE Controller with I2C
Pin Configuration
TOP VIEW
N.C.
N.C.
OSC
18
4567
EE
ILIM1
LED
*EP
ILIM2
N.C.
PWMEN
I.C.
14
13
12
11
10
9
8
MIDSPAN
EN
LEGACY
V
EE_DIG
AD0
INT
SCL
SDA
MAX5971B
*CONNECT TO V
N.C.
DET
N.C.
OUTP
OUT
OUT
N.C.
AGND
20211917 16 15
22
23
24
25
26
27
28
+
12
EE
V
MAX5971B
3
EE
V
V
THIN QFN
.
EE
Pin Description
PINNAMEFUNCTION
1, 2, 3V
4ILIM1
EE
Analog Low-Side Supply Input. Bypass with an external 100V, 47FF capacitor in parallel with a
100V, 0.1FF ceramic capacitor between AGND and VEE.
Class 5 Current-Limit Digital Adjust 1. Referenced to VEE. ILIM1 is internally pulled up to the digital
supply. Use ILIM1 with ILIM2 to enable Class 5 operation and to adjust the Class 5 current-limit
value. See the Electrical Characteristics table and Table 3 in the Class 5 PD Classification section
for details.
Class 5 Current-Limit Digital Adjust 2. Referenced to VEE. ILIM2 is internally pulled up to the digital
5ILIM2
supply. Use ILIM2 with ILIM1 to enable Class 5 operation and to adjust the Class 5 current-limit
value. See the Electrical Characteristics table and Table 3 in the Class 5 PD Classification section
for details.
PWM Control Logic Input. Referenced to VEE. PWMEN is internally pulled up to the digital sup-
6PWMEN
ply. Leave unconnected to enable the internal PWM to drive the LED pin. Force low to disable the
internal PWM.
Detection Collision Avoidance Logic Input. Referenced to VEE. MIDSPAN is internally pulled up
7MIDSPAN
to the digital supply. Leave unconnected to activate the detection collision avoidance circuitry
for midspan PSE systems. Force low to disable this function for an end-point PSE system. The
MIDSPAN logic level latches after the device is powered up or after a reset condition.
8SDA
2-Wire Serial Interface Input/Output Data Line. Referenced to VEE. Connect to VEE if the I2C interface is not used.
N.C.No Connection. Not internally connected. Leave N.C. unconnected.
2-Wire Serial Interface Input Clock Line. Referenced to VEE. Connect to VEE if the I2C interface is
not used.
Open-Drain Interrupt Output. Referenced to VEE. INT is pulled low whenever an interrupt is sent to
the microcontroller. See the Interrupt section for details. Connect to VEE if the I2C interface is not
used.
Address Input. Referenced to VEE. AD0 is used to form the lower part of the device address. See
the Device Address section and Table 5 for details. Connect to VEE if the I2C interface is not used.
Digital Low-Side Supply Input. Connect to VEE externally.
Legacy Detection Logic Input. Referenced to VEE. LEGACY is internally pulled up to the digital
supply. Leave unconnected to activate the legacy PD detection. Force low to disable this function.
The LEGACY logic level latches after the device is powered up or after a reset condition.
Enable Input. Referenced to VEE. EN is internally pulled up to the digital supply. Leave unconnected to enable the device. Force low for at least 40Fs to reset the device. The MIDSPAN, OSC,
and LEGACY states latch-in when the reset condition is removed (low-to-high transition). Bypass
EN to VEE with a 1nF ceramic capacitor.
LED Indicator Open-Drain Output. Referenced to VEE. LED can sink 10mA and can drive an external LED directly. Blinking functionality is provided to signal different conditions (see the PWM and LED Signals section). Connect LED to AGND externally (see Figures 15 and 16) or to an external
supply (if available) through a series resistance.
MAX5971B
AC-Disconnect Triangular Wave Output. Bypass with a 100nF (Q10% tolerance) external capacitor
19OSC
21AGNDHigh-Side Supply Input
23DET
25OUTP
26, 27OUT
—EPExposed Pad. Connect EP to VEE externally. See the Layout Procedure section for details.
to VEE to enable the AC disconnect function. Connect OSC to VEE to disable the AC disconnect
function and to activate the DC disconnect function. The OSC state latches after the device is
powered up or after a reset condition.
Detection/Classification Voltage Output. DET is used to set the detection and classification probe
voltages and for the AC current sensing when using the AC disconnect function. To use the AC
disconnect function, place a 1kI and 0.47FF RC series in parallel with the external protection
diode to OUTP (see Figure 16).
Port Pullup Output. OUTP is used to pull up the port voltage to AGND when needed. If AC disconnect is used, connect OUTP to the anode of the AC-blocking diode. If AC disconnect is not
used, connect OUTP to OUT (see Figures 15 and 17). Bypass OUTP to AGND with a 100V, 0.1FF
ceramic capacitor.
Integrated MOSFET Output. If DC disconnect is used, connect the port output to OUTP (see
Figures 15 and 17). If the AC disconnect function is used, connect OUT to the cathode of the
AC-blocking diode (see Figure 16).
Single-Port, 40W, IEEE 802.3af/at,
PSE Controller with I2C
Simplified Diagram
SCLSDA
ADO
SERIAL PORT
INTERFACE (SPI)
EN
MAX5971B
LEGACY
MIDSPAN
AGND
V
LED
INT
EE
REGISTER FILE
ANALOG
BIAS AND
SUPPLY
MONITOR
CENTRAL LOGIC
UNIT (CLU)
INTERNAL
SUPPLIES
VOLTAGE
REFERENCES
CURRENT
REFERENCES
OSC STATUS
MONITOR
PORT STATE
MACHINE (SM)
PWM
OSC
TRIANGLE
WAVE
GENERATOR
AC DISCONNECT
SIGNAL (ACD)
MAX5971B
VOLTAGE
PROBING AND
CURRENT-LIMIT
CONTROL
DETECTION AND
CLASSIFICATION
CONTROL
A = 1
AC DETECTOR
THRESHOLD
SETTINGS
CURRENT SENSING
9-BIT ADC
AC DISCONNECT
ENABLE
POWER ENABLE
ACD
REFERENCE
CURRENT
CURRENT-LIMIT,
OVERCURRENT, AND OPEN-
CIRCUIT SENSING,
AND FOLDBACK CONTROL
CLASS 5 ENABLE/DISABLE,
OVERCURRENT AND
CURRENT-LIMIT CONTROL
GATEDRIVE
CONTROL
VOLTAGE
SENSING
FOLDBACK
CONTROL
INTERNAL
INTERNAL
AGND
MOSFET
R
SENSE
DET
OUTP
OUT
ILIM2
ILIM1PWMEN
Detailed Description
The MAX5971B is a single-port power controller designed
for use in IEEE 802.3af/802.3at-compliant PSE. This
device provides PD discovery, classification, current
limit, and DC and AC load-disconnect detections. The
MAX5971B supports both fully automatic operation and
software programmability, and features an integrated
of port current through the I2C interface. The MAX5971B
provides input undervoltage lockout (UVLO), input undervoltage detection, input overvoltage lockout, overtemperature protection, output voltage slew-rate limit during startup, and LED status indication. The MAX5971B
programmability includes startup timeout, overcurrent
timeout, and load-disconnect detection timeout.
power MOSFET and sense resistor. The device also supports new Class 5 and 2-event classification for detection
and classification of high-power PDs. The MAX5971B
provides up to 40W to a single port (Class 5 enabled), and
still provides high-capacitance detection for legacy PDs.
The MAX5971B features an I2C-compatible, 2-wire serial
interface, and is fully software configurable and programmable. The device provides instantaneous readout
The MAX5971B is reset by any of the following conditions:
1) Power-Up. Reset condition is cleared once VEE rises
above the UVLO threshold.
2) Hardware Reset. Reset occurs once the EN input is
driven low (> 40Fs, typ) any time after power-up. The
device exits the reset condition once the EN input is
driven high again.
Reset
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