The MAX5970 dual hot-swap controller provides complete protection for systems with two supply voltages
from 0V to +16V. The MAX5970 includes four programmable LED outputs. The two hot-swap channels can be
configured to operate as independent hot-swap controllers, or as a pair operating together so that both channels shut down if either channel experiences a fault.
The MAX5970 provides two programmable levels of
overcurrent circuit-breaker protection: a fast-trip threshold for a fast turn-off, and a lower slow-trip threshold for
a delayed turn-off. The maximum overcurrent circuitbreaker threshold range is set independently for each
channel with a trilevel logic input IRNG_, or by programming though the I2C interface.
The MAX5970 is an advanced hot-swap controller that
monitors voltage and current with an internal 10-bit
ADC which is continuously multiplexed to convert the
output voltage and current of both hot-swap channels at
10ksps. Each 10-bit sample is stored in an internal circular buffer so that 50 past samples of each signal can be
read back through the I2C interface at any time or after
a fault condition.
The device includes five user-programmable digital
comparators per hot-swap channel to implement overcurrent warning and two levels of overvoltage/undervoltage detection. When any of the measured values violates
the programmable limits, an external ALERT output is
asserted. In addition to the ALERT signal, the MAX5970
can be programmed to deassert the power-good signal
and/or turn off the external MOSFET.
The MAX5970 features four I/Os that can be independently configured as general-purpose inputs/outputs
(GPIOs) or as open-drain LED drivers with programmable blinking. These four I/Os can be configured for
any mix of LED driver or GPIO function.
The MAX5970 is available in a 36-pin thin QFN-EP package and operates over the -40NC to +85NC extended
temperature range.
Features
S Two Independent Hot-Swap Controllers Operate
from 0V to +16V
S 10-Bit ADC Monitors Voltage and Current of Each
Channel
S Circular Buffers Store 5ms of Current and Voltage
Measurements
S Two Independent Internal Charge Pumps
Generate n-Channel MOSFET Gate Drives
S Internal 500mA Gate Pulldown Current for Fast
Shutdown
S VariableSpeed/BiLevel™ Circuit-Breaker
Protection
S Independent Precision-Voltage Enable Inputs
S Alert Output Indicates Fault and Warning
Conditions
S Independent Power-Good Outputs
S Independent Fault Outputs
S Four Open-Drain Outputs Sink 25mA to Directly
Drive LEDs
S Programmable LED Flashing Function
S Autoretry or Latched Fault Management
S 400kHz I
S Small 6mm x 6mm, 36-Pin TQFN-EP Package
2
C Interface
Applications
Single PCI ExpressM Hot-Plug Slot
Blade Servers
Disk Drives/DASD/Storage Systems
Soft-Switch for ASICs, FPGAs, and Microcontrollers
with Independent Core and I/O Voltages
Ordering Information
PARTTEMP RANGEPIN-PACKAGE
MAX5970ETX+
-40NC to +85NC
36 TQFN-EP*
MAX5970
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
VariableSpeed/BiLevel is a trademark of Maxim Integrated Products, Inc.
PCI Express is a registered trademark of PCI-SIG Corp.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
0V to 16V, Dual Hot-Swap Controller with 10-Bit
Current and Voltage Monitor and 4 LED Drivers
ABSOLUTE MAXIMUM RATINGS
IN, SENSE_, MON_, GATE_ to AGND ..................-0.3V to +30V
LED_ to AGND ......................................................-0.3V to +16V
ON_, SDA, SCL to AGND ........................................-0.3V to +6V
REG, DREG, IRNG_, MODE, PROT, A_,
PG_, ALERT, FAULT_ to AGND ................................-0.3V to +4V
REG to DREG .......................................................-0.3V to +0.3V
RETRY, HWEN, POL to AGND ................-0.3V to (V
GATE1 to MON1, GATE2 to MON2 ........................-0.3V to +6V
MAX5970
GND_, DGND to AGND .......................................-0.3V to +0.3V
SDA, ALERT Current ....................................... -20mA to +50mA
LED_ Current ................................................. -20mA to +100mA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal consideration, refer to www.maxim-ic.com/thermal-tutorial.
**As per JEDEC51 Standard (Multilayer Board)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
REG
+ 0.3V)
ELECTRICAL CHARACTERISTICS
(VIN = 2.7V to 16V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VIN = 3.3V and TA = +25NC.) (Note 2)
27DGNDDigital Ground. Connect all GND_ and DGND to AGND externally using a star connection.
28ON2Channel 2 Precision Turn-On Input
29RETRY
30MODE
31LED4LED Driver 4
32LED3LED Driver 3
33GND2
34GATE2Channel 2 Gate-Drive Output. Connect to gate of an external n-channel MOSFET.
35MON2Channel 2 Voltage Monitoring Input
36SENSE2
—EPExposed Pad. EP is internally grounded. Connect externally to ground plane using a star connection.
FAULT1Channel 1 Active-Low Open-Drain Fault Output. FAULT1 goes low if an overcurrent occurs on channel 1.
FAULT2Channel 2 Active-Low Open-Drain Fault Output. FAULT2 goes low if an overcurrent occurs on channel 2.
ALERTOpen-Drain Alert Output. ALERT goes low during a fault to notify the system of an impending failure.
Polarity Select Input. Connect to DREG for active-high power-good outputs (PG_). Connect to GND for
active-low power-good outputs.
Logic Power-Supply Input. Connect to REG externally through a 10I resistor and to DGND with a 1FF
ceramic capacitor.
Hardware Enable Input. Connect to DREG or DGND. State is read upon power-up as VIN crosses the
UVLO threshold and sets enable register bits with this value. After UVLO, this input becomes inactive until
power is cycled.
Autoretry Fault Management Input. Connect to DREG to enable autoretry operation. Connect to DGND to
enable latched-off operation.
Hot-Swap Two-State Mode Select Input. Connect MODE to DGND, DREG or leave it unconnected to operate the hot-swap channels independently or as a pair.
Channel 2 Gate Discharge Current Ground Return. Connect all GND_ and DGND to AGND externally
using a star connection.
Channel 2 Current-Sense Input. Connect SENSE2 to the source of an external MOSFET and to one end of
R
0V to 16V, Dual Hot-Swap Controller with 10-Bit
Current and Voltage Monitor and 4 LED Drivers
Detailed Description
The MAX5970 includes a set of registers that are
accessed through the I2C interface. Some of the registers
Table 1a. Register Address Map (Channel Specific)
MAX5970
REGISTERDESCRIPTIONCHANNEL 1CHANNEL 2
adc_chx_cs_msb
adc_chx_cs_lsb
adc_chx_mon_msb
adc_chx_mon_ lsb
min_chx_cs_msb
min_chx_cs_ lsb
max_chx_cs_msb
max_chx_cs_ lsb
min_chx_mon_msb
min_chx_mon_ lsb
max_chx_mon_msb
max_chx_mon_ lsb
uv1thr _chx_msb
uv1thr_chx_ lsb
uv2thr_chx_msb
uv2thr_chx_ lsb
ov1thr_chx_msb
ov1thr_chx_ lsb
High 8 bits ([9:2]) of latest current-signal
ADC result
Low 2 bits ([1:0]) of latest current-signal ADC
result
High 8 bits ([9:2]) of latest voltage-signal
ADC result
Low 2 bits ([1:0]) of latest voltage-signal
ADC result
High 8 bits ([9:2]) of current-signal minimum
value
Low 2 bits ([1:0]) of current-signal minimum
value
High 8 bits ([9:2]) of current-signal maximum
value
Low 2 bits ([1:0]) of current-signal maximum
value
High 8 bits ([9:2]) of voltage-signal minimum
value
Low 2 bits ([1:0]) of voltage-signal minimum
value
High 8 bits ([9:2]) of voltage-signal maximum
value
Low 2 bits ([1:0]) of voltage-signal maximum
value
High 8 bits ([9:2]) of undervoltage warning
(UV1) threshold
Low 2 bits ([1:0]) of undervoltage warning
(UV1) threshold
High 8 bits ([9:2]) of undervoltage critical
(UV2) threshold
Low 2 bits ([1:0]) of undervoltage critical
(UV2) threshold
High 8 bits ([9:2]) of overvoltage warning
(OV1) threshold
Low 2 bits ([1:0]) of overvoltage warning
(OV1) threshold
are read only and some of the registers are read and write
that are updated to configure the MAX5970 for a specific
operation. See Tables 1a and 1b for the registers map.
High 8 bits ([9:2]) of overvoltage critical
(OV2) threshold
Low 2 bits ([1:0]) of overvoltage critical
(OV2) threshold
High 8 bits ([9:2]) of overcurrent warning
threshold
Low 2 bits ([1:0]) of overcurrent warning
threshold
Base address for block read of 50-sample
voltage-signal data buffer
Base address for block read of 50-sample
current-signal data buffer
0x200x2A0xFFR/W
0x210x2B0x03R/W
0x220x2C0xFFR/W
0x230x2D0x03R/W
0x460x48—R
0x470x49—R
RESET
VALUE
Table 1b. Register Address Map (General)
REGISTERDESCRIPTION
mon_rangeMON input range setting0x180x00R/W
cbuf_chx_storeSelective enabling of circular buffer0x190x0FR/W
ifast2slowCurrent threshold fast-to-slow ratio setting0x300x0FR/W
status0Slow-trip and fast-trip comparators status register0x310x00R
status1PROT, MODE, and ON_ inputs status register0x32—R
status2
status3
fault0Status register for undervoltage detection (warning or critical)0x350x00R/C
fault1Status register for overvoltage detection (warning or critical)0x360x00R/C
fault2Status register for overcurrent detection (warning)0x370x00R/C
pgdlyDelay setting between MON measurement and PG_ assertion0x380x00R/W
fokeyLoad register with 0xA5 to enable force-on function0x390x00R/W
fosetRegister that enables force-on function for a channel0x3A0x00R/W
chxenChannel enable bits0x3B—R/W
dgl_iOC deglitch enable bits0x3C0x00R/W
dgl_uvUV deglitch enable bits0x3D0x00R/W
dgl_ovOV deglitch enable bits0x3E0x00R/W
cbufrd_hibyonlyCircular buffers readout mode: 8 bit or 10 bit0x3F0x0FR/W
cbuf_dly_stop
peak_log_rstReset control bits for peak-detection registers0x410x00R/W
peak_log_holdHold control bits for peak-detection registers0x420x00R/W
Fast-trip threshold maximum range setting bits, from IRNG_
three-state inputs
LATCH, POL, ALERT, and PG_ status register
Circular buffer stop-delay. Number of samples recorded to the
circular buffer after channel shutdown.