Rainbow Electronics MAX5969B User Manual

19-5008; Rev 0; 12/09

EVALUATION KIT

AVAILABLE

IEEE 802.3af/at-Compliant, Powered Device Interface

Controllers with Integrated Power MOSFET

General Description

The MAX5969A/MAX5969B provide a complete interface
for a powered device (PD) to comply with the IEEE®

802.3af/at standard in a power-over-Ethernet (PoE) sys­tem. The MAX5969A/MAX5969B provide the PD with a
detection signature, classification signature, and an inte­grated isolation power switch with inrush current control.
During the inrush period, the MAX5969A/MAX5969B limit
the current to less than 180mA before switching to the
higher current limit (720mA to 880mA) when the isolation
power MOSFET is fully enhanced. The devices feature
an input UVLO with wide hysteresis and long deglitch
time to compensate for twisted-pair cable resistive drop
and to assure glitch-free transition during power-on/-off
conditions. The MAX5969A/MAX5969B can withstand up
to 100V at the input.

The MAX5969A/MAX5969B support a 2-event classifica­tion method as specified in the IEEE 802.3at standard
and provide a signal to indicate when probed by Type 2
power-sourcing equipment (PSE). The devices detect
the presence of a wall adapter power-source connec­tion and allow a smooth switchover from the PoE power
source to the wall power adapter.

The MAX5969A/MAX5969B also provide a power-good
(PG) signal, two-step current limit and foldback, over­temperature protection, and di/dt limit.

The MAX5969A/MAX5969B are available in a space-sav­ing, 10-pin, 3mm x 3mm, TDFN power package. These
devices are rated over the -40NC to +85NC extended
temperature range.

Features

S IEEE 802.3af/at Compliant
S 2-Event Classification
S Simplified Wall Adapter Interface
S PoE Classification 0 to 5
S 100V Input Absolute Maximum Rating
S Inrush Current Limit of 180mA Maximum
S Current Limit During Normal Operation Between

720mA and 880mA

S Current Limit and Foldback
S Legacy UVLO at 36V (MAX5969A)
S IEEE 802.3af/at-Compliant, 40V UVLO (MAX5969B)
S Overtemperature Protection
S Thermally Enhanced, 3mm x 3mm, 10-Pin TDFN

Ordering Information

PART TEMP RANGE

MAX5969AETB+

MAX5969BETB+

+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.

-40NC to +85NC

-40NC to +85NC

PIN-

PACKAGE

10 TDFN-EP* 35.4

10 TDFN-EP* 38.6

UVLO

THRESHOLD

(V)

Pin Configuration

MAX5969A/MAX5969B

Applications

TOP VIEW

IEEE 802.3af/at Powered Devices

IP Phones, Wireless Access Nodes, IP Security
Cameras

WiMAXK Base Station

IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.

WiMAX is a trademark of WiMAX Forum.

_______________________________________________________________ Maxim Integrated Products 1

_______________________________________________________________ Maxim Integrated Products 1

V

DD

N.C.

I.C.

SS

*EP = EXPOSED PAD. CONNECT TO V

+

1

2 9

3

4

5 6

MAX5969A
MAX5969B

EP*

TDFN

(3mm × 3mm)

SS

.

CLS

10

2ECDET

PG

8

WAD

7

RTNV

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated Power MOSFET

ABSOLUTE MAXIMUM RATINGS

VDD to VSS ..........................................................-0.3V to +100V

DET, RTN, WAD, PG, 2EC to V

CLS to VSS ..............................................................-0.3V to +6V

Maximum Current on CLS (100ms maximum) .................100mA

Continuous Power Dissipation (TA = +70NC) (Note 1)
10-Pin TDFN (derate 24.4mW/NC above +70NC)

Multilayer Board ........................................................1951mW

Note 1: Maximum power dissipation is obtained using JEDEC JESD51-5 and JESD51-7 specifications.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

SS .......................

-0.3V to +100V

ELECTRICAL CHARACTERISTICS

(VIN = (VDD - VSS) = 48V, R
unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3)

= 24.9kω, R

DET

= 615ω. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to V

CLS

Package Thermal Resistance (Note 2)

BJA .................................................................................4NC/W

BJC ................................................................................9NC/W

Operating Temperature Range .......................... -40NC to +85NC

Maximum Junction Temperature .....................................+150NC

Storage Temperature Range ............................ -65NC to +150NC

Soldering Temperature (reflow) .................................... +260NC

SS,

MAX5969A/MAX5969B

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DETECTION MODE

Input Offset Current I

Effective Differential Input
Resistance

CLASSIFICATION MODE

Classification Disable
Threshold

Classification Stability Time 0.2 ms

Classification Current I

TYPE 2 (802.3at) CLASSIFICATION MODE

Mark Event Threshold V

Hysteresis on Mark Event
Threshold

Mark Event Current I

Reset Event Threshold V

POWER MODE

VIN Supply Voltage Range 60 V
VIN Supply Current I

OFFSET

dR

V

TH,CLS

CLASS

THM

MARK

THR

Q

VIN = 1.4V to 10.1V (Note 4) 10

VIN = 1.4V up to 10.1V with 1V step,
V

= RTN = WAD = PG = 2EC (Note 5)

DD

V

rising (Note 6) 22.0 22.8 23.6 V

IN

Class 0, R

=

Class 1, R
Class 2, R
Class 3, R
Class 4, R
Class 5, R

DD

VIN = 12.5V to

20.5V, V
RTN = WAD =
PG = 2EC

VIN falling 10.1 10.7 11.6 V

VIN falling to enter mark event, 5.2V P V

P 10.1V

VIN falling 2.8 4 5.2 V

Measured at V

DD

CLS

CLS

CLS

CLS

CLS

CLS

= 619I
= 117I
= 66.5I
= 43.7I
= 30.9I
= 21.3I

23.95 25.00 25.5

0 3.96

9.12 11.88

17.2 19.8

26.3 29.7

36.4 43.6

52.7 63.3

0.84 V

IN

0.25 0.85 mA

0.27 0.55 mA

FA

kI

mA

2 ______________________________________________________________________________________

IEEE 802.3af/at-Compliant, Powered Device Interface

Controllers with Integrated Power MOSFET

ELECTRICAL CHARACTERISTICS (continued)

(VIN = (VDD - VSS) = 48V, R
unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VIN Turn-On Voltage V

VIN Turn-Off Voltage V

VIN Turn-On/-Off Hysteresis
(Note 7)

VIN Deglitch Time t

Inrush to Operating Mode
Delay

Isolation Power MOSFET
On-Resistance

RTN Leakage Current I

CURRENT LIMIT

Inrush Current Limit I

Current Limit During Normal
Operation

Foldback Threshold V

LOGIC

WAD Detection Threshold V

WAD Detection Threshold
Hysteresis

WAD Input Current I

2EC Sink Current

2EC Off-Leakage Current

PG Sink Current

PG Off-Leakage Current VPG = 48V 1

THERMAL SHUTDOWN

Thermal-Shutdown Threshold T
Thermal-Shutdown Hysteresis TJ falling 28

= 24.9kω, R

DET

V

CLS

ON

OFF

HYST_UVLO

OFF_DLY

t

DELAY

R

ON_ISO

RTN_LKG

INRUSH

I

LIM

WAD-REF

WAD-LKG

SD

= 615ω. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to V

VIN rising

VIN falling 30 V
MAX5969A 4.2
MAX5969B 7.3
VIN falling from 40V to 20V (Note 8) 30 120

t

= minimum PG current pulse width

DELAY

after entering into power mode

I

= 600mA

RTN

V

= 12.5V to 30V 10

RTN

During initial turn-on period,
V

= 1.5V

RTN

After inrush completed,
V

= 1V

RTN

(Note 9) 13 16.5 V

RTN

V

rising, VIN = 14V to 48V (referenced

WAD

to RTN)

V

falling, V

WAD

unconnected

V

= 10V (referenced to RTN) 3.5

WAD

V

= 3.5V (referenced to RTN), VSS

2EC

unconnected

V

= 48V

2EC

V

= 1.5V, V

RTN

period

TJ rising +140

MAX5969A 34.3 35.4 36.6

MAX5969B 37.2 38.6 40

80 96 112 ms

TJ = +25NC

TJ = +125NC

90 135 180 mA

720 800 880 mA

8 9 10

= 0V, VSS

RTN

1 1.5 2.25 mA

= 0.8V, during inrush

PG

125 230 375

0.5 0.7

0.65 1

0.8

0.725

V

V

Fs

ITJ = +85NC

FA

V

FA

1

FA

FA

FA

NC
NC

MAX5969A/MAX5969B

SS,

_______________________________________________________________________________________ 3

IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated Power MOSFET

ELECTRICAL CHARACTERISTICS (continued)

(VIN = (VDD - VSS) = 48V, R
unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3)

Note 3: All devices are 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design.
Note 4: The input offset current is illustrated in Figure 1.
Note 5: Effective differential input resistance is defined as the differential resistance between VDD and VSS. See Figure 1.
Note 6: Classification current is turned off whenever the device is in power mode.
Note 7: UVLO hysteresis is guaranteed by design, not production tested.
Note 8: A 20V glitch on input voltage that takes VDD below VON shorter than or equal to t

MAX5969B to exit power-on mode.

Note 9: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an overload

condition across VDD and RTN.

I

IN

(V

INi + 1

dRi x

(I

INi + 1

I

x I

OFFSET

MAX5969A/MAX5969B

I

INi + 1

I

INi

INi

V

INi

­dR

= 24.9kω, R

DET

- V

)

INi

= 1V

- I

)

(I

INi

i

INi + 1

= 615ω. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to V

CLS

OFF_DLY

- I

)

INi

dR

i

does not cause the MAX5969A/

SS,

I

OFFSET

1VV

INi

V

INi + 1

V

IN

Figure 1. Effective Differential Input Resistance/Offset Current

4 ______________________________________________________________________________________

IEEE 802.3af/at-Compliant, Powered Device Interface

Controllers with Integrated Power MOSFET

Typical Operating Characteristics

(VIN = (VDD - VSS) = 54V, R

= 24.9kω, R

DET

= 615ω. RTN, WAD, PG, and 2EC unconnected; all voltages are referenced to V

CLS

SS.

MAX5969A/MAX5969B

)

DETECTION CURRENT

vs. INPUT VOLTAGE

0.5
IIN = I

+ I

VDD

DET

= 24.9kI

DET

DD

VIN (V)

R
RTN = 2EC = PG = WAD = V

0.4

-40°C P TA P +85NC

0.3

(mA)

IN

I

0.2

0.1

0

0 10

CLASSIFICATION CURRENT vs.

INPUT VOLTAGE

70

V

CLASS 5

CLASS 4

CLASS 3

CLASS 2

CLASS 1

CLASS 0

(V)

60

50

40

(mA)

IN

I

30

20

10

0

0 30

SIGNATURE RESISTANCE

vs. INPUT VOLTAGE

26.0
IIN = I

+ I

VDD

R

MAX5969A toc01

8642

MAX5969A toc04

252015105

RTN = 2EC = PG = WAD = V

25.5

(kI)

25.0

SIGNATURE

TA = +25NC

R

24.5

24.0

0 10

DET

= 24.9kI

DET

CLASSIFICATION SETTLING TIME

TA = -40NC

TA = +85NC

VIN (V)

100µs/div

DD

8642

MAX5969A toc05

= 30.9I

R

CLS

MAX5969A toc02

V

IN

10V/div

I

IN

0A

200mA/div

V

CLS

1V/div

0V

4

2

0

-2

INPUT OFFSET CURRENT (µA)

-4

2.0

1.6

1.2

(mA)

2EC

I

0.8

0.4

0

INPUT OFFSET CURRENT

vs. INPUT VOLTAGE

TA = -40NC

TA = +25NC

0 10

TA = +85NC

8642

VIN (V)

2EC SINK CURRENT vs. 2EC VOLTAGE

TA = -40NC

VSS UNCONNECTED
V
V

0 60

TA = +25NC

TA = +85NC

REFERENCED TO RTN

2EC

= 14V

WAD

V

(V)

2EC

5040302010

MAX5969A toc03

MAX5969A toc06

PG SINK CURRENT vs. PG VOLTAGE

300

TA = -40NC

250

200

(µA)

PG

I

150

100

50

0 60

TA = +25NC

VPG (V)

_______________________________________________________________________________________ 5

TA = +85NC

5040302010

150

130

MAX5969A toc07

110

90

INRUSH CURRENT LIMIT (mA)

70

50

0 60

INRUSH CURRENT LIMIT

vs. RTN VOLTAGE

V

(V)

RTN

NORMAL OPERATION CURRENT LIMIT

vs. RTN VOLTAGE

900

800

MAX5969A toc08

5040302010

700

600

500

400

CURRENT LIMIT (mA)

300

200

100

0 60

V

(V)

RTN

MAX5969A toc09

504010 20 30

IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated Power MOSFET

Typical Operating Characteristics (continued)

(VIN = (VDD - VSS) = 54V, R

= 24.9kω, R

DET

= 615ω. RTN, WAD, PG, and 2EC unconnected; all voltages are referenced to V

CLS

SS.

)

INRUSH CONTROL WAVEFORM WITH

TYPE 2 CLASSIFICATION

USING TYPICAL APPLICATION CIRCUIT
2EC PULLED UP TO V

200

DD

µs/div

WITH 10kI

MAX5969A toc10

V
50V/div

0V

0V

I
100mA/div

0A

0V

2EC

V

RTN

50V/div

RTN

V

DD

50V/div

MAX5969A/MAX5969B

ENTERING POWER MODE WITH

TYPE 2 CLASSIFICATION

USING TYPICAL APPLICATION CIRCUIT

2EC PULLED UP TO V

20ms/div

WITH 10kI

DD

MAX5969A toc11

0V

0V

0A

0V

V

PG

10V/div0V

V

2EC

40V/div
V

RTN

50V/div

I

RTN

200mA/div

V

DD

50V/div

6 ______________________________________________________________________________________

IEEE 802.3af/at-Compliant, Powered Device Interface

Controllers with Integrated Power MOSFET

Pin Description

PIN NAME FUNCTION

1 VDD Positive Supply Input. Connect a 68nF (min) bypass capacitor between VDD and VSS.
2 DET
3 N.C. No Connection. Not internally connected.
4 I.C. Internally Connected. Leave unconnected.

5 V

6 RTN

7 WAD

8 PG

9

10 CLS

–– EP

SS

2EC

Detection Resistor Input. Connect a signature resistor (R

Negative Supply Input. VSS connects to the source of the integrated isolation n-channel power
MOSFET.

Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power
MOSFET. Connect RTN to the downstream DC-DC converter ground as shown in the Typical
Application Circuit.

Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment VDD - VSS crosses
the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V.
When a wall power adapter is present, the isolation n-channel power MOSFET turns off, 2EC current
sink turns on. Connect WAD directly to RTN when the wall power adapter or other auxiliary power
source is not used.

Open-Drain Power-Good Indicator Output. PG sinks 230FA to disable the downstream DC-DC converter
while turning on the hot-swap MOSFET switch until the hot-swap switch is fully on. PG current sink is
disabled during detection, classification, and in the steady-state power mode.

Active-Low 2-Event Classification Detect or Wall Adapter Detect Output. A 1.5mA current sink is
enabled at 2EC when a Type 2 PSE or a wall adapter is detected. When powered by a Type 2 PSE, the
2EC current sink is enabled and latched low after the isolation MOSFET is fully on until VIN drops below
the UVLO threshold. 2EC also asserts when a wall adapter supply, typically greater than 9V, is applied
between WAD and RTN. 2EC is not latched if asserted by WAD.

Classification Resistor Input. Connect a resistor (R
current. See the classification current specifications in the Electrical Characteristics table to find the resis-
tor value for a particular PD classification.

Exposed Pad. Do not use EP as an electrical connection to VSS. EP is internally connected to VSS
through a resistive path and must be connected to VSS externally. To optimize power dissipation, solder
the exposed pad to a large copper power plane.

CLS

= 24.9kI) from DET to VDD.

DET

) from CLS to VSS to set the desired classification

MAX5969A/MAX5969B

_______________________________________________________________________________________ 7

IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated Power MOSFET

Simplified Block Diagram

V

V

DD

22.8/22

V

DD

5V REGULATOR

5V

1.23V

D Q

SET

CLR

D QQSET

Q

CLR

EN CLS

DD

CLASSIFICATION

PSE 2

1.23V

2EC

V

DD

11.6V/4V

5V

46µA

MAX5969A/MAX5969B

DET

I

V

SS

SWITCH

11.6V/10.8V

V

DD

15V

ISOLATION

SWITCH

1.5mA

PG

VON/V

OFF

V

DD

THERMAL

SHUTDOWN

95ms

WAPD

R

HSON

4V

Q

S

= 38.6V/31V FOR MAX5969B

V

ON/VOFF

VON/V

= 35.4V/31V FOR MAX5969A

OFF

230µA

WAD

9V

RTN

K x I

SWITCH

I

REF

1/K

MUX

S

135mA

I0

I1

760mA

MAX5969A
MAX5969B

8 ______________________________________________________________________________________

IEEE 802.3af/at-Compliant, Powered Device Interface

Controllers with Integrated Power MOSFET

Typical Operating Circuit

2-EVENT

CLASSIFICATION

DETECTION

GND

RJ-45

AND

BRIDGE

RECTIFIER

R

DET

24.9kI

V

DD

2EC

IN+

PG

ENABLE

GND

MAX5969A/MAX5969B

-54V

SMAJ58A

68nF

R

CLS

DET

CLS

V

DC-DC

MAX5969A

WAD

CONVERTER

MAX5969B

24V/48V

BATTERY

SS

RTN

IN-

_______________________________________________________________________________________ 9

IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated Power MOSFET

Detailed Description

Operating Modes

Depending on the input voltage (V
MAX5969A/MAX5969B operate in four different modes:
PD detection, PD classification, mark event, and PD
power. The devices enter PD detection mode when the
input voltage is between 1.4V and 10.1V. The device
enters PD classification mode when the input voltage is
between 12.6V and 20V. The device enters PD power
mode once the input voltage exceeds VON.

Detection Mode (1.4V ≤ VIN ≤ 10.1V)

In detection mode, the PSE applies two voltages on VIN
in the range of 1.4V to 10.1V (1V step minimum) and
then records the current measurements at the two points.
The PSE then computes DV/DI to ensure the presence
of the 24.9kω signature resistor. Connect the signature
resistor (R

) from VDD to DET for proper signature

DET

detection. The MAX5969A/MAX5969B pull DET low in
detection mode. DET goes high impedance when the

MAX5969A/MAX5969B

input voltage exceeds 12.5V. In detection mode, most of
the MAX5969A/MAX5969B internal circuitry is off and the
offset current is less than 10µA.

If the voltage applied to the PD is reversed, install pro­tection diodes at the input terminal to prevent internal
damage to the MAX5969A/MAX5969B (see the Typical
Application Circuit). Since the PSE uses a slope tech­nique (DV/DI) to calculate the signature resistance, the
DC offset due to the protection diodes is subtracted and
does not affect the detection process.

= VDD - VSS), the

IN

Classification Mode (12.6V ≤ VIN ≤ 20V)

In the classification mode, the PSE classifies the PD
based on the power consumption required by the PD. This
allows the PSE to efficiently manage power distribution.
Class 0 to 5 is defined as shown in Table 1. (The IEEE

802.3af/at standard defines only Class 0 to 4 and Class 5
for any special requirement.) An external resistor (R

CLS

connected from CLS to VSS sets the classification current.

The PSE determines the class of a PD by applying a volt­age at the PD input and measuring the current sourced
out of the PSE. When the PSE applies a voltage between

12.6V and 20V, the MAX5969A/MAX5969B exhibit a cur­rent characteristic with a value shown in Table 1. The
PSE uses the classification current information to classify
the power requirement of the PD. The classification cur­rent includes the current drawn by R

and the supply

CLS

current of the MAX5969A/MAX5969B so the total current
drawn by the PD is within the IEEE 802.3af/at standard
figures. The classification current is turned off whenever
the device is in power mode.

2-Event Classification and Detection

During 2-event classification, a Type 2 PSE probes PD
for classification twice. In the first classification event,
the PSE presents an input voltage between 12.6V and

20.5V and the MAX5969A/MAX5969B present the pro­grammed load I

. The PSE then drops the probing

CLASS

voltage below the mark event threshold of 10.1V and
the MAX5969A/MAX5969B present the mark current
(I

). This sequence is repeated one more time.

MARK

)

Table 1. Setting Classification Current

MAXIMUM

CLASS

0 0.44 to 12.95 615 12.6 to 20 0 4 0 5
1 0.44 to 3.94 117 12.6 to 20 9 12 8 13
2 3.84 to 6.49 66.5 12.6 to 20 17 20 16 21
3 6.49 to 12.95 43.7 12.6 to 20 26 30 25 31
4 12.95 to 25.5 30.9 12.6 to 20 36 44 35 45
5 > 25.5 21.3 12.6 to 20 54 64 — —

*VIN is measured across the MAX5969A/MAX5969B input VDD to VSS.

10 _____________________________________________________________________________________

POWER USED

BY PD

(W)

R

CLS

(I)

VIN*

(V)

CLASS CURRENT SEEN AT

VIN (mA)

MIN MAX MIN MAX

IEEE 802.3at PSE

CLASSIFICATION CURRENT

SPECIFICATION (mA)

IEEE 802.3af/at-Compliant, Powered Device Interface

Controllers with Integrated Power MOSFET

When the MAX5969A/MAX5969B are powered by a Type 2
PSE, the 2-event identification output 2EC asserts low
after the internal isolation n-channel MOSFET is fully
turned on. 2EC current sink is turned off when VDD goes
below the UVLO threshold (V
VDD goes above the UVLO threshold (VON), unless VDD
goes below V
PSE detection flag.

Alternatively, the 2EC output also serves as a wall adapt­er detection output when the MAX5969A/MAX5969B are
powered by an external wall power adapter. See the Wall
Power Adapter Detection and Operation section for more
information.

The MAX5969A/MAX5969B enter power mode when VIN
rises above the undervoltage lockout threshold (VON).
When VIN rises above VON, the MAX5969A/MAX5969B
turn on the internal n-channel isolation MOSFET to con­nect VSS to RTN with inrush current limit internally set
to 135mA (typ). The isolation MOSFET is fully turned on
when the voltage at RTN is near VSS and the inrush cur­rent is reduced below the inrush limit. Once the isolation
MOSFET is fully turned on, the MAX5969A/MAX5969B
change the current limit to 800mA. The open-drain
power-good output (PG) remains low for a minimum of
t
downstream DC-DC converter disabled during inrush.

until the power MOSFET fully turns on to keep the

DELAY

to reset the latched output of the Type 2

THR

) and turns on when

OFF

Power Mode (Wake Mode)

Undervoltage Lockout

The MAX5969A/MAX5969B operate up to a 60V sup­ply voltage with a turn-on UVLO threshold (VON) at

35.4V/38.6V and a turn-off UVLO threshold (V
When the input voltage is above VON, the MAX5969A/
MAX5969B enter power mode and the internal MOSFET
is turned on. When the input voltage goes below V
more than t

OFF_DLY

, the MOSFET turns off.

OFF

) at 31V.

for

OFF

An open-drain output (PG) is used to allow disabling
downstream DC-DC converter until the n-channel isola­tion MOSFET is fully turned on. PG is pulled low to VSS
for a period of t
MOSFET is fully turned on. The PG is also pulled low
when coming out of thermal shutdown.

and until the internal isolation

DELAY

Thermal-Shutdown Protection

The MAX5969A/MAX5969B include thermal protection
from excessive heating. If the junction temperature
exceeds the thermal-shutdown threshold of +140NC,
the MAX5969A/MAX5969B turn off the internal power
MOSFET and 2EC current sink. When the junction tem­perature falls below +112NC, the devices enter inrush
mode and then return to power mode. Inrush mode
ensures the downstream DC-DC converter is turned off
as the internal power MOSFET is turned on.

Wall Power Adapter Detection

For applications where an auxiliary power source such
as a wall power adapter is used to power the PD,
the MAX5969A/MAX5969B feature wall power adapter
detection. Once the input voltage (VDD - VSS) exceeds
the mark event threshold, the MAX5969A/MAX5969B
enable wall adapter detection. The wall power adapt­er is connected from WAD to RTN. The MAX5969A/
MAX5969B detect the wall power adapter when the
voltage from WAD to RTN is greater than 9V. When a
wall power adapter is detected, the internal n-channel
isolation MOSFET turns off, 2EC current sink turns on,
and classification current is disabled if VIN is in the clas­sification range.

Power-Good Output

and Operation

MAX5969A/MAX5969B

______________________________________________________________________________________ 11

IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated Power MOSFET

Applications Information

Operation with 12V Adapter

Layout Procedure

Careful PCB layout is critical to achieve high efficiency
and low EMI. Follow these layout guidelines for optimum
performance:

1) Place the input capacitor, classification resistor, and
transient voltage suppressor as close as possible to
the MAX5969A/MAX5969B.

MAX5969A/MAX5969B

RJ-45

AND

BRIDGE

RECTIFIER

GND

R

DET

24.9kI

V

DD

2EC

2) Use large SMT component pads for power dissipat­ing devices such as the MAX5969A/MAX5969B and
the external diodes.

3) Use short and wide traces for high-power paths.

4) Use the MAX5969 Evaluation Kit layout as a refer­ence.

2-EVENT

CLASSIFICATION

(ASSERTED ON)

IN+

PG

ENABLE

GND

DET

-54V

SMAJ58A

68nF

R

CLS

CLS

V

MAX5969A
MAX5969B

SS

WAD

BATTERY

RTN

Figure 2. Typical Configuration When Using a 12V Wall Power Adapter

DC-DC

CONVERTER

12V

IN-

THIS CIRCUIT ACHIEVES

PROPER 2EC LOGIC WHEN

BATTERY IS < 12.5V

12 _____________________________________________________________________________________

IEEE 802.3af/at-Compliant, Powered Device Interface

Controllers with Integrated Power MOSFET

Typical Application Circuit

ISOLATED 2-EVENT

CLASSIFICATION

OUTPUT

GND

V

AC

GND

24.9kI

V

DD

2EC

PG

PG

MAX5969A/MAX5969B

V

AC

-54V

1.37MI

PG

4.99kI

GND

68nF

SMAJ58A

33kI

51.5kI

ULVO/EN IN

UFLG

FB

MAX15000

10kI

COMP

CS

CS

43.7I

DET

CLS

V

SS

0.1µF

0.1µF

1kI

V

CC

NDRV

GND

RT

MAX5969A

WAD

MAX5969B

24/48V

BATTERY

RTN

249I

4.7µF

RTN

GND

22µF

CS

649I

330pF

619I

0.75I

RTN

0.1µF

18.1kI

V

CC

22.1I

4.99kI

0.1µF

V

CC

RTN

ISOLATED +5.3V/2A

ISOLATED RTN

8.2nF

8.06kI

1kI 100pF

33nF

8.06kI

1kI

RTN

2.2nF

ISOLATED RTN

2.49kI

______________________________________________________________________________________ 13

IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated Power MOSFET

Chip Information

PROCESS: BiCMOS

MAX5969A/MAX5969B

Package Information

For the latest package outline information and land pat­terns, go to www.maxim-ic.com/packages. Note that
a “+”, “#”, or “-” in the package code indicates RoHS
status only. Package drawings may show a different suf­fix character, but the drawing pertains to the package
regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

10 TDFN-EP T1033+1

21-0137

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.

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