The MAX5969A/MAX5969B provide a complete interface
for a powered device (PD) to comply with the IEEE®
802.3af/at standard in a power-over-Ethernet (PoE) system. The MAX5969A/MAX5969B provide the PD with a
detection signature, classification signature, and an integrated isolation power switch with inrush current control.
During the inrush period, the MAX5969A/MAX5969B limit
the current to less than 180mA before switching to the
higher current limit (720mA to 880mA) when the isolation
power MOSFET is fully enhanced. The devices feature
an input UVLO with wide hysteresis and long deglitch
time to compensate for twisted-pair cable resistive drop
and to assure glitch-free transition during power-on/-off
conditions. The MAX5969A/MAX5969B can withstand up
to 100V at the input.
The MAX5969A/MAX5969B support a 2-event classification method as specified in the IEEE 802.3at standard
and provide a signal to indicate when probed by Type 2
power-sourcing equipment (PSE). The devices detect
the presence of a wall adapter power-source connection and allow a smooth switchover from the PoE power
source to the wall power adapter.
The MAX5969A/MAX5969B also provide a power-good
(PG) signal, two-step current limit and foldback, overtemperature protection, and di/dt limit.
The MAX5969A/MAX5969B are available in a space-saving, 10-pin, 3mm x 3mm, TDFN power package. These
devices are rated over the -40NC to +85NC extended
temperature range.
Features
SIEEE 802.3af/at Compliant
S2-Event Classification
SSimplified Wall Adapter Interface
SPoE Classification 0 to 5
S100V Input Absolute Maximum Rating
SInrush Current Limit of 180mA Maximum
SCurrent Limit During Normal Operation Between
720mA and 880mA
SCurrent Limit and Foldback
SLegacy UVLO at 36V (MAX5969A)
SIEEE 802.3af/at-Compliant, 40V UVLO (MAX5969B)
SOvertemperature Protection
SThermally Enhanced, 3mm x 3mm, 10-Pin TDFN
Ordering Information
PARTTEMP RANGE
MAX5969AETB+
MAX5969BETB+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
-40NC to +85NC
-40NC to +85NC
PIN-
PACKAGE
10 TDFN-EP*35.4
10 TDFN-EP*38.6
UVLO
THRESHOLD
(V)
Pin Configuration
MAX5969A/MAX5969B
Applications
TOP VIEW
IEEE 802.3af/at Powered Devices
IP Phones, Wireless Access Nodes, IP Security
Cameras
WiMAXK Base Station
IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.
Note 1: Maximum power dissipation is obtained using JEDEC JESD51-5 and JESD51-7 specifications.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
SS .......................
-0.3V to +100V
ELECTRICAL CHARACTERISTICS
(VIN = (VDD - VSS) = 48V, R
unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3)
= 24.9kω, R
DET
= 615ω. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to V
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated Power MOSFET
ELECTRICAL CHARACTERISTICS (continued)
(VIN = (VDD - VSS) = 48V, R
unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3)
Note 3: All devices are 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design.
Note 4: The input offset current is illustrated in Figure 1.
Note 5: Effective differential input resistance is defined as the differential resistance between VDD and VSS. See Figure 1.
Note 6: Classification current is turned off whenever the device is in power mode.
Note 7: UVLO hysteresis is guaranteed by design, not production tested.
Note 8: A 20V glitch on input voltage that takes VDD below VON shorter than or equal to t
MAX5969B to exit power-on mode.
Note 9: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an overload
condition across VDD and RTN.
I
IN
(V
INi + 1
dRi x
(I
INi + 1
I
x I
OFFSET
MAX5969A/MAX5969B
I
INi + 1
I
INi
INi
V
INi
dR
= 24.9kω, R
DET
- V
)
INi
= 1V
- I
)
(I
INi
i
INi + 1
= 615ω. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to V
CLS
OFF_DLY
- I
)
INi
dR
i
does not cause the MAX5969A/
SS,
I
OFFSET
1VV
INi
V
INi + 1
V
IN
Figure 1. Effective Differential Input Resistance/Offset Current