The MAX5965A/MAX5965B are quad, monolithic, -48V
power controllers designed for use in IEEE
®
802.3af-compliant/pre-IEEE 802.3at-compatible power-sourcing equipment (PSE). These devices provide powered device (PD)
discovery, classification, current limit, DC and AC load disconnect detections in compliance with the IEEE 802.3af
standard. The MAX5965A/MAX5965B are pin compatible
with the MAX5952/MAX5945/LTC4258/LTC4259A PSE
controllers and provide additional features.
The MAX5965A/MAX5965B feature a high-power mode
that provides up to 45W per port. The MAX5965A/
MAX5965B provide new Class 5 and 2-event classification (Class 6) for detection and classification of highpower PDs. The MAX5965A/MAX5965B provide
instantaneous readout of each port current through the
I
2
C interface. The MAX5965A/MAX5965B also provide
high-capacitance detection for legacy PDs.
These devices feature an I
2
C-compatible, 3-wire serial interface, and are fully software configurable and programmable.
The class-overcurrent detection function enables system
power management to detect if a PD draws more than the
allowable current. The MAX5965A/MAX5965B’s extensive
programmability enhances system flexibility, enables field
diagnosis, and allows for uses in other applications.
The MAX5965A/MAX5965B provide four operating modes
to suit different system requirements. Auto mode allows
the devices to operate automatically without any software
supervision. Semi-automatic mode automatically detects
and classifies a device connected to a port after initial
software activation, but does not power up that port until
instructed to by software. Manual mode allows total software control of the device and is useful for system diagnostics. Shutdown mode terminates all activities and
securely turns off power to the ports.
The MAX5965A/MAX5965B provide input undervoltage
lockout (UVLO), input undervoltage detection, a loadstability safety check during detection, input overvoltage lockout, overtemperature detection, output voltage
slew-rate limit during startup, power-good status, and
fault status. The MAX5965A/MAX5965B’s programmability includes startup timeout, overcurrent timeout, and
load-disconnect detection timeout.
The MAX5965A/MAX5965B are available in a 36-pin SSOP
package and are rated for both extended (-40°C to +85°C)
and upper commercial (0°C to +85°C) temperature ranges.
Applications
Power-Sourcing Equipment (PSE)
Switches/Routers
Midspan Power Injectors
= +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at
V
AGND
= +48V, V
DGND
= +48V, VDD= (V
DGND
+ 3.3V), TA= +25°C. Currents are positive when entering the pin and negative other-
wise.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(Voltages referenced to VEE, unless otherwise noted.)
AGND, DGND, DET_, V
DD
, RESET, A3–A0, SHD_, OSC,
SCL, SDAIN, AUTO .............................................-0.3V to +80V
OUT_........................................................-12V to (AGND + 0.3V)
GATE_ (internally clamped) (Note 1) ..................-0.3V to +11.4V
SENSE_ ..................................................................-0.3V to +24V
V
DD
, RESET, MIDSPAN, A3–A0, SHD_, OSC, SCL,
SDAIN and AUTO to DGND ..................................-0.3V to +7V
INT and SDAOUT to DGND....................................-0.3V to +12V
Maximum Current into INT, SDAOUT, DET_ .......................80mA
= +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at
V
AGND
= +48V, V
DGND
= +48V, VDD= (V
DGND
+ 3.3V), TA= +25°C. Currents are positive when entering the pin and negative other-
wise.) (Note 2)
Note 2: Limits to TA= -40°C are guaranteed by design.
Note 3: Default values. The charge/discharge currents are programmable through the serial interface (see the
Register Map and
Description
section).
Note 4: Default values. The current-limit thresholds are programmed through the I2C-compatible serial interface (see the
Register
Map and Description
section).
Note 5: Functional test is performed over thermal shutdown entering test mode.
Note 6: This is the default value. Threshold can be programmed through serial interface R23h[2:0].
Note 7: AC disconnect works only if (V
DD
- V
DGND
) ≥ 3V and DGND is connected to AGND.
Note 8:t
DISC
can also be programmed through the serial interface (R16H) (see the
Register Map and Description
section).
Note 9: R
D
= (V
OUT_2
- V
OUT_1
)/(I
DET_2
- I
DET_1
). V
OUT_1
, V
OUT_2
, I
DET_2
, and I
DET_1
represent the voltage at OUT_ and the cur-
rent at DET_ during phase 1 and 2 of the detection.
Note 10: Default values. The startup and fault times can also be programmed through the I
2
C serial interface (see the
Register Map
and Description
section).
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Differential NonlinearityDNL0.21.5LSB
Gain Error3%
ADC Absolute AccuracyV
TIMING CHARACTERISTICS(For 2-Wire Fast Mode)
Serial-Clock Frequencyf
Bus Free Time Between a
STOP and START Condition
Hold Time for a START
Condition
Low Period of the SCL Clockt
High Period of the SCL Clockt
Setup Time for a Repeated
START Condition (Sr)
Data Hold Timet
Data in Setup Timet
Rise Time of Both SDA and
SCL Signals, Receiving
Fall Time of SDA Transmittingt
Setup Time for STOP Conditiont
Capacitive Load for Each Bus
Line
Pulse Width of Spike
Suppressed
t
HD, STA
t
SU, STA
HD, DAT
SU, DAT
SU, STO
= 300mV295300305LSB
SENSE
SCL
t
BUF
LOW
HIGH
t
R
F
C
B
t
SP
1.2µs
0.6µs
1.2µs
0.6µs
0.6µs
100300ns
100ns
20 +
0.1C
B
20 +
0.1C
B
0.6µs
400kHz
300ns
300ns
400pF
50ns
SENSE TRIP VOLTAGE
vs. INPUT VOLTAGE
MAX5965A toc09
V
AGND
- VEE (V)
SENSE TRIP VOLTAGE (mV)
565236404448
185.5
186.0
186.5
187.0
187.5
188.0
188.5
189.0
185.0
3260
MAX5965A/MAX5965B
High-Power, Quad, Monolithic, PSE Controllers
for Power over Ethernet
= +25°C, all registers = default setting, unless otherwise noted.)
Pin Description
DETECTION WITH INVALID PD (OPEN CIRCUIT,
USING TYPICAL OPERATING CIRCUIT 2)
MAX5965A toc28
STARTUP WITH DIFFERENT
PD CLASSES
MAX5965A toc29
(AGND - V
0V
0A
V
EE
40ms/div
5V/div
I
OUT
1mA/div
V
GATE_
10V/div
OUT
)
2-EVENT CLASSIFICATION
0V
0A
V
EE
WITH A CLASS 4 PD
MAX5965A toc30
V
AGND
5V/div
I
OUT
20mA/div
V
GATE
10V/div
V
- V
AGND
OUT
5V/div
0V
CLASS 5
CLASS 4
CLASS 3
CLASS 2
CLASS 1
- V
OUT
I
OUT
20mA/div
0A
PINNAMEFUNCTION
Hardware Reset. Pull RESET low for at least 300µs to reset the device. All internal registers reset to their
1RESET
2MIDSPAN
3INT
4SCLSerial Interface Clock Line Input
5SDAOUT
default value. The address (A0–A3), and AUTO and MIDSPAN input-logic levels latch on during low-tohigh transition of RESET. RESET is internally pulled up to V
with a 50kΩ resistor.
DD
Midspan Mode Input. An internal 50kΩ pulldown resistor to DGND sets the default mode to endpoint PSE
operation (power-over-signal pairs). Pull MIDSPAN to V
to set midspan operation. The MIDSPAN value
DIG
latches after the device is powered up or reset (see the PD Detection section).
Open-Drain Interrupt Output. INT goes low whenever a fault condition exists. Reset the fault condition
using software or by pulling RESET low (see the Interrupt section for more information about interrupt
management).
Serial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the Typical OperatingCircuits). Connect SDAOUT to SDAIN if using a 2-wire, I
21AGNDAnalog Ground. Connect to the high-side analog supply.
22, 25,
29, 32
23, 26,
30, 33
DD
SENSE4,
SENSE3,
SENSE2,
SENSE1
GATE4,
GATE3,
GATE2,
GATE1
Serial Interface Input Data Line. Connect the data line optocoupler output to SDAIN (see the TypicalOperating Circuits). Connect SDAIN to SDAOUT if using a 2-wire, I
Address Bits. A3–A0 form the lower part of the device’s address. Address inputs default high with an
internal 50kΩ pullup resistor to V
its UVLO threshold or after a reset. The 3 MSBs of the address are set to 010.
Detection/Classification Voltage Outputs. Use DET1 to set the detection and classification probe voltages
on port 1. Use DET1 for the AC voltage sensing of port 1 when using the AC disconnect scheme (see the
Typical Operating Circuits).
Positive Digital Supply. Connect to a digital power supply (reference to DGND).
Port Shutdown Inputs. Pull SHD_ low to turn off the external FET on port_. Internally pulled up to V
a 50kΩ resistor.
MOSFET Source Current-Sense Negative Inputs. Connect to the source of the power MOSFET and
connect a current-sense resistor between SENSE_ and V
Port_ MOSFET Gate Drivers. Connect GATE_ to the gate of the external MOSFET (see the TypicalOperating Circuits).
. The address values latch when VDD or VEE ramps up and exceeds
DD
2
C-compatible system.
with
DD
(see the Typical Operating Circuits).
EE
24, 27,
31, 34
OUT4, OUT3,
OUT2, OUT1
28V
35AUTO
36OSC
MOSFET Drain-Output Voltage Senses. Connect OUT_ to the power MOSFET drain through a resistor
(100Ω to 100kΩ). The low leakage at OUT_ limits the drop across the resistor to less than 100mV (see the
Typical Operating Circuits).
EE
Low-Side Analog Supply Input. Connect the low-side analog supply to VEE (-48V). Bypass with a 1µF
capacitor between AGND and V
Auto or Shutdown Mode Input. Force AUTO high to enter auto mode after a reset or power-up. Drive low
to put the MAX5965A/MAX5965B into shutdown mode. In shutdown mode, software controls the
operational modes of the MAX5965A/MAX5965B. A 50kΩ internal pulldown resistor defaults to AUTO low.
AUTO latches when V
Software commands can take the MAX5965A/MAX5965B out of AUTO while AUTO is high.
Oscillator Input. AC-disconnect detection function uses OSC. Connect a 100Hz ±10%, 2V
offset sine wave to OSC. If the oscillator positive peak falls below the OSC_FAIL threshold of 2V, the ports
that have the AC function enabled shut down and are not allowed to power-up. When not using the ACdisconnect detection function, leave OSC unconnected.
or VEE ramps up and exceeds its UVLO threshold or when the device resets.
DD
EE
.
±5%, +1.2V
P-P
MAX5965A/MAX5965B
High-Power, Quad, Monolithic, PSE Controllers
for Power over Ethernet
The MAX5965A/MAX5965B are quad -48V power controllers designed for use in IEEE 802.3af-compliant/preIEEE 802.3at-compatible PSE. The devices provide PD
discovery, classification, current limit, DC and AC load
disconnect detections in compliance with the IEEE 802.3af
standard. The MAX5965A/MAX5965B are pin compatible
with the MAX5952/MAX5945/LTC4258/LTC4259A PSE
controllers and provides additional features.
The MAX5965A/MAX5965B feature a high-power mode,
which provides up to 45W per port. The devices allow
the user to program the current-limit and overcurrent
thresholds up to 2.5 times the default thresholds. The
MAX5965A/MAX5965B can also be programmed to
decrease the current-limit and overcurrent threshold by
15% for high operating voltage conditions to keep the
output power constant.
The MAX5965A/MAX5965B provide new Class 5 and 2event classification (Class 6) for detection and classification of high-power PDs. The MAX5965A/MAX5965B
provide instantaneous readout of each port current
through the I2C interface. The MAX5965A/MAX5965B
also provide high-capacitance detection for legacy PDs.
The MAX5965A/MAX5965B are fully software configurable and programmable through an I2C-compatible,
3-wire serial interface with 49 registers. The class-overcurrent detection function enables system power management to detect if a PD draws more than the
allowable current. The MAX5965A/MAX5965B’s extensive programmability enhances system flexibility,
enables field diagnosis, and allows for uses in other
applications.
The MAX5965A/MAX5965B provide four operating
modes to suit different system requirements. Auto mode
allows the device to operate automatically without any
software supervision. Semi-auto mode automatically
detects and classifies a device connected to a port
after initial software activation but does not power up
that port until instructed to by software. Manual mode
allows total software control of the device and is useful
for system diagnostics. Shutdown mode terminates all
activities and securely turns off power to the ports.
The MAX5965A/MAX5965B provide input undervoltage
lockout, input undervoltage detection, a load-stability
safety check during detection, input overvoltage lockout,
overtemperature detection, output voltage slew-rate limit
during startup, power-good, and fault status. The
MAX5965A/MAX5965B’s programmability includes startup timeout, overcurrent timeout, and load-disconnect
detection timeout.
The MAX5965A/MAX5965B communicate with the system microcontroller through an I
2
C-compatible interface. The MAX5965A/MAX5965B feature separate input
and output data lines (SDAIN and SDAOUT) for use
with optocoupler isolation. As slave devices, the
MAX5965A/MAX5965B include four address inputs
allowing 16 unique addresses. A separate INT output
and four independent shutdown inputs (SHD_) provide
fast response from a fault to port shutdown between
the MAX5965A/MAX5965B and the microcontroller. A
RESET input allows hardware reset of the device.
Reset
Reset is a condition the MAX5965A/MAX5965B enter
after any of the following conditions:
1) After power-up (VEEand VDDrise above their
UVLO thresholds).
2) Hardware reset. The RESET input is driven low and
back high again any time after power-up.
3) Software reset. Writing a 1 into R1Ah[4] any time
after power-up.
4) Thermal shutdown.
During a reset, the MAX5965A/MAX5965B reset their
register map to the reset state as shown in Table 37
and latch in the state of AUTO (pin 35) and MIDSPAN
(pin 2). During normal operation, change at the AUTO
and MIDSPAN input is ignored. While the condition that
caused the reset persists (i.e. high temperature, RESET
input low, or UVLO conditions) the MAX5965A/
MAX5965B do not acknowledge any addressing from
the serial interface.
Port Reset (R1Ah[3:0])
Set high anytime during normal operation to turn off
power and clear the events and status registers of the
corresponding port. Port reset only resets the events
and status registers.
Midspan Mode
In midspan mode, the device adopts cadence timing
during the detection phase. When cadence timing is
enabled and a failed detection occurs, the port waits
between 2s and 2.4s before attempting to detect again.
Midspan mode is activated by setting R11[1] high. The
status of the MIDSPAN pin is written to R11[1] during
power-up or after a reset. MIDSPAN is internally pulled
low by a 50kΩ resistor.
MAX5965A/MAX5965B
High-Power, Quad, Monolithic, PSE Controllers
for Power over Ethernet
The MAX5965A/MAX5965B contain four independent,
but identical state machines to provide reliable and realtime control of the four network ports. Each state
machine has four operating modes: auto mode, semiauto mode, manual, and shutdown. Auto mode allows
the device to operate automatically without any software
supervision. Semi-auto mode, upon request, continuously detects and classifies a device connected to a port
but does not power up that port until instructed by software. Manual mode allows total software control of the
device and is useful in system diagnostics. Shutdown
mode terminates all activities and securely turns off
power to the ports.
Switching between auto, semi, or manual mode does
not interfere with the operation of the port. When the
port is set into shutdown mode, all the port operations
are immediately stopped and the port remains idle until
shutdown is exited.
Automatic (Auto) Mode
Enter automatic (auto) mode by forcing the AUTO input
high prior to a reset, or by setting R12h[P_M1,P_M0] to
[1,1] during normal operation (see Tables 16a and
16b). In auto mode, the MAX5965A/MAX5965B performs detection, classification, and power up the port
automatically once a valid PD is detected at the port. If
a valid PD is not connected at the port, the
MAX5965A/MAX5965B repeat the detection routine
continuously until a valid PD is connected.
Going into auto mode, the DET_EN and CLASS_EN bits
are set to high and stay high unless changed by software. Using software to set DET_EN and/or CLASS_EN
low causes the MAX5965A/MAX5965B to skip detection
and/or classification. As a protection, disabling the
detection routine in auto mode does not allow the corresponding port to power up, unless the DET_BY
(R23H[4]) is set to 1.
The AUTO status is latched into the register only during a reset. Any changes to the AUTO input after reset
are ignored.
Semi-Automatic (Semi-Auto) Mode
Enter semi-auto mode by setting R12h[P_M1,P_M0] to
[1,0] during normal operation (see Tables 16a and
16b). In semi-auto mode, the MAX5965A/MAX5965B,
upon request, perform detection and/or classification
repeatedly but do not power up the port(s), regardless
of the status of the port connection.
Setting R19h[PWR_ON_] (Table 22) high immediately
terminates detection/classification routines and turns on
power to the port(s).
R14h[DET_EN_, CLASS_EN_] default to low in semi-auto
mode. Use software to set R14h[DET_EN_, CLASS_EN_]
to high to start the detection and/or classification routines. R14h[DET_EN_, CLASS_EN_] are reset every time
the software commands a power off of the port (either
through reset or PWR_OFF). In any other case, the status
of the bits is left unchanged (including when the state
machine turns off the power because a load disconnect
or a fault condition is encountered).
Manual Mode
Enter manual mode by setting R12h[P_M1,P_M0] to [0,1]
during normal operation (see Tables 16a and 16b).
Manual mode allows the software to dictate any
sequence of operation. Write a 1 to both R14h[DET_EN_]
and R14h[CLASS_EN_] to start detection and classification operations, respectively, and in that priority order.
After execution, the command is cleared from the register(s). PWR_ON_ has highest priority. Setting PWR_ON_
high at any time causes the device to immediately enter
the powered mode. Setting DET_EN and CLASS_EN
high at the same time causes detection to be performed
first. Once in the powered state, the device ignores
DET_EN_ or CLASS_EN_ commands.
When switching to manual mode from another mode,
DET_EN_, CLASS_EN_ default to low. These bits
become pushbutton rather than configuration bits (i.e.,
writing ones to these bits while in manual mode commands the device to execute one cycle of detection
and/or classification. The bits are reset back to zeros at
the end of the execution).
Shutdown Mode
Enter shutdown mode by forcing the AUTO input low
prior to a reset, or by setting R12h[P_M1,P_M0] to [0,0]
during normal operation (see Tables 16a and 16b).
Putting the MAX5965A/MAX5965B into shutdown mode
immediately turns off power and halts all operations to
the corresponding port. The event and status bits of the
affected port(s) are also cleared. In shutdown mode, the
DET_EN_, CLASS_EN_, and PWR_ON_ commands are
ignored.
In shutdown mode, the serial interface operates normally.
PD Detection
When PD detection is activated, the MAX5965A/
MAX5965B probe the output for a valid PD. After each
detection cycle, the device sets the DET_END_ bit
R04h/05h[3:0] high and reports the detection results in
the status registers R0Ch[2:0], R0Dh[2:0], R0Eh[2:0],
and R0Fh[2:0]. The DET_END_ bit is reset to low when
read through R05h or after a port reset.
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