The MAX5945 quad network power controller is designed
for use in IEEE 802.3af-compliant power-sourcing equipment (PSE). The device provides power devices (PD) discovery, classification, current-limit, and both DC and AC
load disconnect detections. The MAX5945 can be used
in either endpoint PSE (LAN switches/routers) or midspan
PSE (power injector) applications. The MAX5945 is pin
and function compatible with LTC4259A.
The MAX5945 can operate autonomously or be controlled by software through an I2C*-compatible interface. Separate input and output data lines (SDAIN and
SDAOUT) allow usage with optocouplers. The
MAX5945 is a slave device. Its four address inputs
allow 16 unique MAX5945 addresses. A separate INT
output and four independent shutdown inputs (SHD_)
allow fast response from a fault to port shutdown. A
RESET input allows hardware reset of the device. A
special watchdog feature allows the hardware to gracefully take over control if the software crashes. A
cadence timing feature allows the MAX5945 to be used
in midspan systems.
The MAX5945 is fully software configurable and programmable. A class-overcurrent detection function enables
system power management to detect if a PD draws more
current than the allowable amount for its class. Other features are input under/overvoltage lockout, overtemperature protection, output-voltage slew-rate limit during
startup, power-good, and fault status. The MAX5945’s
programmability includes gate-charging current, currentlimit threshold, startup timeout, overcurrent timeout,
autorestart duty cycle, PD disconnect AC detection
threshold, and PD disconnect detection timeout.
The MAX5945 is available in a 36-pin SSOP package
and is rated for both extended (-40°C to +85°C) and
commercial (0°C to +70°C) temperature ranges.
Applications
Power-Sourcing Equipment (PSE)
Power-Over-LAN/Power-Over-Ethernet
Switches/Routers
Midspan Power Injectors
Features
♦ IEEE 802.3af Compliant
♦ Pin and Function Compatible with LTC4259A
♦ Controls Four Independent, -48V-Powered
Ethernet Ports in Either Endpoint or Midspan PSE
Applications
♦ Wide Digital Power Input, V
DIG
, Common-Mode
Range: VEEto (AGND + 7.7V)
♦ PD Violation of Class Current Protection
♦ PD Detection and Classification
♦ Provides Both DC and AC Load Removal
Detections
♦ I2C-Compatible, 3-Wire Serial Interface
♦ Fully Programmable and Configurable Operation
Through I
2
C Interface
♦ Current Foldback and Duty-Cycle-
Controlled/Programmable Current Limit
♦ Short-Circuit Protection with Fast Gate Pulldown
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(Voltages referenced to VEE, unless otherwise noted.)
AGND, DGND, DET_, V
DD
, RESET, A3, A2, A1, A0, SHD_,
OSC_IN, SCL, SDAIN, OUT_ and AUTO............-0.3V to +80V
GATE_ (internally clamped, Note 1)....................-0.3V to +11.4V
SENSE_ ..................................................................-0.3V to +24V
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(AGND = +32V to +60V, VEE= 0V, VDDto DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, V
DD
= (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
negative otherwise.)
Note 1: GATE_ is internally clamped to 11.4V above VEE. Driving GATE_ higher than 11.4V above VEEmay damage the device.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLIES
V
AGNDVAGND
V
Operating Voltage Range
Supply Currents
DGND
V
DD
I
EE
I
DIG
GATE DRIVER AND CLAMPING
GATE_ Pullup CurrentI
Weak GATE_ Pulldown CurrentI
Maximum Pulldown CurrentI
External Gate DriveV
PU
PDW
PDS
GS
CURRENT LIMIT
Current-Limit Clamp VoltageV
Overcurrent Threshold After
Startup
Foldback Initial OUT_ VoltageV
Foldback Final OUT_ VoltageV
SU_LIM
V
FLT_LIM
FLBK_ST
FLBK_END
- V
EE
VDD to V
VDD to V
DGND, VDGND
DGND, VDGND
OUT_ = VEE, SENSE_ = VEE, DET_ = AGND,
all logic inputs open, SCL = SDAIN = V
INT and SDAOUT open; measured at AGND
in power mode after GATE_ pullup
(AGND = +32V to +60V, VEE= 0V, VDDto DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, V
DD
= (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
negative otherwise.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Minimum Foldback CurrentLimit Threshold
V
TH_FBVOUT_
SENSE_ Input Bias CurrentV
SUPPLY MONITORS
VEE Undervoltage LockoutV
VEE Undervoltage-Lockout
Hysteresis
VEE OvervoltageV
VEE Overvoltage HysteresisV
VEE UndervoltageV
VDD OvervoltageV
VDD UndervoltageV
VDD Undervoltage LockoutV
VDD Undervoltage-Lockout
Hysteresis
Thermal-Shutdown ThresholdT
Thermal-Shutdown HysteresisT
EEUVLOVAGND
V
EEUVLOH
EE_OV
OVH
EE_UV
DD_OV(VDD
DD_UV(VDD
DDUVLO
V
DDHYS
SHD
SHDH
OUTPUT MONITOR
OUT_ Input CurrentI
Idle Pullup Current at OUT_I
PGOOD High ThresholdPG
PGOOD HysteresisPG
PGOOD Low-to-High Glitch
Filter
BOUT
DIS
TH
HYS
t
PGOOD
LOAD DISCONNECT
DC Load Disconnect
Threshold
V
DCTH
= V
SENSE_
AGND
= V
EE
- VEE, (V
- VEE) increasing2728.530V
AGND
64mV
-2µA
3V
(V
AGND
- VEE) > V
EE_OV
, V
increasing6162.564V
AGND
1V
(V
- VEE) < V
AGND
- V
- V
DGND)
DGND
> V
) < V
Device operates when (VDD - V
V
DDUVLO
, VDD increasing
EE_UV
DD_OV
DD_UV
, V
decreasing394041V
AGND
, VDD increasing3.573.713.90V
, VDD decreasing2.552.822.97V
) >
DGND
1.7V
120mV
Ports shut down and device resets if its junction
temperature exceeds this limit, temperature
+150°C
increasing
20°C
V
OUT
= V
, all modes2µA
AGND
OUT_ discharge current, detection and
classification off, port shutdown,
V
= V
OUT_
V
- VEE, OUT_ decreasing1.82.02.2V
OUT_
AGND
- 2.8V
200260µA
220mV
Minimum time PGOOD has to be high to set bit in
register 10h
(AGND = +32V to +60V, VEE= 0V, VDDto DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, V
DD
= (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
negative otherwise.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
AC Load Disconnect
Threshold (Note 4)
Oscillator Buffer GainA
OSC_IN Fail Threshold
(Note 5)
OSC_IN Input ResistanceZ
OSC_IN Input CapacitanceC
Load Disconnect Timert
I
ACTH
OSC
V
OS C _F AI L
OSC
OSC_IN
DISC
DETECTION
Detection Probe Voltage
(First Phase)
Detection Probe Voltage
(Second Phase)
Current-Limit ProtectionI
Short-Circuit ThresholdV
Open-Circuit ThresholdI
Resistor Detection WindowR
Resistor Rejection WindowR
V
DPH1VAGND
V
DPH2
DLIM
DCP
D_OPEN
DOK
DBAD
CLASSIFICATION
Classification Probe VoltageV
Current-Limit ProtectionI
Classification Current
Thresholds
CL
ClLIM
I
CL
DIGITAL INPUTS/OUTPUTS (REFERRED to DGND)
Digital Input LowV
Digital Input HighV
IL
IH
Current into DET_, ACD_EN_ bit = high,
OSC_IN = 2.2V
V
/ V
DET_
= 400nF
C
DET
Port will not power on if V
, ACD_EN_ bit = high,
OSC_IN
OSC_IN
< V
OSC_FAIL
and
ACD_EN_ bit = high
OSC_IN input impedance when all the ACD_EN_
are active
300325350µA
2.922.983.04V/V
1.81.92.1V
100kΩ
5pF
Time from V
to gate shutdown (Note 6)
< I
ACTH
- V
V
- V
AGND
phase
V
= V
DET_
current through DET_
If V
A GN D
- V
p hase a shor t ci r cui t to AG N D i s d etected
First point measurement current threshold for
open condition
(AGND = +32V to +60V, VEE= 0V, VDDto DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, V
DD
= (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
negative otherwise.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Internal Input Pullup/Pulldown
Resistor
Open-Drain Output Low
Voltage
Open-Drain LeakageI
TIMING
Startup Timet
Fault Timet
Port Turn-Off Timet
Detection Timet
Midspan Mode Detection
Delay
Classification Timet
V
Restart Timert
Watchdog Clock Periodt
TIMING CHARACTERISTICS for 2-WIRE FAST MODE (Figures 5 and 6)
Serial Clock Frequencyf
Bus Free Time Between a
STOP and a START Condition
Hold Time for Start Conditiont
Low Period of the SCL Clockt
High Period of the SCL Clockt
Turn-On Delayt
EEUVLO
R
DIN
V
OL
OL
START
FAULT
OFF
DET
t
DMID
CLASS
DLY
RESTART
WD
SCL
t
BUF
HD, STA
LOW
HIGH
Pullup (pulldown) resistor to VDD (DGND) to set
default level
I
= 15mA0.4V
SINK
Open-drain high impedance, VO = 3.3V2µA
Time during which a current limit set by V
is allowed, starts when the GATE_
is turned on (Note 8)
Maximum allowed time for an overcurrent
condition set by V
Minimum delay between any port turning off,
does not apply in the case of a reset
Maximum time allowed before detection
is completed
Time allowed for classification40ms
Time V
thresholds before the device operates
Ti m e a p or t has to w ai t
b efor e tur ni ng on after an
over cur r ent faul t,
RS TR_E N b i t = hi g h
Note 2: Default values. The charge/discharge currents are programmable through the serial interface (see the Register Map and
Description section).
Note 3: Default values. The current-limit thresholds are programmed through the I
2
C-compatible serial interface (see the Register
Map and Description section).
Note 4: This is the default value. Threshold can be programmed through serial interface R23h[2:0].
Note 5: AC disconnect works only if V
DD
- V
DGND
≥ 3V.
Note 6: t
DISC
can also be programmed through the serial interface (R29h) (see the Register Map and Description section).
Note 7: R
D
= (V
OUT_2
- V
OUT_1
) / (I
DET_2
- I
DET_1
). V
OUT_1
, V
OUT_2
, I
DET_2
and I
DET_1
represent the voltage at OUT_ and the current
at DET_ during phase 1 and 2 of the detection.
Note 8: Default values. The startup and fault times can also be programmed through the I
2
C serial interface (see the Register Map
and Description section).
Note 9: Guaranteed by design. Not subject to production testing.
ANALOG SUPPLY CURRENT
vs. INPUT VOLTAGE
MAX5945 toc01
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
5752474237
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
3.5
3262
MEASURED AT AGND
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX5945 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
3.0
-4085
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
MAX5945 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
-4085
Typical Operating Characteristics
(VEE= -48V, VDD= +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, R
SENSE
= 0.5Ω, all registers = default setting,
T
A
= +25°C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +32V to +60V, VEE= 0V, VDDto DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, V
DD
= (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
Hardware Reset. Pull RESET low for at least 300µs to reset the device. All internal registers reset to
1RESET
2MIDSPAN
3INT
4SCLSerial Interface Clock Line
5SDAOUT
6SDAIN
7–10A3, A2, A1, A0
11–14
15DGNDConnect to Digital Ground
16V
17–20
21AGNDAnalog Ground. Connect to the high-side analog supply.
22, 25,
29, 32
23, 26,
30, 33
24, 27,
31, 34
28V
35AUTO
36OSC_IN
DET1, DET2,
DET3, DET4
DD
SHD1, SHD2,
SHD3, SHD4
SENSE4, SENSE3,
SENSE2, SENSE1
GATE4, GATE3,
GATE2, GATE1
OUT4, OUT3,
OUT2, OUT1
EE
their default value. The address (A0–A3), and AUTO and MIDSPAN input logic levels latch on during
low-to-high transition of RESET. Internally pulled up to V
MIDSPAN Mode Input. An internal 50kΩ pulldown resistor to DGND sets the default mode to endpoint
PSE operation (power-over-signal pairs). Pull MIDSPAN TO V
MIDSPAN value latches after the IC is powered up or reset (see the PD Detection section).
Open-Drain Interrupt Output. INT goes low whenever a fault condition exists. Reset the fault condition
using software or by pulling RESET low (see the Interrupt section of the Detailed Description for more
information about interrupt management).
Serial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the TypicalApplication Circuit). Connect SDAOUT to SDAIN if using a 2-wire I
Serial Interface Input Data Line. Connect the data line optocoupler output SDAIN (see the TypicalApplication Circuit). Connect SDAIN to SDAOUT if using a 2-wire wire I
Address Bits. A3, A2, A1, and A0 form the lower part of the device’s address. Address inputs default
high with an internal 50kΩ pullup resistor to V
up and exceeds its UVLO threshold or after a reset. The 3 MSB bits of the address are set to 010.
Detection and Classification Voltage Outputs. Use DET1 to set the detection and classification probe
voltages on port 1. Use DET1 for the AC voltage sensing of port 1 when using the AC disconnect
scheme (see the Typical Application Circuit).
Positive Digital Supply. Connect to digital supply (referenced to DGND).
Port Shutdown Inputs. Pull SHD_ low to turn off the external FET on port_. Internally pulled up to V
with a 50kΩ resistor.
MOSFET Source Current-Sense Negative Inputs. Connect to the source of the power MOSFET and
connect a current-sense resistor between SENSE_ and V
Port_ MOSFET Gate Drivers. Connect GATE_ to the gate of the external FET (see the TypicalApplication Circuit).
MOSFET Drain-Output Voltage Senses. Connect OUT_ to the power MOSFET drain through a resistor
(100Ω to 100kΩ). The low leakage at OUT_ limits the drop across the resistor to less than 100mV
(see the Typical Application Circuit).
Low-Side Analog Supply Input. Connect the low-side analog supply to VEE (-48V). Bypass with a 1µF
capacitor between AGND and V
AUTO or SHUTDOWN Mode Input. Force high to enter AUTO mode after a reset or power-up. Drive
low to put the MAX5945 into SHUTDOWN mode. In SHUTDOWN mode, software controls the
operational modes of the MAX5945. A 50kΩ internal pulldown resistor defaults AUTO low. AUTO
latches when V
Software commands can take the MAX5945 out of AUTO while AUTO is high.
Oscillator Input. AC-disconnect detection function uses OSC_IN. Connect a 100Hz ±10%, 2V
±5%, +1.2V offset sine wave to OSC_IN. If the oscillator positive peak falls below the OSC_FAIL
threshold of 2V, the ports that have the AC function enabled shut down and are not allowed to power
up. When not using the AC-disconnect detection function, leave OSC_IN unconnected.
or VEE ramps up and exceeds its UVLO threshold or when the device resets.
DD
EE
.
. The address values latch when VDD or VEE ramps
DD
with 50kΩ resistor.
DD
to set MIDSPAN operation. The
DIG
2
C-compatible system.
2
C-compatible system.
(see the Typical Application Circuit).
EE
DD
P-P
MAX5945
Detailed Description
The MAX5945 four-port network power controller controls -32V to -60V negative supply rail systems. Use the
MAX5945, which is compliant with the IEEE 802.3af
standard for PSE in power-over-LAN applications. The
MAX5945 provides PD discovery, classification, current
limit, both DC and AC load disconnect detections, and
other necessary functions for an IEEE 802.3af-compli-
ant PSE. The MAX5945 can be used in either endpoint
PSE (LAN switch/router) or midspan PSE (power injector) applications.
The MAX5945 is fully software-configurable and programmable with more than 25 internal registers. The
device features an I
2
C-compatible, 3-wire serial interface and a class-overcurrent detection. The class-overcurrent detection function enables system power man-
agement where it detects a PD that draws more current
than the allowable amount for its class. The MAX5945’s
extensive programmability enhances system flexibility
and allows for uses in other applications.
The MAX5945 has four different operating modes: auto
mode, semi-auto mode, manual mode, and shutdown
mode (see the Operation Modes section). A special
watchdog feature allows the hardware to gracefully
take over control if the software/firmware crashes. A
cadence timing feature allows the MAX5945 to be used
in midspan systems.
The MAX5945 provides input undervoltage lockout,
input undervoltage detection, input overvoltage lockout,
overtemperature protection, output-voltage slew-rate
limit during startup, power-good status, and fault
status. The MAX5945’s programmability includes
gate-charging current, current-limit threshold, startup
timeout, overcurrent timeout, autorestart duty cycle, PD
disconnect AC detection threshold and PD disconnect
detection timeout.
The MAX5945 communicates with the system
microcontroller through an I2C-compatible interface.
The MAX5945 features separate input and output data
lines (SDAIN and SDAOUT) for use with optocoupler
isolation. The MAX5945 is a slave device. Its four
address inputs allow 16 unique MAX5945 addresses. A
separate INT output and four independent shutdown
inputs (SHD_) allow fast interrupt signals between the
MAX5945 and the microcontroller. A RESET input
allows hardware reset of the device.
Reset
Reset is a condition the MAX5945 enters after any of
the following conditions:
•After power-up (VEEand VDDrise above their UVLO
thresholds).
•Hardware reset. The RESET input is driven low and
up high again any time after power-up.
•Software reset. Writing a 1 into R1Ah[4] any time
after power-up.
•Thermal shutdown.
During a reset, the MAX5945 resets its register map to
the reset state as shown in Table 30 and latches in the
state of AUTO (pin 35) and MIDSPAN (pin 2). During
normal operation, changes at the AUTO and MIDSPAN
inputs are ignored. While the condition that caused the
reset persists (i.e., high temperature, RESET input low,
or UVLO conditions) the MAX5945 will not acknowledge any addressing from the serial interface.
Port Reset (R1Ah[3:0])
Set high anytime during normal operation to turn off
power and clear the events and status registers of the
corresponding port. Port reset only resets the events
and status registers.
Operation Modes
The MAX5945 contains four independent but identical
state machines to provide reliable and real-time control
of the four network ports. Each state machine has four
different operating modes: auto, semi-auto, manual,
and shutdown. Auto mode allows the device to operate
automatically without any software supervision. Semiauto mode, upon request, continuously detects and
classifies a device connected to a port but does not
power up that port until instructed by software. Manual
mode allows total software control of the device and is
useful in system diagnostic. Shutdown mode terminates
all activities and securely turns off power to the ports.
Switching between AUTO, SEMI, or MANUAL mode
does not take effect until the part finishes its current
task. When the port is set into SHUTDOWN mode, all
the port operations are immediately stopped and the
port remains idle until SHUTDOWN is exited.
Automatic (AUTO) Mode
Enter automatic (AUTO) mode by forcing the
AUTO input high prior to a reset, or by setting
R12h[P_ M1,P_M0] to [1,1] during normal operation
(see Tables 15 and 15a). In AUTO mode, the MAX5945
performs detection, classification, and powers up the
port automatically once a valid PD is detected at the
port. If a valid PD is not detected at the port, the
MAX5945 repeats the detection routine continuously
until a valid PD is detected.
Going into AUTO mode, the DET_EN and CLASS_EN
bits are set to high and stay high unless changed by
software. Using software to set DET_EN and/or
CLASS_EN low causes the MAX5945 to skip detection
and/or classification. As a protection, disabling the
detection routine in AUTO mode will not allow the corresponding port to power up, unless the DET_BYP
(R23H[4]) is set to 1.
The AUTO status is latched into the register only during
a reset. Any changes to the AUTO input after reset is
ignored.
Semi-Automatic (SEMI) Mode
Enter semi-automatic (SEMI) mode by setting
R12h[P_M1,P_M0] to [1,0] during normal operation
(see Tables 15 and 15a). In SEMI mode, the MAX5945,
upon request, performs detection and/or classification
repeatedly but does not power up the port(s), regardless of the status of the port connection.
Setting R19h[PWR_ON_] (Table 21) high immediately
terminates detection/classification routines and turns on
power to the port(s).
R14h[DET_EN_, CLASS_EN_] default to low in SEMI
mode. Use software to set R14h[DET_EN_,
CLASS_EN_] to high to start the detection and/or classification routines. R14h[DET_EN_, CLASS_EN_] are
reset every time the software commands a power-off of
the port (either through reset or PWR_OFF). In any other
case, the status of the bits is left unchanged (including
when the state machine turns off the power because a
load disconnect or a fault condition is encountered).
MANUAL Mode
Enter MANUAL mode by setting R12h[P_M1,P_M0] to
[0,1] during normal operation (see Tables 15 and 15a).
MANUAL mode allows the software to dictate any
sequence of operation. Write a 1 to both R14h[DET_ EN_]
and R14h[CLASS_EN_] start detection and classification operations, respectively, and in that priority order.
After execution, the command is cleared from the register(s). PWR_ON_ has highest priority. Setting PWR_ON_
high at any time causes the device to immediately enter
the powered mode. Setting DET_EN and CLASS_EN
high at the same time causes detection to be performed first. Once in the powered state, the device
ignores DET_EN_ or CLASS_EN_ commands.
When switching to MANUAL mode from another mode,
DET_EN_, CLASS_EN_ default to low. These bits
become pushbutton rather than configuration bits (i.e.,
writing ones to these bits while in MANUAL mode commands the device to execute one cycle of detection
and/or classification. The bits are reset back to zeros at
the end of the execution). Putting the MAX5945 into
shutdown mode immediately turns off power and halts
all operations to the corresponding port. The event and
status bits of the affected port(s) are also cleared. In
SHUTDOWN mode, the DET_EN_, CLASS_EN_, and
PWR_ON_ commands are ignored.
In SHUTDOWN mode, the serial interface operates
normally.
Watchdog
R1Dh, R1Eh, and R1Fh registers control watchdog operation. The watchdog function, when enabled, allows the
MAX5945 to gracefully take over control or securely shut
down the power to the ports in case of software/firmware
crashes. Contact the factory for more details.
PD Detection
When PD detection is activated, the MAX5945 probes
the output for a valid PD. After each detection cycle,
the device sets the DET_END_ bit R04h/05h[3:0] high
and reports the detection results in the status registers
R0Ch[2:0], R0Dh[2:0], R0Eh[2:0], and R0Fh[2:0]. The
DET_END_ bit is reset to low when read through R05h
or after a port reset. Both DET_END_ bit status registers
are cleared after the port powers down.
A valid PD has a 25kΩ discovery signature characteristic as specified in the IEEE 802.3af standard. Table 1
shows the IEEE 802.3af specification for a PSE detecting a valid PD signature (see the Typical ApplicationCircuit and Figure 2). The MAX5945 can probe and categorize different types of devices connected to the port
such as a valid PD, an open circuit, a low resistive load,
a high resistive load, a high capacitive load, a positive
DC supply, or a negative DC supply.
During detection, the MAX5945 turns off the external
MOSFET and forces two probe voltages through the
DET_ input. The current through the DET_ input is measured as well as the voltage at OUT_. A two-point slope
measurement is used as specified by the IEEE 802.3af
standard to verify the device connected to the port. The
MAX5945 implements appropriate settling times and a
100ms digital integration to reject 50Hz/60Hz powerline noise coupling.
An external diode, in series with the DET_ input,
restricts PD detection to the 1st quadrant as specified
by the IEEE 802.3af standard. To prevent damage to
non-PD devices and to protect itself from an output
short circuit, the MAX5945 limits the current into DET_
to less than 2mA maximum during PD detection.
In midspan mode, the MAX5945 waits 2.2s before
attempting another detection cycle after every failed
detection. The first detection, however, happens immediately after issuing the detection command.
Power Device Classification
(PD Classification)
During the PD classification mode, the MAX5945 forces
a probe voltage (-18V) at DET_ and measures the current into DET_. The measured current determines the
class of the PD.
After each classification cycle, the device sets the
CL_END_ bit (R04h/05h[7:4]) high and reports the classification results in the status registers R0Ch[6:4],
R0Dh[6:4], R0Eh[6:4], and R0Fh[6:4]. The CL_END_ bit
is reset to low when read through register R05h or after
a port reset. Both Class_END_ bit status registers are
cleared after the port powers down.