General Description
The MAX5889 advanced 12-bit, 600Msps, digital-toanalog converter (DAC) meets the demanding performance requirements of signal synthesis applications
found in wireless base stations and other communications applications. Operating from +3.3V and +1.8V
supplies, the MAX5889 DAC supports update rates of
600Msps using high-speed LVDS inputs while consuming only 292mW of power and offers exceptional
dynamic performance such as 79dBc spurious-free
dynamic range (SFDR) at f
OUT
= 30MHz.
The MAX5889 utilizes a current-steering architecture that
supports a 2mA to 20mA full-scale output current range,
and produces -2dBm to -22dBm full-scale output signal
levels with a double-terminated 50Ω load. The MAX5889
features an integrated +1.2V bandgap reference and
control amplifier to ensure high-accuracy and low-noise
performance. A separate reference input (REFIO) allows
for the use of an external reference source for optimum
flexibility and improved gain accuracy.
The MAX5889 digital inputs accept LVDS voltage levels, and the flexible clock input can be driven differentially or single-ended, AC- or DC-coupled. The
MAX5889 is available in a 68-pin QFN package with an
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.
Refer to the MAX5891 and MAX5890 data sheets for pincompatible 16-bit and 14-bit versions of the MAX5889.
Applications
Base Stations: Single-Carrier UMTS,
CDMA, GSM
Communications: Fixed Broadband Wireless
Access, Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination Systems (CMTS)
Automated Test Equipment (ATE)
Instrumentation
Features
♦ 600Msps Output Update Rate
♦ Low-Noise Spectral Density: -157dBFS/Hz at
f
OUT
= 36MHz
♦ Excellent SFDR and IMD Performance
SFDR = 79dBc at f
OUT
= 30MHz (to Nyquist)
SFDR = 67dBc at f
OUT
= 130MHz (to Nyquist)
IMD = -93dBc at f
OUT
= 30MHz
IMD = -76dBc at f
OUT
= 130MHz
♦ ACLR = 72dB at f
OUT
= 122.88MHz
♦ 2mA to 20mA Full-Scale Output Current
♦ LVDS-Compatible Digital Inputs
♦ On-Chip +1.2V Bandgap Reference
♦ Low 292mW Power Dissipation at 600Msps
♦ Compact (10mm x 10mm) QFN-EP Package
♦ Evaluation Kit Available (MAX5891EVKIT)
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3620; Rev 0; 4/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART
TEMP RANGE
PIN-PACKAGE
PKG
CODE
MAX5889EGK
68 QFN-EP*
G6800-4
MAX5889
+1.2V
REFERENCE
REFIO
DACREF
FSADJ
CLK
INTERFACE
600MHz
12-BIT DAC
LATCH
LVDS
RECEIVER
D0–D11
LVDS DATA
INPUTS
POWER
DOWN
PD
CLKP
CLKN
OUTP
OUTN
Functional Diagram
PART
RESOLUTION
(BITS)
UPDATE RATE
(Msps)
LOGIC INPUT
MAX5889
12 600 LVDS
MAX5890
14 600 LVDS
MAX5891
16 600 LVDS
Selector Guide
*EP = Exposed paddle.
Pin Configuration appears at end of data sheet.
-40°C to +85°C
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference V
REFIO
= +1.2V, output load 50Ω double-ter-
minated, transformer-coupled output, I
OUT
= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are
guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
DD1.8
, DV
DD1.8
to AGND, DGND, DACREF,
and CGND.......................................................-0.3V to +2.16V
AV
DD3.3
, DV
DD3.3
, AV
CLK
to AGND, DGND,
DACREF, and CGND.........................................-0.3V to +3.9V
REFIO, FSADJ to AGND, DACREF,
DGND, and CGND ..........................-0.3V to (AV
DD3.3
+ 0.3V)
OUTP, OUTN to AGND, DGND, DACREF,
and CGND .......................................-1.2V to (AV
DD3.3
+ 0.3V)
CLKP, CLKN to AGND, DGND, DACREF,
and CGND..........................................-0.3V to (AV
CLK
+ 0.3V)
PD to AGND, DGND, DACREF,
and CGND.......................................-0.3V to (DV
DD3.3
+ 0.3V)
Digital Data Inputs (D0N–D11N, D0P–D11P) to AGND,
DGND, DACREF, and CGND ..........-0.3V to (DV
DD1.8
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C) (Note 1)
68-Pin QFN-EP (derate 28.6mW/°C above +70°C)....3333mW
Thermal Resistance
θ
JA
(Note 1) ....................................24°C/W
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution 12 Bits
Integral Nonlinearity INL Measured differentially
LSB
Differential Nonlinearity DNL Measured differentially
LSB
Offset Error OS
%FS
Full-Scale Gain Error GE
FS
External reference -4 ±1+4
%FS
Internal reference
Gain-Drift Tempco
External reference
ppm/°C
Full-Scale Output Current I
OUT
220mA
Output Compliance Single-ended
V
Output Resistance R
OUT
1MΩ
Output Capacitance C
OUT
5pF
Output Leakage Current PD = high, power-down mode ±1µA
DYNAMIC PERFORMANCE
Maximum DAC Update Rate
Msps
Minimum DAC Update Rate 1
Msps
f
OUT
= 36MHz,
Noise Spectral Density N
-12dBFS, 20MHz
offset from the
carrier
f
OUT
= 151MHz,
dBFS/Hz
f
OUT
= 36MHz 68
Signal-to-Noise Ratio Over
Nyquist
SNR
f
CLK
= 500MHz,
0dBFS
f
OUT
= 151MHz 64
dB
Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.
±0.25
±0.15
-0.02 0.001 +0.02
±130
f
= 500MHz,
CLK
A
FULL-SCALE
A
FULL-SCALE
-1.0 +1.1
600
= -3.5dBm
= -6.4dBm
±100
-157
-152
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference V
REFIO
= +1.2V, output load 50Ω double-ter-
minated, transformer-coupled output, I
OUT
= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are
guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
OUT
= 16MHz 86
f
CLK
= 200MHz,
0dBFS
f
OUT
= 30MHz 85
f
OUT
= 16MHz 78
f
CLK
= 200MHz,
-12dBFS
f
OUT
= 30MHz 77
f
OUT
= 16MHz 77 83
f
OUT
= 30MHz 79
f
OUT
= 130MHz 67
Spurious-Free
Dynamic Range to
Nyquist
SFDR
f
CLK
= 500MHz,
0dBFS
f
OUT
= 200MHz 63
dBc
f
CLK
= 500MHz
f
OUT1
= 29MHz,
f
OUT2
= 30MHz,
-6.5dBFS per tone
-93
Two-Tone IMD TTIMD
f
CLK
= 500MHz
f
OUT1
= 129MHz,
f
OUT2
= 130MHz,
-6.5dBFS per tone
-76
dBc
f
CLK
= 491.52MHz,
f
OUT
= 30.72MHz
80
WCDMA single
carrier
f
CLK
= 491.52MHz,
72
f
CLK
= 491.52MHz,
f
OUT
= 30.72MHz
72
Adjacent Channel
Leakage Power Ratio
ACLR
f
CLK
= 491.52MHz,
67
dB
Output Bandwidth
(Note 2)
REFERENCE
Internal Reference Voltage Range
V
REFIO
1.2
V
Reference Input Voltage Range
Using external reference
1.2
V
Reference Input Resistance R
REFIO
10 kΩ
Reference Voltage Temperature
Drift
BW
-1dB
V
REFIOCR
TCO
WCDMA four carriers
REF
f
= 122.88MHz
OUT
f
= 122.88MHz
OUT
1.14
0.10
1000 MHz
1.26
1.32
±30 ppm/°C
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference V
REFIO
= +1.2V, output load 50Ω double-ter-
minated, transformer-coupled output, I
OUT
= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are
guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG OUTPUT TIMING (Figure 3)
Output Fall Time t
FALL
90% to 10% (Note 3) 0.4 ns
Output Rise Time t
RISE
10% to 90% (Note 3) 0.4 ns
Output Propagation Delay t
PD
Reference to data latency (Note 3) 2.5 ns
Output Settling Time To 0.025% of the final value (Note 3) 11 ns
Glitch Impulse Measured differentially 1
I
OUT
= 2mA 30
Output Noise N
OUT
I
OUT
= 20mA 30
TIMING CHARACTERISTICS
Input Data Rate 600
Data Latency 5.5
Clock
Data to Clock Setup Time t
SETUP
ns
Data to Clock Hold Time t
HOLD
2ns
Clock Frequency f
CLK
CLKP, CLKN 600
Minimum Clock Pulse-Width High
t
CH
CLKP, CLKN 0.6 ns
Minimum Clock Pulse-Width Low
t
CL
CLKP, CLKN 0.6 ns
Turn-On Time t
SHDN
External reference, PD falling edge to
output settle within 1%
µs
CMOS LOGIC INPUT (PD)
Input Logic High V
IH
0.7 x
V
Input Logic Low V
IL
0.3 x
V
Input Current I
IN
-10
µA
Input Capacitance C
IN
3pF
LVDS INPUTS
Differential Input High
mV
Differential Input Low
mV
Common-Mode Voltage Range
V
Differential Input Resistance
Ω
Common-Mode Input Resistance
3.2 kΩ
Input Capacitance
3pF
DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)
Clock Common-Mode Voltage CLKP and CLKN are internally biased
V
Minimum Differential Input
Voltage Swing
0.5
Referenced to rising edge of clock (Note 4) -1.2
Referenced to rising edge of clock (Note 4)
350
pV•s
pA/√Hz
MWps
cycles
MHz
V
IHLVDS
V
ILLVDS
V
ICMLVDS
R
IDLVDS
R
ICMLVDS
C
INLVDS
DV
DD3.3
DV
DD3.3
±1.8 +10
+100
-100
1.125 1.375
110
AV
/ 2
CLK
V
P-P
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
_______________________________________________________________________________________ 5
Note 2: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5889.
Note 3: Parameter measured single-ended with 50Ω double-terminated outputs.
Note 4: Not production tested. Guaranteed by design.
Note 5: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltages.
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference V
REFIO
= +1.2V, output load 50Ω double-ter-
minated, transformer-coupled output, I
OUT
= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥ +25°C are
guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
CONDITIONS
UNITS
Minimum Common-Mode Voltage
1V
Maximum Common-Mode
Voltage
1.9 V
Input Resistance R
CLK
Single-ended 5 kΩ
Input Capacitance C
CLK
3pF
POWER SUPPLIES
3.3
Analog Supply Voltage Range
1.8
V
Clock Supply Voltage Range AV
CLK
3.3
V
3.3
Digital Supply Voltage Range
1.8
V
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz
28
f
CLK
= 600MHz, f
OUT
= 16MHz
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz 50 58
Analog Supply Current
f
CLK
= 600MHz, f
OUT
= 16MHz 60
mA
f
CLK
= 100MHz, f
OUT
= 16MHz 2.8
f
CLK
= 500MHz, f
OUT
= 16MHz 2.8 3.6Clock Supply Current I
AVCLK
f
CLK
= 600MHz, f
OUT
= 16MHz 2.8
mA
f
CLK
= 100MHz, f
OUT
= 16MHz 0.2
f
CLK
= 500MHz, f
OUT
= 16MHz 0.2 0.5
f
CLK
= 600MHz, f
OUT
= 16MHz 0.2
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz 42 48
Digital Supply Current
f
CLK
= 600MHz, f
OUT
= 16MHz 48
mA
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz
297
f
CLK
= 600MHz, f
OUT
= 16MHz
mW
Total Power Dissipation P
DISS
Power-down, clock static low,
data input static
13 µW
Power-Supply Rejection Ratio PSRR (Note 5)
%FS
SYMBOL
AV
DD3.3
AV
DD1.8
DV
DD3.3
DV
DD1.8
I
AVDD3.3
I
AVDD1.8
I
DVDD3.3
I
DVDD1.8
MIN TYP MAX
3.135
1.710
3.135
3.135
1.710
26.5
26.5
26.5
11.3
10.2
137
263
292
±0.025
3.465
1.890
3.465
3.465
1.890
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
6 _______________________________________________________________________________________
Typical Operating Characteristics
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference V
REFIO
= +1.2V, output load 50Ω double-ter-
minated, transformer-coupled output, I
OUT
= 20mA, TA= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 100MHz)
MAX5889 toc01
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
302010
10
20
30
40
50
60
70
80
90
100
0
05040
0dBFS
-6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 200MHz)
MAX5889 toc02
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
706040 5020 3010
10
20
30
40
50
60
70
80
90
100
0
080
0dBFS
-6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 500MHz)
MAX5889 toc03
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
1601208040
10
20
30
40
50
60
70
80
90
100
0
0200
0dBFS
-6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 600MHz)
MAX5889 toc04
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
1601208040
10
20
30
40
50
60
70
80
90
100
0
0 200
0dBFS
-6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
(f
CLK
= 500MHz, I
OUT
= 20mA, 10mA, 5mA)
MAX5889 toc05
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
1601208040
10
20
30
40
50
60
70
80
90
100
0
0200
20mA
10mA
5mA
0dBFS
DAC OUTPUT SPECTRAL PLOT
(f
CLK
= 200MHz)
MAX5889 toc06
OUTPUT FREQUENCY (MHz)
OUTPUT POWER (dBm)
80604020
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
0100
70503010 90
DAC OUTPUT SPECTRAL PLOT
(f
CLK
= 500MHz)
MAX5889 toc07
OUTPUT FREQUENCY (MHz)
200
15010050
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
0 250
OUTPUT POWER (dBm)
TWO-TONE SPECTRAL PLOT
(f
CLK
= 500MHz, -6.5dBFS PER TONE)
MAX5889 toc08
OUTPUT FREQUENCY (MHz)
131
130129128
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
127 132
OUTPUT POWER (dBm)
TWO-TONE SPECTRAL PLOT
(f
CLK
= 500MHz, -6.5dBFS PER TONE)
MAX5889 toc09
OUTPUT FREQUENCY (MHz)
31
302928 302928
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
27 32
OUTPUT POWER (dBm)
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
_______________________________________________________________________________________ 7
TWO-TONE INTERMODULATION DISTORTION
vs. OUTPUT FREQUENCY
(f
CLK
= 500MHz, 1MHz CARRRIER SPACING)
MAX5889 toc10
OUTPUT FREQUENCY (MHz)
TTIMD (dBc)
1601208040
-110
-100
-90
-80
-70
-60
-120
0 200
-6.5dBFS
-12dBFS
SINGLE-CARRIER WCDMA ACLR
(f
CLK
= 491.52MHz)
OUTPUT POWER (dBm)
MAX5889 toc11
2.55MHz/div
-120
-130
-110
-100
-90
-80
-70
-60
-50
-40
-20
-30
ACLR = 72.0dB
f
CENTER
= 122.88MHz
FOUR-CARRIER WCDMA ACLR
(f
CLK
= 491.52MHz)
MAX5889 toc12
4.06MHz/div
OUTPUT POWER (dBm)
-120
-130
-110
-100
-90
-80
-70
-60
-50
-40
-20
-30
ACLR = 67.4dB
f
CENTER
= 122.88MHz
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE (f
CLK
= 500MHz)
MAX5889 toc13
TEMPERATURE (°C)
SFDR (dBc)
603510-15
60
70
80
90
100
50
-40 85
f
OUT
= 10MHz
f
OUT
= 50MHz
f
OUT
= 100MHz
0dBFS
INTEGRAL NONLINEARITY
MAX5889 toc14
DIGITAL INPUT CODE
INL (LSB)
3584
3072
512
1024
1536
2048
2560
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
-0.20
0 4096
DIFFERENTIAL NONLINEARITY
MAX5889 toc15
DIGITAL INPUT CODE
DNL (LSB)
3584
3072
512
1024
1536
2048
2560
-0.05
-0.10
-0.15
0
0.05
0.10
0.15
0.20
-0.20
0 4096
TOTAL POWER DISSIPATION vs. CLOCK FREQUENCY
(f
OUT
= 16MHz, A
OUT
= 0dBFS)
MAX5889 toc16
CLOCK FREQUENCY (MHz)
POWER DISSIPATION (mW)
500400300200100
50
100
150
200
250
300
350
0
0600
Typical Operating Characteristics (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference V
REFIO
= +1.2V, output load 50Ω double-ter-
minated, transformer-coupled output, I
OUT
= 20mA, TA= +25°C, unless otherwise noted.)
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
8 _______________________________________________________________________________________
PIN NAME FUNCTION
1, 46, 48, 50,
52, 54, 56, 58,
60, 63, 65, 67
D0N, D11N, D10N,
D9N, D8N, D7N,
D6N, D5N, D4N,
D3N, D2N, D1N
Differential Negative LVDS Inputs. Data bits D0–D11 (offset binary format).
2–9 N.C. No Connection. Leave floating or connect to DGND.
10 DGND Digital Ground. Ground return for DV
DD3.3
and DV
DD1.8
.
11 DV
DD3.3
Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1µF capacitor to DGND.
12 PD
Power-Down Input. Set PD high to force the DAC into power-down mode. Set PD low for
normal operation. PD has an internal 2µA pulldown.
13, 42, 43, 44
N.C. No Connection. Leave floating or connect to AGND.
14, 21, 22, 25,
26, 31, 32
AV
DD3.3
Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1µF capacitor to AGND.
15, 20, 23, 24,
27, 30, 33
AGND Analog Ground. Ground return for AV
DD3.3
and AV
DD1.8
.
16 REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a
0.1µF capacitor to AGND. REFIO can be driven with an external reference source.
17 FSADJ
Full-Scale Current Adjustment. Connect an external resistor R
SET
between FSADJ and
DACREF to set the output full-scale current. The output full-scale current is equal to 32 x
V
REF
/ R
SET
.
18 DACREF
Current-Set Resistor Return Path. Internally connected to ground, but do not use as
ground connection.
19, 34, 35 AV
DD1.8
Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a
0.1µF capacitor to AGND.
28 OUTN Complementary DAC Output. Negative terminal for current output.
29 OUTP DAC Output. Positive terminal for current output.
36, 41 AV
CLK
Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1µF capacitor to CGND.
37, 40 CGND Clock Supply Ground
38 CLKN
Complementary Converter Clock Input. Negative input terminal for differential converter
clock.
39 CLKP Converter Clock Input. Positive input terminal for differential converter clock.
45, 47, 49, 51,
53, 55, 57, 59,
62, 64, 66, 68
D11P, D10P, D9P,
D8P, D7P, D6P, D5P,
D4P, D3P, D2P, D1P,
D0P
Differential Positive LVDS Inputs. Data bits D0–D11 (offset binary format).
61 DV
DD1.8
Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a
0.1µF capacitor to DGND.
— EP
Exposed Pad. Must be connected to common point for AGND, DGND, and CGND through
a low-impedance path. EP is internally connected to AGND, DGND, and CGND.
Pin Description
Detailed Description
Architecture
The MAX5889 high-performance, 12-bit, current-steering DAC (see the Functional Diagram) operates with
DAC update rates up to 600Msps. The current-steering
array generates differential full-scale currents in the
2mA to 20mA range. An internal current-switching network, in combination with external 50Ω termination
resistors, converts the differential output currents into a
differential output voltage with a 0.1V to 1V peak-topeak output voltage range. The analog outputs have a
-1.0V to +1.1V voltage compliance. For applications
requiring high dynamic performance, use the differential output configuration and limit the output voltage
swing to ±0.5V at each output. An integrated +1.2V
bandgap reference, control amplifier, and user-selectable external resistor determine the data converter’s
full-scale output range.
Reference Architecture and Operation
The MAX5889 operates with the internal +1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, lowimpedance reference source or as a reference output
when the DAC operates in internal reference mode. For
stable operation with the internal reference, bypass
REFIO to AGND with a 0.1µF capacitor. The REFIO output resistance is 10kΩ. Buffer REFIO with a high-inputimpedance amplifier when using it as a reference
source for external circuitry.
The MAX5889’s reference circuit (Figure 1) employs a
control amplifier to regulate the full-scale current,
I
OUTFS
, for the differential current outputs of the DAC.
Calculate the output current as follows:
where I
OUTFS
is the full-scale output current of the
DAC. R
SET
(located between FSADJ and DACREF)
determines the amplifier’s full-scale output current for
the DAC. See Table 1 for a matrix of different I
OUTFS
and R
SET
selections.
Analog Outputs (OUTP, OUTN)
The complementary current outputs (OUTP, OUTN) can
be connected in a single-ended or differential configuration. A load resistor converts these two output currents into complementary single-ended output
voltages. A transformer or a differential amplifier converts the differential voltage existing between OUTP
and OUTN to a single-ended voltage. When not using a
transformer, terminate each output with a 25Ω resistor
to ground and a 50Ω resistor between the outputs.
To generate a single-ended output, select OUTP as the
output and connect OUTN to AGND. Figure 2 shows a
simplified diagram of the internal output structure of the
MAX5889.
I
V
R
OUTFS
REFIO
SET
=× ×−
32 1
1
2
12
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
_______________________________________________________________________________________ 9
R
SET
(kΩ)
FULL-SCALE CURRENT
I
OUTFS
(mA)
1% EIA STD
2 19.2 19.1
5 7.68 7.5
10 3.84 3.83
15 2.56 2.55
20 1.92 1.91
Table 1. I
OUTFS
and R
SET
Selection Matrix
Based on a Typical +1.200V Reference
Voltage
OUTP
OUTN
+1.2V
REFERENCE
CURRENT-SOURCE
ARRAY DAC
REFIO
FSADJ
R
SET
I
REF
10kΩ
DACREF
0.1µF
I
REF
= V
REFIO
/ R
SET
Figure 1. Reference Architecture, Internal Reference
Configuration
CALCULATED
MAX5889
Clock Inputs (CLKP, CLKN)
To achieve the best possible jitter performance, the
MAX5889 features flexible differential clock inputs
(CLKP, CLKN) that operate from a separate clock
power supply (AV
CLK
). Drive the differential clock
inputs from a single-ended or a differential clock
source. For highest dynamic performance, differential
clock source is required. For single-ended operation,
drive CLKP and bypass CLKN to CGND.
CLKP and CLKN are internally biased at AV
CLK
/ 2,
allowing the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The input resistance from CLKP and CLKN to
ground is approximately 5kΩ.
Data-Timing Relationship
Figure 3 shows the timing relationship between digital
LVDS data, clock, and output signals. The MAX5889
features a 2ns hold, a -1.2ns setup, and a 2.5ns propagation delay time. There is a 5.5 clock-cycle latency
between data write operation and the corresponding
analog output transition.
LVDS Data Inputs
The MAX5889 has 12 pairs of LVDS data inputs (offset
binary format) and can accept data rates up to
600MWps. Each differential input pair is terminated with
an internal 110Ω resistor. The common-mode input
resistance is 3.2kΩ.
Power-Down Operation (PD)
The MAX5889 features a power-down mode that
reduces the DAC’s power consumption. Set PD high to
power down the MAX5889. Set PD low or leave unconnected for normal operation.
When powered down, the MAX5889 overall power consumption is reduced to less than 13µW. The MAX5889
requires 350µs to wake up from power-down and enter
a fully operational state if the external reference is
used. If the internal reference is used, the power-down
recovery time is 10ms. The PD internal pulldown circuit
sets the MAX5889 in normal mode when PD is left
unconnected.
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
10 ______________________________________________________________________________________
I
OUT
I
OUT
OUTN OUTP
CURRENT
SOURCES
CURRENT
SWITCHES
AV
DD3.3
Figure 2. Simplified Analog Output Structure
D0–D11
t
SETUP
t
HOLD
D
N
CLKP
CLKN
D
N + 2
D
N + 4
D
N + 6
IOUTP
IOUTN
t
PD
D
N + 1
D
N + 3
D
N + 5
D
N + 7
OUT
N - 2
OUT
N - 3
OUT
N - 4
OUT
N - 5
OUT
N - 6
OUT
N - 7
OUT
N-1
OUT
N
Figure 3. Timing Relationship Between Clock, Input Data, and Analog Output
Applications Information
Clock Interface
To achieve the best possible jitter performance, the
MAX5889 features flexible differential clock inputs
(CLKP, CLKN) that operate from a separate clock
power supply (AV
CLK
). Use a low-jitter clock to reduce
the DAC’s phase noise and wideband noise. To
achieve the best DAC dynamic performance, the
CLKP/CLKN input source must be designed carefully.
The differential clock (CLKN and CLKP) input can be
driven from a single-ended or a differential clock
source. Use differential clock drive to achieve the best
dynamic performance from the DAC. For single-ended
operation, drive CLKP with a low-noise source and
bypass CLKN to CGND with a 0.1µF capacitor.
Figure 4 shows a convenient and quick way of applying
a differential signal created from a single-ended source
using a wideband transformer. Alternatively, drive
CLKP/CLKN from a CMOS-compatible clock source.
Use sine wave or AC-coupled differential ECL/PECL
drive for best dynamic performance.
Differential Output Coupling Using a
Wideband RF Transformer
Use a pair of transformers (Figure 5) or a differential
amplifier configuration to convert the differential voltage
existing between OUTP and OUTN to a single-ended
voltage. Optimize the dynamic performance by using a
differential transformer-coupled output and limit the output power to <0dBm full scale. To achieve the best
dynamic performance, use the differential transformer
configuration. Terminate the DAC as shown in Figure 5,
and use 50Ω termination at the transformer singleended output. This provides double 50Ω termination for
the DAC output network. With the double-terminated
output and 20mA full-scale current, the DAC produces a
full-scale signal level of approximately -2dBm. Pay close
attention to the transformer core saturation characteristics when selecting a transformer for the MAX5889.
Transformer core saturation can introduce strong 2ndorder harmonic distortion especially at low output frequencies and high signal amplitudes. For best results,
connect the center tap of the transformer to ground.
When not using a transformer, terminate each DAC output to ground with a 25Ω resistor. Additionally, place a
50Ω resistor between the outputs (Figure 6).
For a single-ended unipolar output, select OUTP as the
output and connect OUTN to AGND. Operating the
MAX5889 single-ended is not recommended because
it degrades the dynamic performance.
The distortion performance of the DAC depends on the
load impedance. The MAX5889 is optimized for 50Ω
differential double termination. Using higher termination
impedance degrades distortion performance and
increases output noise voltage.
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
______________________________________________________________________________________ 11
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED-TO-
DIFFERENTIAL CONVERSION
SINGLE-ENDED
CLOCK SOURCE
AGND
1:1
25Ω
25Ω
CLKP
CLKN
TO DAC
0.1µF
0.1µF
Figure 4. Differential Clock-Signal Generation
MAX5889
OUTP
OUTN
WIDEBAND RF TRANSFORMER T2 PERFORMS THE
DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION
T1, 1:1
T2, 1:1
AGND
50Ω
100Ω
50Ω
V
OUT
, SINGLE-ENDED
D0–D11
LVDS
DATA INPUTS
Figure 5. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer
MAX5889
Grounding, Bypassing, and Power-Supply
Considerations
Grounding and power-supply decoupling strongly influence the MAX5889 performance. Unwanted digital
crosstalk coupling through the input, reference, power
supply, and ground connections affects dynamic performance. High-speed, high-frequency applications
require closely followed proper grounding and powersupply decoupling. These techniques reduce EMI and
internal crosstalk that can significantly affect the
MAX5889 dynamic performance.
Use a multilayer printed circuit (PC) board with separate ground and power-supply planes. Run high-speed
signals on lines directly above the ground plane. Keep
digital signals as far away from sensitive analog inputs
and outputs, reference input sense lines, commonmode inputs, and clock inputs as practical. Use a symmetric design of clock input and the analog output lines
to minimize 2nd-order harmonic distortion components,
thus optimizing the DAC’s dynamic performance. Keep
digital signal paths short and run lengths matched to
avoid propagation delay and data skew mismatches.
The MAX5889 requires five separate power-supply
inputs for analog (AV
DD1.8
and AV
DD3.3
), digital
(DV
DD1.8
and DV
DD3.3
), and clock (AV
CLK
) circuitry.
Decouple each AV
DD3.3
, AV
DD1.8
, AV
CLK
, DV
DD3.3
, and
DV
DD1.8
input with a separate 0.1µF capacitor as close
to the device as possible with the shortest possible connection to the respective ground plane (Figure 7).
Connect all the 3.3V supplies together at one point with
ferrite beads to minimize supply noise coupling.
Decouple all five power-supply voltages at the point they
enter the PC board with tantalum or electrolytic capacitors. Ferrite beads with additional decoupling capacitors
forming a pi network can also improve performance.
Similarly, connect all 1.8V supplies together at one point
with ferrite beads.
The analog and digital power-supply inputs AV
DD3.3
,
AV
CLK
, and DV
DD3.3
allow a +3.135V to +3.465V supply voltage range. The analog and digital power-supply
inputs AV
DD1.8
and DV
DD1.8
allow a +1.71V to +1.89V
supply voltage range.
The MAX5889 is packaged in a 68-pin QFN-EP package with exposed paddle, providing optimized DAC AC
performance. The exposed pad must be soldered to
the ground plane of the PC board. Thermal efficiency is
not the key factor, since the MAX5889 features lowpower operation. The exposed pad ensures a solid
ground connection between the DAC and the PC
board’s ground layer.
The data converter die attaches to an EP lead frame
with the back of this frame exposed at the package
bottom surface, facing the PC board side of the package. This allows for a solid attachment of the package
to the PC board with standard infrared (IR) reflow soldering techniques. A specially created land pattern on
the PC board, matching the size of the EP (6mm x
6mm), ensures the proper attachment and grounding of
the DAC. Place vias into the land area and implement
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
12 ______________________________________________________________________________________
MAX5889
OUTP
OUTN
AGND
25Ω
50Ω
25Ω
OUTP
OUTN
D0–D11
LVDS
DATA INPUTS
Figure 6. Differential Output Configuration
MAX5889
OUTPAV
DD3.3
AV
DD1.8
DV
DD3.3
DV
DD1.8
AV
CLK
OUTN
0.1µF
3.3V VOLTAGE SUPPLY
0.1µF
0.1µF 0.1µF
1.8V VOLTAGE SUPPLY
0.1µF
BYPASSING—DAC LEVEL
*FERRITE BEADS
D0–D11
LVDS
DATA INPUTS
*
**
**
Figure 7. Recommended Power-Supply Decoupling and
Bypassing Circuitry
large ground planes in the PC board design to ensure
the highest dynamic performance of the DAC. Connect
the MAX5889 exposed paddle to the common connection point of DGND, AGND, and CGND. Vias connect
the top land pattern to internal or external copper
planes. Use as many vias as possible to the ground
plane to minimize inductance. The vias should have a
diameter greater than 0.3mm.
Static Performance Parameter
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a line drawn between the
end points of the transfer function, once offset and gain
errors have been nullified. For a DAC, the deviations
are measured at every individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
Glitch Impulse
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011...111 to 100...000. The glitch
impulse is found by integrating the voltage of the glitch
at the midscale transition over time. The glitch impulse
is usually specified in pV
•s.
Dynamic Performance Parameter
Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of the
full-scale analog output (RMS value) to the RMS quantization error (residual error). The ideal, theoretical maximum can be derived from the DAC’s resolution (N bits):
SNRdB = 6.02dB x N + 1.76dB
However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading;
therefore, SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four
harmonics, and the DC offset.
Noise Spectral Density
The DAC output noise floor is the sum of the quantization noise and the output amplifier noise (thermal and
shot noise). Noise spectral density is the noise power in
1Hz bandwidth, specified in dBFS/Hz.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier
frequency (maximum signal components) to the RMS
value of their next-largest distortion component. SFDR is
usually measured in dBc and with respect to the carrier
frequency amplitude or in dBFS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or to
Nyquist.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or
dBFS) of the worst 3rd-order IMD differential product to
either output tone. The two-tone IMD performance of
the MAX5889 is tested with the two individual output
tone levels set to at least -6.5dBFS.
Adjacent Channel Leakage Power Ratio (ACLR)
Commonly used in combination with wideband codedivision multiple-access (WCDMA), ACLR reflects the
leakage power ratio in dB between the measured
power within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
______________________________________________________________________________________ 13
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
14 ______________________________________________________________________________________
Pin Configuration
D0N
1
N.C.2N.C.3N.C.4N.C.5N.C.6N.C.7N.C.8N.C.
9
DGND
10
DV
DD3.3
11PD12
N.C.
13
AV
DD3.3
14
AGND
15
REFIO
EXPOSED PADDLE
16
FSADJ
17
D8P51D9N50D9P49D10N48D10P47D11N46D11P45N.C.44N.C.43N.C.42AV
CLK
41
CGND40CLKP39CLKN38CGND37AV
CLK
36
AV
DD1.8
35
DACREF
18
AV
DD1.819
AGND
20
AV
DD3.321
AV
DD3.322
AGND
23
AGND
24
AV
DD3.325
AV
DD3.326
AGND
27
OUTN
28
OUTP
29
AGND
30
AV
DD3.331
AV
DD3.332
AGND
33
AV
DD1.834
D0P
68
D1N
67
D1P
66
D2N
65
D2P
64
D3N
63
D3P
62
DV
DD1.8
61
D4N
60
D4P
59
D5N
58
D5P
57
D6N
56
D6P
55
D7N
54
D7P
53
D8N
52
MAX5889
QFN-EP
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
68L QFN.EPS
C
1
2
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
C
1
2
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
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