Rainbow Electronics MAX5887 User Manual
General Description
The MAX5887 is an advanced, 14-bit, 500Msps digitalto-analog converter (DAC) designed to meet the
demanding performance requirements of signal synthesis applications found in wireless base stations and
other communications applications. Operating from a
single 3.3V supply, this DAC offers exceptional dynamic performance such as 76dBc spurious-free dynamic
range (SFDR) at f
OUT
= 30MHz. The DAC supports
update rates of 500Msps and a power dissipation of
only 230mW.
The MAX5887 utilizes a current-steering architecture,
which supports a full-scale output current range of 2mA
to 20mA, and allows a differential output voltage swing
between 0.1V
P-P
and 1V
P-P
.
The MAX5887 features an integrated 1.2V bandgap reference and control amplifier to ensure high accuracy
and low noise performance. Additionally, a separate
reference input pin enables the user to apply an external reference source for optimum flexibility and to
improve gain accuracy.
The digital and clock inputs of the MAX5887 are
designed for differential low-voltage differential signal
(LVDS)-compatible voltage levels. The MAX5887 is
available in a 68-pin QFN package with an exposed
paddle (EP) and is specified for the extended industrial
temperature range (-40°C to +85°C).
Refer to the MAX5886 and MAX5888 data sheets for
pin-compatible 12- and 16-bit versions of the MAX5887.
Applications
Base Stations: Single-/Multicarrier UMTS,
CDMA, GSM
Communications: LMDS, MMDS, Point-to-Point
Microwave
Digital Signal Synthesis
Automated Test Equipment (ATE)
Instrumentation
Features
♦ 500Msps Output Update Rate
♦ Single 3.3V Supply Operation
♦ Excellent SFDR and IMD Performance
SFDR = 76dBc at f
OUT
= 30MHz (to Nyquist)
IMD = -85dBc at f
OUT
= 10MHz
ACLR = 72dB at f
OUT
= 61MHz
♦ 2mA to 20mA Full-Scale Output Current
♦ Differential, LVDS-Compatible Digital and Clock
Inputs
♦ On-Chip 1.2V Bandgap Reference
♦ Low 130mW Power Dissipation
♦ 68-Lead QFN-EP Package
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2777; Rev 0; 4/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX5887EGK -40°C to +85°C 68 QFN-EP*
5859606162 5455565763
38
39
40
41
42
43
44
45
46
47
VCLK
AGND
B4P
QFN
TOP VIEW
DGND
DVDDDGND
B5N
B5P
B6N
B6P
B7N
B7P
5253
B8N
B8P
AV
DD
FSADJ
REFIO
N.C.
DACREF
AGND
AV
DD
IOUTP
IOUTN
AV
DD
AGND
AGND
AV
DDAVDD
B11N
B11P
B12N
B12P
B13N
B13P
DGND
DV
DD
SEL0
N.C.
35
36
37
N.C.
N.C.
N.C.
DV
DD
DGND
N.C
N.C
N.C
VCLK
CLKGND
CLKN
CLKP
CLKGND
N.C
B0N
B0P
B1N
48 B10P
B1P
64
B4N
656667
B2P
B3N
B3P
68
B2N
2322212019 2726252418 2928 323130
AGND
N.C.
3433
49
50
B9P
B10N
51 B9N
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
PD 17
MAX5887
Pin Configuration
*EP = Exposed paddle.
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characteriza-
tion. Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDD, VCLK to AGND................................-0.3V to +3.9V
AV
DD
, DVDD, VCLK to DGND ...............................-0.3V to +3.9V
AVDD, DVDD, VCLK to CLKGND...........................-0.3V to +3.9V
AGND, CLKGND to DGND....................................-0.3V to +0.3V
DACREF, REFIO, FSADJ to AGND.............-0.3V to AVDD+ 0.3V
IOUTP, IOUTN to AGND................................-1V to AVDD+ 0.3V
CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V
B0P/B0N–B13P/B13N, SEL0,
PD to DGND...........................................-0.3V to DV
DD
+ 0.3V
Continuous Power Dissipation (TA= +70°C)
68-Pin QFN-EP (derate 41.7mW/°C above +70°C) ......3333mW
Thermal Resistance (
θ
JA
)..............................................+24°C/W
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
PARAMETER
CONDITIONS
STATIC PERFORMANCE
Resolution 14 Bits
Integral Nonlinearity INL Measured differentially
LSB
Differential Nonlinearity
DNL Measured differentially
LSB
Offset Error OS
Offset Drift
Full-Scale Gain Error GE
FS
External reference, TA ≥ +25°C
Internal reference
Gain Drift
External reference
Full-Scale Output Current I
OUT
(Note 1) 2 20 mA
Min Output Voltage Single ended
V
Max Output Voltage Single ended 1.1 V
Output Resistance R
OUT
1MΩ
Output Capacitance C
OUT
5pF
DYNAMIC PERFORMANCE
Output Update Rate f
CLK
1 500
Noise Spectral Density
dB FS/
Hz
f
OUT
= 1MHz, 0dB FS 88
f
OUT
= 1MHz, -6dB FS 89
Spurious-Free Dynamic Range to
Nyquist
SFDR
f
OUT
= 1MHz, -12dB FS 80
dBc
SYMBOL
MIN TYP MAX UNITS
±0.8
±0.5
-0.025 ±0.01 +0.025 % FS
-3.5 +1.5 % FS
±100
±50 ppm/°C
±50
ppm/°C
-0.5
f
= 100MHz f
CLK
f
= 200MHz f
CLK
f
= 100MHz
CLK
= 16MHz, -12dB FS -157
OUT
= 80MHz, -12dB FS -157
OUT
Msps
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characteriza-
tion. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
81
76
71
TA ≥ +25°C
69 76
72
64
66
63
65
Spurious-Free Dynamic Range to
Nyquist
SFDR
59
dBc
-85
2-Tone IMD TTIMD
-61
dBc
4-Tone IMD, 1MHz Frequency
Spacing, GSM Model
FTIMD
-78 dBc
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
WCDMA Model
ACLR
f
CLK
=
184.32MHz
f
OUT
= 61.44MHz 72 dB
Output Bandwidth
(Note 2)
MHz
REFERENCE
Internal Reference Voltage Range
V
REFIO
V
Reference Voltage Drift
ppm/°C
Reference Input Compliance
Range
0.1
V
Reference Input Resistance R
REFIO
10 kΩ
ANALOG OUTPUT TIMING
Output Fall Time t
FALL
90% to 10% (Note 3)
ps
Output Rise Time t
RISE
10% to 90% (Note 3)
ps
Output Voltage Settling Time
Output settles to 0.025% FS (Note 3) 11 ns
Output Propagation Delay t
PD
(Note 3) 1.8 ns
Glitch Energy 1
pV-s
I
OUT
= 2mA 30
Output Noise N
OUT
I
OUT
= 20mA 30
pA/√Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time t
SETUP
ns
Data to Clock Hold Time t
HOLD
1.8 ns
f
= 100MHz
CLK
f
= 200MHz
CLK
f
= 500MHz
CLK
f
= 100MHz
CLK
f
= 200MHz
CLK
f
= 300MHz f
CLK
f
= 10MHz, -12dB FS
OUT
= 30MHz, -12dB FS
f
OUT
f
= 10MHz, -12dB FS
OUT
f
= 16MHz, -12dB FS,
OUT
f
= 50MHz, -12dB FS
OUT
= 80MHz, -12dB FS
f
OUT
f
= 10MHz, -12dB FS
OUT
f
= 30MHz, -12dB FS
OUT
f
= 50MHz, -12dB FS
OUT
= 80MHz, -12dB FS
f
OUT
f
= 9MHz, -6dB FS,
OUT1
f
= 10MHz, -6dB FS
OUT2
f
= 79M H z, -6dB FS,
OU T 1
= 80M H z, -6dB FS
f
OU T 2
= 32MHz, -12dB FS
OUT
BW
-1dB
TCO
REF
V
REFIOCR
t
SETTLE
Referenced to rising edge of clock (Note 4) -0.8
Referenced to rising edge of clock (Note 4)
450
1.12 1.22 1.32
±50
375
375
1.25
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characteriza-
tion. Typical values are at T
A
= +25°C.)
PARAMETER
CONDITIONS
UNITS
Data Latency 4
Clock
cycles
Minimum Clock Pulse Width High
t
CH
CLKP, CLKN 0.9 ns
Minimum Clock Pulse Width Low
t
CL
CLKP, CLKN 0.9 ns
LVDS LOGIC INPUTS (B0N–B13N, B0P–B13P)
Differential Input Logic High V
IH
100 mV
Differential Input Logic Low V
IL
mV
Common-Mode Voltage Range V
COM
V
Differential Input Resistance R
IN
85
125 Ω
Input Capacitance C
IN
5pF
CMOS LOGIC INPUTS (PD, SEL0)
Input Logic High V
IH
0.7 ✕
V
Input Logic Low V
IL
0.3 ✕
V
Input Leakage Current I
IN
-15 +15 µA
Input Capacitance C
IN
5pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
Differential Input Voltage Swing V
CLK
Square wave
V
P-P
Differential Input Slew Rate SR
CLK
(Note 5)
V/µs
Common-Mode Voltage Range V
COM
1.5
V
Input Resistance R
CLK
5kΩ
Input Capacitance C
CLK
5pF
POWER SUPPLIES
Analog Supply Voltage Range AV
DD
3.3
V
Digital Supply Voltage Range DV
DD
3.3
V
Clock Supply Voltage Range V
CLK
3.3
V
f
CLK
= 100Msps, f
OUT
= 1MHz 27
Analog Supply Current I
AVDD
Power-down 0.3
mA
f
CLK
= 100Msps, f
OUT
= 1MHz 6.4 mA
Digital Supply Current I
DVDD
Power-down 10 µA
f
CLK
= 100Msps, f
OUT
= 1MHz 5.5 mA
Clock Supply Current I
VCLK
Power-down 10 µA
SYMBOL
MIN TYP MAX
-100
1.125 1.375
100
DV
DD
DV
DD
≥1.5
≥0.5
>100
±20%
3.135
3.135
3.135
3.465
3.465
3.465
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
_______________________________________________________________________________________ 5
Note 1: Nominal full-scale current I
OUT
= 32 ✕ I
REF
.
Note 2: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5887.
Note 3: Parameter measured single ended into a 50Ω termination resistor.
Note 4: Parameter guaranteed by design.
Note 5: A differential clock input slew rate of >100V/µs is required to achieve the specified dynamic performance.
Note 6: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
PARAMETER
CONDITIONS
UNITS
f
CLK
= 100Msps, f
OUT
= 1MHz
Power Dissipation P
DISS
Power-down 1
mW
Power-Supply Rejection Ratio PSRR
-1 +1
% FS/V
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characteriza-
tion. Typical values are at T
A
= +25°C.)
Typical Operating Characteristics
(AVDD= DVDD= VCLK = 3.3V, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA, TA= +25°C, unless otherwise noted.)
0
30
20
10
40
50
60
70
80
90
100
02010 30 40 50
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 100MHz)
MAX5887 toc01
f
OUT
(MHz)
SFDR (dBc)
0dB FS
-6dB FS
-12dB FS
0
30
20
10
40
50
60
70
80
90
100
10 4020 30 60 7050 80 90 100
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 200MHz)
MAX5887 toc02
f
OUT
(MHz)
SFDR (dBc)
0dB FS
-12dB FS
-6dB FS
0
30
20
10
40
50
60
70
80
90
100
5 10555 155 205 255
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 500MHz)
MAX5887 toc03
f
OUT
(MHz)
SFDR (dBc)
-6dB FS
0dB FS
-12dB FS
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
5987610
13
1211 14
2-TONE INTERMODULATION DISTORTION
(f
CLK
= 100MHz)
MAX5887 toc04
f
OUT
(MHz)
OUTPUT POWER (dBm)
A
OUT
= -6dB FS
BW = 9MHz
f
T1
= 9.0252MHz
f
T2
= 10.0417MHz
fT1 fT2
2 x fT1 - f
T2
2 x fT2 - f
T1
-50
-60
-80
-70
-90
-100
10
2-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 200MHz)
MAX5887 toc05
f
OUT
(MHz)
TWO-TONE IMD (dBc)
40
20 30 50 60
80
70
-12dB FS
-6dB FS
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
75 79 8076 77 78 81 82 83 84
2-TONE INTERMODULATION DISTORTION
(f
CLK
= 500MHz)
MAX5887 toc06
f
OUT
(MHz)
OUTPUT POWER (dBm)
A
OUT
= -6dB FS
BW = 9MHz
f
T1
= 79.095MHz
f
T2
= 80.3223MHz
2 x fT1 - f
T2
2 x fT2 - f
T1
fT1
fT2
SYMBOL
AVDD = VCLK = DVDD = 3.3V ±5% (Note 6)
MIN TYP MAX
130
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD= DVDD= VCLK = 3.3V, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA, TA= +25°C, unless otherwise noted.)
50
58
66
74
82
90
SFDR vs. TEMPERATURE
(f
CLK
= 300MHz, A
OUT
= -6dB FS, I
OUT
= 20mA)
MAX5887 toc08
TEMPERATURE (°C)
SFDR (dBc)
-40 10-15 6035 85
f
OUT
= 120MHz
f
OUT
= 10MHz
f
OUT
= 40MHz
f
OUT
= 80MHz
0
20
40
60
80
100
SFDR vs. OUTPUT FREQUENCY
(f
CLK
= 300MHz, A
OUT
= -6dB FS)
MAX5887 toc07
f
OUT
(MHz)
SFDR (dBc)
06030 12090 150
I
OUT
= 20mA
I
OUT
= 10mA
I
OUT
= 5mA
-1.0
-0.6
-0.8
0
-0.2
-0.4
0.4
0.2
1.0
0.8
0.6
DIFFERENTIAL NONLINEARTIY
vs. DIGITAL INPUT CODE
MAX5887 toc10
DIGITAL INPUT CODE
DNL (LSB)
0
100002000 6000 18000
14000
-1.5
-0.9
-1.2
-0.6
0
-0.3
0.3
1.2
0.9
0.6
1.5
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5887 toc9
DIGITAL INPUT CODE
INL (LSB)
0 60002000 10000 1800014000
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
26 3028 3432 36 38
8-TONE MULTITONE POWER RATIO PLOT
(f
CLK
= 300MHz, f
CENTER
= 31.9702MHz)
MAX5887 toc11
f
OUT
(MHz)
OUTPUT POWER (dBm)
fT2
f
T6
fT3
f
T7
fT4
f
T8
f
T1
f
T5
f
T1
= 28.0151MHz
f
T2
= 29.0405MHz
f
T3
= 30.0659MHz
f
T4
= 31.0181MHz
f
T5
= 33.06881MHz
f
T6
= 34.0209MHz
f
T7
= 35.0464MHz
f
T8
= 36.0718MHz
A
OUT
= -18dB FS
BW = 12MHz
80
120
160
200
240
280
POWER DISSIPATION vs. CLOCK FREQUENCY
(f
OUT
= 10MHz, A
OUT
= 0dB FS, I
OUT
= 20mA)
MAX5887 toc12
f
CLK
(MHz)
POWER DISSIPATION (mW)
100 300200 400 500
120
125
135
130
140
145
150
POWER DISSIPATION vs. SUPPLY VOLTAGE
(f
CLK
= 100MHz, f
OUT
= 10MHz, IFS = 20mA)
MAX5887 toc13
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
3.135 3.3003.2453.190 3.355 3.410 3.465
EXTERNAL REFERENCE
INTERNAL REFERENCE
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