Rainbow Electronics MAX5858 User Manual

General Description

The MAX5858 dual, 10-bit, 300Msps digital-to-analog converter (DAC) provides superior dynamic performance in wideband communication systems. The MAX5858 integrates two 10-bit DAC cores, 2x/4x programmable digital interpolation filters, and a 1.24V reference. The MAX5858 supports single-ended and differential modes of operation. The MAX5858 dynamic performance is maintained over the entire power-supply operating range of 2.7V to 3.3V. The analog outputs support a compliance voltage of -1.0V to +1.25V.

The 4x/2x programmable interpolation filters feature excellent passband distortion and noise performance. Interpolating filters minimize the design complexity of analog reconstruction filters while lowering data bus and clock speeds of the digital interface. To reduce the I/O pin count, the DAC can also operate in interleave data mode. This allows the MAX5858 to be updated on a single 10-bit bus.

The MAX5858 features digital control of channel gain matching to within ±0.4dB in 16 0.05dB steps. Channel matching improves sideband suppression in analog quadrature modulation applications. The on-chip 1.24V bandgap reference includes a control amplifier that allows external full-scale adjustments of both channels through a single resistor. The internal reference can be disabled and an external reference may be applied for high-accuracy applications.

The MAX5858 features full-scale current outputs of 2mA to 20mA and operates from a 2.7V to 3.3V single supply. The DAC supports three modes of power-control operation: normal, low-power standby, and complete power-down. In power-down mode, the operating current is reduced to 1µA.

The MAX5858 is packaged in a 48-pin TQFP with exposed paddle (EP) for enhanced thermal dissipation and is specified for the extended (-40°C to +85°C) temperature range.

Applications

Communications

SatCom, LMDS, MMDS, HFC, DSL, WLAN, Point-to-Point Microwave Links

Wireless Base Stations

Direct Digital Synthesis

Instrumentation/ATE

Features

♦ 10-Bit Resolution, Dual DAC

♦ 300Msps Update Rate

♦ Integrated 4x/2x Interpolating Filters

♦ 2.7V to 3.3V Single Supply

♦ Full Output Swing and Dynamic Performance at

2.7V Supply

♦ Superior Dynamic Performance

75dBc SFDR at f

OUT

= 20MHz

UMTS ACLR = 63dB at f

OUT

= 30.7MHz

♦ Programmable Channel-Gain Matching

♦ Integrated 1.24V Low-Noise Bandgap Reference

♦ Single-Resistor Gain Control

♦ Interleave Data Mode

♦ Differential Clock Input Modes

♦ EV Kit Available—MAX5858 EV Kit

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with

4x/2x/1x Interpolation Filters

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2879; Rev 0; 7/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Pin Configuration

*EP = Exposed paddle.

PART TEMP RANGE PIN-PACKAGE

MAX5858ECM -40°C to +85°C 48 TQFP-EP*

39404142434445464748

DGND

OUTPA

DB7

DB6

OUTNA

MAX5858

DB5

TQFP-EP

DA9/PD

DA8/DACEN

DA7/F2EN

DA6/F1EN

DA5/G3

DGND

DA4/G2

DA3/G1

DA2/G0

DA1

DA0

NOTE: EXPOSED PADDLE CONNECTED TO GND.

DB8

DB9

13 14 15 16 17 18 19 20 21 22

AGND

OUTPB

DGND

OUTNB

CLK

N.C.

REFR

IDE

DB4

REFO

REN

I.C.

CGND

CLKXN

CLKXP

CGND

I.C.

DB0

DB1

DB3

DB2

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 165Msps, no interpolation, external reference, V

REF

= 1.2V,

= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C guaranteed by

production test. T

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AVDD, DVDD, CVDDto AGND, DGND, CGND .........-0.3V to +4V

DA9–DA0, DB9–DB0, CW, REN to AGND,

DGND, CGND .......................................................-0.3V to +4V

IDE to AGND, DGND, CGND...................-0.3V to (DV

+ 0.3V)

CLKXN, CLKXP to CGND.........................................-0.3V to +4V

OUTP_, OUTN_ to AGND.......................-1.25V to (AV

+ 0.3V)

CLK to DGND ..........................................-0.3V to (DVDD+ 0.3V)

REFR, REFO to AGND .............................-0.3V to (AV

+ 0.3V)

AGND to DGND, DGND to CGND,

AGND to CGND..................................................-0.3V to +0.3V

Maximum Current into Any Pin

(excluding power supplies) ............................................±50mA

Continuous Power Dissipation (T

= +70°C)

48-Pin TQFP-EP (derate 36.2mW/°C above +70°C) ....2.898W

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

STATIC PERFORMANCE

Resolution 10 Bits

Integral Nonlinearity INL RL = 0 -1.25 ±0.5 +1.25 LSB

Differential Nonlinearity DNL Guaranteed monotonic, RL = 0 -0.75 ±0.25 +0.75 LSB

Offset Error V

Gain Error (See Gain Error Parameter Definitions Section)

DYNAMIC PERFORMANCE

Maximum Output DAC Update Rate

Glitch Impulse 5 pV-s

Spurious-Free Dynamic Range to Input Update Rate Nyquist

Spurious-Free Dynamic Range Within a Window

Multitone Power Ratio, 8 Tones, 300kHz Spacing

Adjacent Channel Leakage Ratio with UMTS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DAC

SFDR

MTPR f

ACLR f

Internal reference (Note 1) -9 ±1.5 +10

External reference -5 ±1.5 +7

= 165Msps

DAC

= 300Msps,

DAC

2x interpolation

= 200Msps, 2x interpolation;

DAC

= 40MHz, span = 20MHz

OUT

= 165Msps, f

DAC

span = 4MHz

= 165Msps, f

DAC

=122.88Msps, f

DAC

OUT

-0.5 ±0.1 +0.5 LSB

300 Msps

= 5MHz,

OUT

≥ +25°C

= 20MHz 75

OUT

= 40MHz 65

OUT

= 60MHz 63

OUT

= 5MHz 76

OUT

= 40MHz 78

OUT

= 60MHz 70

OUT

= 5MHz,

= 20MHz 76 dBc

= 30.72MHz 63 dB

69 76

78 85

dBc

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with

4x/2x/1x Interpolation Filters

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 165Msps, no interpolation, external reference, V

REF

= 1.2V,

= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C guaranteed by

production test. T

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

Total Harmonic Distortion to Nyquist

Noise Spectral Density N

Output Channel-to-Channel Isolation

Gain Mismatch Between Channels

Phase Mismatch Between Channels

Wideband Output Noise 50 pA/√Hz

ANALOG OUTPUT

Full-Scale Output Current Range I

Output Voltage Compliance Range

Output Leakage Current Power-down or standby mode -5 +5 µA

REFERENCE

Reference Output Voltage V

Output-Voltage Temperature Drift TCV

Reference Output Drive Capability

Reference Input Voltage Range REN = AV

Reference Supply Rejection 0.2 mV/V

Current Gain IFS/I

INTERPOLATION FILTER (2x interpolation)

Passband Width

Stopband Rejection

Group Delay 18

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

THD f

REF0

REF

OUT

0.5f

DAC

= 165Msps; f

DAC

= 165Msps; f

DAC

= 5MHz 80 dB

OUT

= 5MHz ±0.05 dB

OUT

= 5MHz ±0.15 Degrees

OUT

REN = AGND 1.14 1.24 1.32 V

-0.005dB 0.398

-0.01dB 0.402

-0.1dB 0.419

-3dB 0.478

0.604f

0.600f

0.594f

0.532f

/ 2 to 1.396f

DAC

/ 2 to 1.400f

DAC

/ 2 to 1.406f

DAC

/ 2 to 1.468f

DAC

OUT

= 5MHz -72 dB

= 5MHz -143 dBm/Hz

220mA

-1.00 +1.25 V

±50 ppm/°C

50 µA

0.10 1.25 V

32 mA/mA

/ 2 74

DAC

/ 2 62

DAC

/ 2 53

DAC

/ 2 14

DAC

MHz/

MHz

Data

clock

cycles

Impulse Response Duration 22

Data

clock

cycles

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 165Msps, no interpolation, external reference, V

REF

= 1.2V,

= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C guaranteed by

production test. T

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

INTERPOLATION FILTER (4x interpolation)

Passband Width

Stopband Rejection

Group Delay 22

Impulse Response Duration 27

LOGIC INPUTS (IDE, CW, REN, DA9–DA0, DB9–DB0)

Digital Input-Voltage High V

Digital Input-Voltage Low V

Digital Input-Current High I

Digital Input-Current Low I

Digital Input Capacitance C

DIGITAL OUTPUTS (CLK)

Digital Output-Voltage High V

Digital Output-Voltage Low V

DIFFERENTIAL CLOCK INPUT (CLKXP, CLKXN)

Clock Input Internal Bias CV

Differential Clock Input Swing 0.5 V Clock Input Impedance Single-ended clock drive 5 kΩ

TIMING CHARACTERISTICS

Output Settling Time t

Output Rise Time 10% to 90% (Note 2) 2.5 ns

Output Fall Time 90% to 10% (Note 2) 2.5 ns

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

-0.005dB 0.200

0.5f

OUT

DATA

-0.01dB 0.201

DAC

-0.1dB 0.210

-3dB 0.239

0.302f

0.300f

0.297f

0.266f

VIH = 2V -1 +1 µA

VIL = 0.8V -1 +1 µA

SOURCE

SINK

No interpolation 165

2x interpolation 150Input Data Rate f

4x interpolation 75

To ±0.1% error band (Note 2) 11 ns

/ 2 to 1.698f

DAC

/ 2 to 1.700f

DAC

/ 2 to 1.703 f

DAC

/ 2 to 1.734f

DAC

= 0.5mA, Figure 1

/ 2 74

DAC

/ 2 63

DAC

/ 2 53

DAC

/ 2 14

DAC

3pF

0.9 ×

0.8 V

0.1 ×

/ 2 V

MHz/

MHz

Data

clock

cycles

Data

clock

cycles

P-P

Msps

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with

4x/2x/1x Interpolation Filters

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 165Msps, no interpolation, external reference, V

REF

= 1.2V,

= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C guaranteed by

production test. T

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

DATA-to-CLK Rise Setup Time t

DATA-to-CLK Rise Hold Time t

DATA-to-CLK Fall Setup Time t

DATA-to-CLK Fall Hold Time t Control Word to CW Fall Setup

Time

Control Word to CW Fall Hold Time

CW High Time 5ns CW Low Time 5ns

DACEN Rise-to-V

PD Fall-to-V

Clock Frequency at CLKXP/CLKXN Input

CLKXP/CLKXN Differential Clock Input to CLK Output Delay

Minimum CLKXP/CLKXN Clock High Time

Minimum CLKXP/CLKXN Clock Low Time

POWER REQUIREMENTS

Analog Power-Supply Voltage AV

Analog Supply Current I

Digital Power-Supply Voltage DV

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

(Note 3) 1.5 ns

(Note 3) 0.4 ns

(Note 3) 1.7 ns

(Note 3) 1.1 ns

External reference 0.5 ms

Differential clock 300 MHz

(Note 4) 45 49 mA

Stable t

OUT

Stable t

OUT

DCSR

DCHR

DCSF

DCHF

CWS

CWH

STB

PDSTB

DAC

CXD

CXH

CXL

AVDD

2.5 ns

0.7 µs

4.6 ns

1.5 ns

2.7 3.3 V

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 165Msps, no interpolation, external reference, V

REF

= 1.2V,

= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C guaranteed by

production test. T

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

Note 1: Including the internal reference voltage tolerance. Note 2: Measured single ended with 50Ω load and complementary output connected to ground. Note 3: Guaranteed by design, not production tested. Note 4: f

OUT

= 5MHz.

Note 5: All digital inputs at 0 or DV

. Clock signal disabled.

Figure 1. Load Test Circuit for CLK Outputs

Digital Supply Current (Note 4) I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Clock Power-Supply Voltage CV

Clock Supply Current (Note 4) I

DAC

DVDD

CVDD

DAC

interpolation

Standby Current I

STANDBY

Power-Down Current I

Total Power Dissipation P

TOT

(Note 5) 4.4 4.8 mA

(Note 5) 1 µA

DAC

= 60Msps

= 165Msps

= 200Msps

= 60Msps 25

= 165Msps 69 80

= 200Msps, 2x interpolation or 4x

= 60Msps

= 165Msps

= 200Msps

No interpolation 34

2x interpolation 75

4x interpolation 72

No interpolation 54 61

2x interpolation 146

4x interpolation 140

2x interpolation 172 186

4x interpolation 165 178

2.7 3.3 V

80 94

No interpolation 312

2x interpolation 435f

4x interpolation 426

No interpolation 504 570

2x interpolation 780

4x interpolation 762

2x interpolation 891

4x interpolation 870

TO OUTPUT

5pF

0.5mA

1.6V

0.5mA

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with

4x/2x/1x Interpolation Filters

_______________________________________________________________________________________ 7

Typical Operating Characteristics

(AVDD= DVDD= CVDD= 3V ±10%, AGND = DGND = CGND = 0, external reference = 1.2V, no interpolation, IFS= 20mA, differential output, T

= +25°C, unless otherwise noted.)

INL (LSB)

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE

0.5

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.5 0 150 300 450 600 750 900 1050

DIGITAL INPUT CODE

POWER DISSIPATION

vs. SAMPLING RATE

1200

= 5MHz

OUT

1000

800

600

POWER DISSIPATION (mW)

400

200

0 300

2x INTERPOLATION

4x INTERPOLATION

10050 150 200 250

SAMPLING RATE (MHz)

RL = 0

MAX5858 toc01

MAX5858 toc04

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE

0.30

0.20

0.10

INL (LSB)

-0.10

-0.20

-0.30 0 150 300 450 600 750 900 1050

DIGITAL INPUT CODE

POWER DISSIPATION

vs. SUPPLY VOLTAGE

1200

4x INTERPOLATION

= 200MHz

1000

POWER DISSIPATION (mW)

CLK

= 5MHz

OUT

800

600

400

200

2.7 3.33.2 SUPPLY VOLTAGE (V)

2x INTERPOLATION

= 200MHz

CLK

= 5MHz

OUT

NO INTERPOLATION

= 165MHz

CLK

= 5MHz

OUT

2.92.8 3.0 3.1

RL = 0

MAX5858 toc02

MAX5858 toc05

POWER DISSIPATION

vs. SAMPLING RATE

550

= 5MHz

OUT

500

450

400

350

300

POWER DISSIPATION (mW)

250

200

NO INTERPOLATION

0 170

6834 102 136

SAMPLING RATE (MHz)

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

1.28

1.27

1.26

1.25

1.24

1.23

1.22

INTERNAL REFERENCE VOLTAGE (V)

1.21

1.20

2.7 3.33.2

2.92.8 3.0 3.1

SUPPLY VOLTAGE (V)

MAX5858 toc03

MAX5858 toc06

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

1.28

1.27

1.26

1.25

1.24

1.23

1.22

INTERNAL REFERENCE VOLTAGE (V)

1.21

1.20

-40 85

10-15 35 60

TEMPERATURE (°C)

MAX5858 toc07

DYNAMIC RESPONSE RISE TIME

10ns/div

MAX5858 toc08

RL = 50Ω SINGLE ENDED

200mV/div

DYNAMIC RESPONSE FALL TIME

RL = 50Ω SINGLE ENDED

10ns/div

MAX5858 toc09

200mV/div

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= DVDD= CVDD= 3V ±10%, AGND = DGND = CGND = 0, external reference = 1.2V, no interpolation, IFS= 20mA, differential output, T

= +25°C, unless otherwise noted.)

100

0 102030405060708090

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(NO INTERPOLATION, f

DAC

= 165MHz)

MAX5858 toc10

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

OUT

= 0dB FS

OUT

= -12dB FS

OUT

= -6dB FS

100

035

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(NO INTERPOLATION, f

DAC

= 65MHz)

MAX5858 toc11

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

20151053025

OUT

= 0dB FS

OUT

= -6dB FS

OUT

= -12dB FS

100

080

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(2x INTERPOLATION, f

DAC

= 300MHz)

MAX5858 toc12

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

40302010 706050

OUT

= 0dB FS

OUT

= -6dB FS

OUT

= -12dB FS

100

0 5 10 15 20 25 30 35 40 45

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(2x INTERPOLATION, f

DAC

= 165MHz)

MAX5858 toc13

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

OUT

= -6dB FS

OUT

= 0dB FS

OUT

= -12dB FS

100

040

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(4x INTERPOLATION, f

DAC

= 300MHz)

MAX5858 toc14

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

2015105353025

OUT

= -6dB FS

OUT

= 0dB FS

OUT

= -12dB FS

100

021

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(4x INTERPOLATION, f

DAC

= 165MHz)

MAX5858 toc15

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

129631815

OUT

= 0dB FS

OUT

= -12dB FS

OUT

= -6dB FS

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with

4x/2x/1x Interpolation Filters

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

(AVDD= DVDD= CVDD= 3V ±10%, AGND = DGND = CGND = 0, external reference = 1.2V, no interpolation, IFS= 20mA, differential output, T

= +25°C, unless otherwise noted.)

100

-40 85

SPURIOUS-FREE DYNAMIC RANGE

vs. TEMPERATURE (NO INTERPOLATION,

DAC

= 165MHz, f

OUT

= 5MHz)

MAX5858 toc16

TEMPERATURE (°C)

SFDR (dBc)

-10-15 35 60

OUT

= 0dB FS

OUT

= -6dB FS

OUT

= -12dB FS

100

0 102030405060708090

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(NO INTERPOLATION, f

DAC

= 165MHz)

MAX5858 toc17

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

TA = -10°C

TA = +25°C

TA = +85°C

OUT

= 0dB FS

-100

-60

-70

-80

-90

-40

-50

-20

-30

-10

7.7 11.7

FFT PLOT

(±2MHz WINDOW)

MAX5858 toc18

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

9.79.28.78.2 11.210.710.2

DAC

= 165MHz

OUT

= 9.7MHz

OUT

= -6dB FS

-119

-110

-100

-60

-70

-80

-90

-40

-50

-20

-30

-10

8.25

16.50

24.75

33.00

41.25

49.50

57.75

66.00

74.25

82.50

FFT PLOT FOR NYQUIST WINDOW

(NO INTERPOLATION, f

DAC

= 165MHz,

OUT

= 10MHz, A

OUT

= 0dB FS)

MAX5858 toc19

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

-119

-110

-100

-60

-70

-80

-90

-40

-50

-20

-30

-10

0 102030405060708090100

FFT PLOT FOR DAC UPDATE NYQUIST

WINDOW (100MHz) (2x INTERPOLATION,

DAC

= 200MHz, f

OUT

= 10MHz, A

OUT

= 0dB FS)

MAX5858 toc20

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

-119

-110

-100

-60

-70

-80

-90

-40

-50

-20

-30

-10

0 102030405060708090100

FFT PLOT FOR DAC UPDATE NYQUIST

WINDOW (100MHz) (4x INTERPOLATION,

DAC

= 200MHz, f

OUT

= 10MHz, A

OUT

= 0dB FS)

MAX5858 toc21

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters

10 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= DVDD= CVDD= 3V ±10%, AGND = DGND = CGND = 0, external reference = 1.2V, no interpolation, IFS= 20mA, differential output, T

= +25°C, unless otherwise noted.)

-100

-30

-40

-10

-20

-70

-80

-90

-50

-60

4.5 4.7 4.9 5.1 5.3 5.5

2-TONE IMD PLOT

(NO INTERPOLATION, f

DAC

= 165MHz)

MAX5858 toc22

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

OUT

= -6dB FS

BW = 1MHz

fT1 = 4.9448MHz f

= 5.0656MHz

2 x fT1 - f

2 x fT2 - f

-100

-30

-40

-10

-20

-70

-80

-90

-50

-60

18.5 19.0 19.5 20.0 20.5 21.0 21.5

8-TONE MTPR PLOT (NO INTERPOLATION,

DAC

= 165MHz, f

CENTER

= 19.9503MHz)

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

MAX5858 toc23

OUT

= 18dB FS

BW = 3MHz

fT1 = 18.8022MHz fT5 = 20.2524MHz f

= 19.0237MHz fT6 = 20.5344MHz

= 19.2654MHz fT7 = 20.8365MHz

= 19.6481MHz fT8 = 21.1386MHz

-100

-30

-40

-10

-20

-70

-80

-90

-50

-60

28.5 29.0 29.5 30.0 30.5 31.0 31.5

8-TONE MTPR PLOT (4x INTERPOLATION,

DAC

= 286.4MHz, f

CENTER

= 29.9572MHz)

MAX5858 toc24

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

OUT

= 18dB FS

BW = 3MHz

fT1 = 28.7597MHz fT5 = 30.2281MHz f

= 29.1008MHz fT6 = 30.5952MHz

= 29.3628MHz fT7 = 30.8924MHz

= 29.6862MHz fT8 = 31.1546MHz

-100

-30

-40

-20

-10

-70

-80

-90

-60

-50

-1

1.00

9.15

17.30

25.25

33.60

41.75

49.90

58.05

66.20

74.35

82.50

8-TONE MTPR PLOT FOR NYQUIST WINDOW

(NO INTERPOLATION, f

DAC

= 165MHz,

CENTER

= 19.9569MHz, A

OUT

= -18dB FS)

MAX5858 toc25

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

MTPR = 76dBc

-110

-40

-50

-30

-20

-80

-90

-100

-70

-60

-10

1.0

15.2

28.6

42.9

57.2

71.5

85.8

100.1

114.4

128.7

143.2

8-TONE MTPR PLOT FOR DAC UPDATE

(WITHIN A NYQUIST WINDOW)

(x4 INTERPOLATION, f

DAC

= 286.4MHz, f

CENTER

= 20MHz,

INPUT TONES SPACED 300kHz APART,A

OUT

= -18dB FS)

MAX5858 toc26

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

A B

35.8MHz

A: IN-BAND-RANGE B: OUT-OF-BAND RANGE

-125

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-25

0 61.44

ACLR UMTS PLOT

(NO INTERPOLATION, f

DAC

= 122.88MHz,

DATA

= 122.88MHz, f

CENTER

= 30.72MHz)

MAX5858 toc27

6.14MHz/div

OUTPUT POWER (dB)

ACLR = 63dB

OUTPUT FREQUENCY (MHz)

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with

4x/2x/1x Interpolation Filters

______________________________________________________________________________________ 11

Pin Description

Typical Operating Characteristics (continued)

(AVDD= DVDD= CVDD= 3V ±10%, AGND = DGND = CGND = 0, external reference = 1.2V, no interpolation, IFS= 20mA, differential output, T

= +25°C, unless otherwise noted.)

OUTPUT POWER (dB)

ACLR WITH UMTS PLOT

(NO INTERPOLATION, f

= 122.88MHz, f

DATA

-25

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-125 0 122.88

12.288MHz/div

OUTPUT FREQUENCY (MHz)

= 122.88MHz,

DAC

CENTER

= 30.72MHz)

ACLR = 63dB

MAX5858 toc28

-25

-30

-40

-50

-60

-70

-80

-90

OUTPUT POWER (dB)

-100

-110

-120

-125

ACLR WITH UMTS PLOT

(2x INTERPOLATION, f

= 122.88MHz, f

DATA

0 61.44

6.14MHz/div

OUTPUT FREQUENCY (MHz)

= 245.76MHz,

DAC

CENTER

ACLR = 63dB

= 30.72MHz)

PIN NAME FUNCTION

Channel A Input Data Bit 9 (MSB)/Power-Down Control Bit:

1 DA9/PD

0: Enter DAC standby mode (DACEN = 0) or power up DAC (DACEN = 1). 1: Enter power-down mode.

Channel A Input Data Bit 8/DAC Enable Control Bit:

2 DA8/DACEN

0: Enter DAC standby mode with PD = 0. 1: Power up DAC with PD = 0. X: Enter power-down mode with PD = 1 (X = don’t care).

Channel A Input Data Bit 7/Second Interpolation Filter Enable Bit:

3 DA7/F2EN

0: Interpolation mode is determined by F1EN. Enable 4x interpolation mode. (F1EN must equal 1.)

Channel A Input Data Bit 6/First Interpolation Filter Enable Bit:

4 DA6/F1EN

0: Interpolation disable. 1: Enable 2x interpolation.

5 DA5/G3 Channel A Input Data Bit 5/Channel A Gain Adjustment Bit 3

6, 19, 47 DGND Digital Ground

7, 18, 48 DV

Digital Power Supply. See the Power Supplies, Bypassing, Decoupling, and Layout section.

8 DA4/G2 Channel A Input Data Bit 4/Channel A Gain Adjustment Bit 2

9 DA3/G1 Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 1

-25

-30

-40

MAX5858 toc29

-50

-60

-70

-80

-90

OUTPUT POWER (dB)

-100

-110

-120

-125

ACLR WITH UMTS PLOT

(2x INTERPOLATION, f

= 122.88MHz, f

DATA

ACLR = 63dB

0 122.88

12.288MHz/div

OUTPUT FREQUENCY (MHz)

= 245.76MHz,

DAC

CENTER

= 30.72MHz)

MAX5858 toc30

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters

12 ______________________________________________________________________________________

Pin Description (continued)

PIN NAME FUNCTION

10 DA2/G0 Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 0

11 DA1 Channel A Input Data Bit 1

12 DA0 Channel A Input Data Bit 0 (LSB)

13 DB9 Channel B Input Data Bit 9 (MSB)

14 DB8 Channel B Input Data Bit 8

15 DB7 Channel B Input Data Bit 7

16 DB6 Channel B Input Data Bit 6

17 DB5 Channel B Input Data Bit 5

20 CLK Clock Output

21 IDE

22 DB4 Channel B Input Data Bit 4

23 DB3 Channel B Input Data Bit 3

24 DB2 Channel B Input Data Bit 2

25 DB1 Channel B Input Data Bit 1

26 DB0 Channel B Input Data Bit 0 (LSB) 27 CW Active-Low Control Word Write Pulse. The control word is latched on the falling edge of CW.

28, 34 I.C. Internally Connected. Do not connect.

29, 33 CGND Clock Ground

30 CLKXP

31 CLKXN

32 CV 35 REN Active-Low Reference Enable. Connect REN to AGND to activate the on-chip 1.24V reference.

36 REFO

37, 38 N.C. No Connection. Not internally connected.

39 REFR

40, 46 AV

41 OUTNB Channel B Negative Analog Current Output

42 OUTPB Channel B Positive Analog Current Output

43 AGND Analog Ground

44 OUTNA Channel A Negative Analog Current Output

45 OUTPA Channel A Positive Analog Current Output

— EP Exposed Pad. Connect to the ground plane.

Interleave Data Mode Enable. When IDE is high, data for both DAC channels is written through port A (bits DA9–DA0). When IDE is low, channel A data is latched on the rising edge of CLK and channel B is latched on the falling edge of CLK.

Differential Clock Input Positive Terminal. Bypass CLKXP with a 0.01µF capacitor to CGND when CLKXN is in single-ended mode.

Differential Clock Input Negative Terminal. Bypass CLKXN with a 0.01µF capacitor to CGND when CLKXP is in single-ended mode.

Clock Power Supply. See the Power Supplies, Bypassing, Decoupling, and Layout section.

Reference I/O. REFO serves as the reference input when the internal reference is disabled. If the internal 1.24V reference is enabled, REFO serves as the output for the internal reference. When the internal reference is enabled, bypass REFO to AGND with a 0.1µF capacitor.

Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET between REFR and AGND. The output full-scale current is equal to 32 × V

Analog Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section.

REFO/RSET

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with

4x/2x/1x Interpolation Filters

______________________________________________________________________________________ 13

Detailed Description

The MAX5858 dual, high-speed, 10-bit, current-output DAC provides superior performance in communication systems requiring low-distortion analog-signal reconstruction. The MAX5858 combines two DACs with 2x/4x programmable digital interpolation filters, divide-by-N clock output, and an on-chip 1.24V reference. The current outputs of the DACs can be configured for differential or single-ended operation. The full-scale output current range is adjustable from 2mA to 20mA to optimize power dissipation and gain control.

The MAX5858 accepts an input data rate to 165MHz or a DAC conversion rate of 300MHz. The inputs are latched on the rising edge of the clock whereas the output latches on the following rising edge.

The two-stage digital interpolation filters are programmable to 4x, 2x, or no interpolation. When operating in 4x interpolation mode, the interpolator increases the DAC conversion by a factor of four, providing a four-

fold increase in separation between the reconstructed waveform spectrum and its first image.

The MAX5858 features three modes of operation: normal, standby, and power-down. These modes allow efficient power management. In power-down, the MAX5858 consumes only 1µA of supply current. Wake-up time from standby mode to normal DAC operation is 0.7µs.

Programming the DAC

An 8-bit control word routed through channel A’s data port programs the gain matching, interpolator configuration, and operational mode of the MAX5858. The control word is latched on the falling edge of CW. Table 1 represents the control word format and function.

The gain on channel A can be adjusted to achieve gain matching between two channels in a user’s system. The gain on channel A can be adjusted from -0.4dB to

0.35dB in steps of 0.05dB by using bits G3 to G0 (see Table 3).

Simplified Block Diagram

DA9–DA0

DB9–DB0

IDE

DVDDCVDDAV

10 10 10 10

CONTROL REGISTER

DGND CGND

INPUT

INTERPOLATION

F1EN

MAX5858

2x DIGITAL

FILTER

2x DIGITAL

FILTER

2x DIGITAL

INTERPOLATION

FILTER

2x DIGITAL

INTERPOLATION

FILTER

F2EN

1.24V REFERENCE AND CONTROL AMPLIFIER

REFO REN

CLKCLKXNCLKXP

OUTPA

10-BIT

300MHz

DAC

OUTNA

OUTPB

10-BIT

300MHz

DAC

OUTNB

AGNDREFR

SET

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters

14 ______________________________________________________________________________________

Device Power-Up and

States of Operation

At power-up, the MAX5858’s default configuration is no-interpolation mode with a gain of 0dB and a fully operational converter. In shutdown, the MAX5858 consumes only 1µA of supply current, and in standby the current consumption is 4.4mA. Wake-up time from standby mode to normal operation is 0.7µs.

Interpolation Filters

The MAX5858 features a two stage, 2x digital interpolating filter based on 43-tap and 23-tap FIR topology. F1EN and F2EN enable the interpolation filters. F1EN high enables the first filter for 2x interpolation and F2EN high enables the second filter for combined 4x interpolation. To bypass and disable both interpolation filters (no-interpolation mode or 1x mode) set F1EN = F2EN =

0. When set for 1x mode the filters are powered down and consume virtually no current. An illegal condition is defined by: F1EN = 0, F2EN = 1 (see Table 2 for configuration modes).

The programmable interpolation filters multiply the MAX5858 input data rate by a factor of 2x or 4x to separate the reconstructed waveform spectrum and the first image. The original spectral images, appearing around multiples of the DAC input data rate, are attenuated at least 60dB by the internal digital filters. This feature provides three benefits:

1) Image separation reduces complexity of analog reconstruction filters.

2) Lower input data rates eliminate board level highspeed data transmission.

3) Sin(x)/x roll-off is reduced over the effective bandwidth.

Figure 2 shows an application circuit and Figure 3 illustrates a practical example of the benefits when using the MAX5858 in 4x-interpolation mode. The example illustrates signal synthesis of a 20MHz IF with a ±10MHz bandwidth. The designer can consider three options to address the design challenge. The tradeoffs for each solution are depicted in Table 4.

Table 1. Control Word Format and Function

Table 2. Configuration Modes

Table 3. Gain Difference Setting

X = Don’t care. F1EN = 0, F2EN = 1 illegal.

MSB LSB

PD DACEN F2EN F1EN G3 G2 G1 G0 X X

CONTROL WORD FUNCTION

PD Power-Down. The part enters power-down mode if PD = 1.

DACEN DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode.

F2EN

F1EN

G3 Bit 3 (MSB) of Gain Adjust Word.

G2 Bit 2 of Gain Adjust Word.

G1 Bit 1 of Gain Adjust Word.

G0 Bit 0 (LSB) of Gain Adjust Word.

Filter Enable. When F2EN = 1 and F1EN = 1, 4x interpolation is enabled. When F2EN = 0, the interpolation mode is determined by F1EN.

Filter Enable. When F1EN = 1 and F2EN = 0, 2x interpolation is active. With F1EN = 0 and F2EN = 0, the interpolation is disabled.

MODE

No interpolation

2x interpolation

4x interpolation

Standby

Power-down

Power-up

PD DACEN F2EN

010

011

00X

1XX

01X

F1EN

GAIN ADJUSTMENT ON

CHANNEL A (dB)

+0.4 0000

0 1000

-0.35 1111

G3 G2 G1 G0

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with

4x/2x/1x Interpolation Filters

______________________________________________________________________________________ 15

Figure 2. Typical Application Circuit

Table 4. Benefits of Interpolation

SINGLE SUPPLY

2.7V TO 3.3V

FS ANALOG OUT

MAINTAINED OVER

ENTIRE SUPPLY RANGE

2.7V TO 3.3V

SINGLE 10-BIT BUS

SAVES I/O PINS

DIGITAL BASEBAND

OFDM PROCESSOR

QAM-MAPPER

DATA CLOCK OUT

= 71.6MHz

DATA

INTERLEAVE

DATA

LATCH

DATA LATCH 10-BIT

DATA LATCH

10-BIT BUS

INTERPOLATING

FILTERS

4x/2x

INTERPOLATING

FILTERS

4x/2x

CLOCK SOURCE

= 286.4MHz

DAC

DIV-4 DIV-2 DIV-1

CH-1

DAC

CH-2

DAC

AOUT1

AOUT2

OPTION SOLUTION ADVANTAGE DISADVANTAGE

• No interpolation

• 2.6x oversample

• f

DAC

= f

DATA

= 78MHz

• Low data rate

• Low clock rate

• High order filter

• Filter gain/phase match

• No interpolation

• 8x oversample

• f

DAC

= f

DATA

• Push image to f

• 4x interpolation

= 286.4MHz, f

• f

DAC

• Passband attenuation = 0.1dB

• Push image to 256MHz

= 240MHz

IMAGE

DATA

= 210MHz

= 71.6MHz

• Lower order filter

• Filter gain/phase match

• Low data rate

• Low order filter

• 60dB image attenuate

• Filter gain/phase match

• High clock rate

• High data rate

• None

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters

16 ______________________________________________________________________________________

Figure 3. MAX5858 in 4x Interpolation Mode

This example demonstrates that 4x interpolation with digital filtering yields significant benefits in reducing system complexity, improving dynamic performance and lowering cost. Data can be written to the MAX5858 at much lower speeds while achieving image attenuation greater than 60dB and image separation beyond three octaves. The main benefit is in analog reconstruc-

tion filter design. Reducing the filter order eases gain/phase matching while lowering filter cost and saving board space. Because the data rate is lowered to

71.6MHz, the setup and hold times are manageable and the clock signal source is simplified, which results in improved system reliability and lower cost.

SOLUTION 1

SOLUTION 2

SOLUTION 3

OUT

20MHz ±10MHz

OUT

20MHz

BW = ±10MHz

IMAGE

- f

DAC

OUT

48MHz

FREQUENCY AXIS NOT TO SCALE

SIMPLE ANALOG FILTER

DAC

78MHz

LOWER ORDER

ANALOG FILTER

IMAGE SEPARATION = 18MHz

LESS THAN ONE OCTAVE

HIGH ORDER ANALOG FILTER

IMAGE

+ f

DAC

OUT

108MHz

IMAGE SEPARATION = 180MHz

HIGH-SPEED CLK = 240MHz

IMAGE

DAC

210MHz

DAC

- f

240MHz

OUT

NEW FIRST IMAGE SEPARATION > 3 OCTAVES

DAC

270MHz

+ f

OUT

DIGITAL FILTER

ATTENUATION >60dB

OUT

20MHz

BW = ±10MHz

FREQUENCY AXIS NOT TO SCALE

DATA

71.6MHz

IMAGE

DAC

256MHz

- f

286MHz

OUT

DAC

316MHz

+ f

OUT

IMAGE

DAC

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with

4x/2x/1x Interpolation Filters

______________________________________________________________________________________ 17

Figure 4. Setting IFS with the Internal 1.24V Reference and the Control Amplifier

Clocking Modes

Apply an external clock to CLKXP and CLKXN at the desired DAC update rate and allowable input amplitude. CLK is an output and provides the signal necessary to synchronize the input data. CLKXP and CLKXN accept a frequency range of 0 to 300MHz (see Table

5). Maintain a low capacitive load at the CLK output (not higher than 10pF for f

CLK

of 165MHz).

Internal Reference and Control Amplifier

The MAX5858 provides an integrated 50ppm/°C, 1.24V, low-noise bandgap reference that can be disabled and overridden with an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is connected to AGND, the internal reference is selected and REFO provides a

1.24V (50µA) output. Buffer REFO with an external amplifier, when driving a heavy load.

The MAX5858 also employs a control amplifier designed to simultaneously regulate the full-scale output current (IFS) for both outputs of the devices. Calculate the output current as:

IFS= 32 ✕ I

REF

where I

REF

is the reference output current (I

REF

REFO/RSET

) and IFSis the full-scale output current.

SET

is the reference resistor that determines the amplifier output current of the MAX5858 (Figure 4). This current is mirrored into the current-source array where I

is equally distributed between matched current segments and summed to valid output current readings for the DACs.

External Reference

To disable the internal reference of the MAX5858, connect REN to AVDD. Apply a temperature-stable, external reference to drive the REFO to set the full-scale output (Figure 5). For improved accuracy and drift performance, choose a fixed output voltage reference such as the

1.24V, 25ppm/°C MAX6520 bandgap reference.

Detailed Timing

The MAX5858 accepts an input data rate up to 165MHz or the DAC conversion rate of 300MHz. The input latches on the rising edge of the clock, whereas the output latches on the following rising edge.

Figure 6 depicts the write cycle of the DACs in 4x interpolation mode. In this timing diagram, signals applied to CLKXP and CLKXN are divided by four to create the DAC’s CLK signal. The MAX5858 DAC output is updated at the rate of the clock applied to CLKXP/CLKXN.

OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS

REN

AGND

MAX4040

REFO

COMP

AGND

REF

SET

*COMPENSATION CAPACITOR (C

COMP

≈ 100nF).

AGND

SET

REFR

REF

1.24V

BANDGAP

REFERENCE

MAX5858

CURRENT-

SOURCE ARRAY

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters

18 ______________________________________________________________________________________

The MAX5858 can also operate in an interleave data mode. Pulling IDE high activates this mode. In interleave mode, data for both DAC channels is written through input port A. Channel B data is written on the falling edge of the CLK signal and then channel A data is written on the following rising edge of the CLK signal. Both DAC outputs (channel A and B) are updated simultaneously on the next following rising edge of the CLK. In interleave data mode, the maximum input data rate per channel is half of the rate in noninterleave mode. The interleave data mode is attractive in applications where lower data rates are acceptable and interfacing on a single 10-bit bus is desired (Figure 7).

Applications Information

Differential-to-Single-Ended Conversion

The MAX5858 exhibits excellent dynamic performance to synthesize a wide variety of modulation schemes, including high-order QAM modulation with OFDM.

Figure 8 shows a typical application circuit with output transformers performing the required differential-to-single-ended signal conversion. In this configuration, the MAX5858 operates in differential mode, which reduces even-order harmonics, and increases the available output power.

Table 5. Clocking Modes

Figure 5. MAX5858 with External Reference

0.1µF10µF

EXTERNAL

+1.24V

REFERENCE

MAX6520

F2EN F1EN

0 0 0 to 165 F

0 1 0 to 300 F

1 1 0 to 300 f

1 0 Illegal

FREQUENCY (f

AGND

DIFFERENTIAL CLOCK

CLKDIFF

SET

) (MHz)

REFO

REFR

REF

CLK OUTPUT

(MHz)

CLKDIFF

REN

1.24V

BANDGAP

REFERENCE

/2 f

/4 f

MAX5858

DAC RATE

)

DAC

CLKDIFF

AGND

CURRENT-

SOURCE ARRAY

INTERPOLATION

1x 82

2x 63

4x 31

MAX SIGNAL

BANDWIDTH (MHz)

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with

4x/2x/1x Interpolation Filters

______________________________________________________________________________________ 19

Figure 7. Timing Diagram for Interleave Data Mode (IDE = High)

Figure 6. Timing Diagram for Noninterleave Data Mode (IDE = Low)

CLKXN

CLKXP

CLK

DA0–DA9/

CONTROL WORD

DB0–DB9

CXD

DCSR

1–THE DIAGRAM SHOWS 4x INTERPOLATION MODE.

CXD

CWH

CWS

CONTROL WORD

N+1

DCHR

CLKXN

CLKXP

CLK

DA0–DA9

CXD

DCSR

1–THE DIAGRAM SHOWS 4x INTERPOLATION MODE.

N+1

DCSFtDCHF

CXD

N+1

N+2

DCHR

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters

20 ______________________________________________________________________________________

Differential DC-Coupled Configuration

Figure 9 shows the MAX5858 output operating in differential, DC-coupled mode. This configuration can be used in communication systems employing analog quadrature upconverters and requiring a baseband sampling, dual-channel, high-speed DAC for I/Q synthesis. In these applications, information bandwidth can extend from 10MHz down to several hundred kilohertz. DC-coupling is desirable in order to eliminate long discharge time constants that are problematic with large, expensive coupling capacitors. Analog quadrature upconverters have a DC common-mode input requirement of typically 0.7V to 1.0V. The MAX5858 differential I/Q outputs can maintain the desired full-scale frequency spectrum at the required 0.7V to 1.0V DC commonmode level when powered from a single 2.85V (±5%) supply. The MAX5858 meets this low-power requirement with minimal reduction in dynamic range while eliminating the need for level-shifting resistor networks.

Power Supplies, Bypassing,

Decoupling, and Layout

Grounding and power-supply decoupling strongly influence the MAX5858 performance. Unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications, like signal-to-noise ratio or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5858. Observe the grounding and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the power supply and filter configuration to realize optimum dynamic performance.

Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. Run high-speed signals on lines directly above the ground plane. The MAX5858 has separate analog and digital ground buses (AGND, CGND, and DGND,

Figure 8. Application with Output Transformer Performing Differential to Single-Ended Conversion

Figure 9. Application with DC-Coupled Differential Outputs

DA0–DA9

MAX5858

DB0–DB9

MAX5858

1/2

50Ω

OUTPA

100Ω

OUTNA

50Ω

OUTPB

100Ω

OUTNB

50Ω

CGNDDGNDAGND

OUTA

SINGLE ENDED

OUTB

SINGLE ENDED

DA0–DA9

DB0–DB9

1/2

MAX5858

1/2

MAX5858

CGNDDGNDAGND

50Ω

OUTPA

OUTNA

50Ω

OUTPB

OUTNB

50Ω

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with

4x/2x/1x Interpolation Filters

______________________________________________________________________________________ 21

respectively). Provide separate analog, digital, and clock ground sections on the PC board with only one point connecting the three planes. The ground connection points should be located underneath the device and connected to the exposed paddle. Run digital signals above the digital ground plane and analog/clock signals above the analog/clock ground plane. Digital signals should be kept away from sensitive analog, clock, and reference inputs. Keep digital signal paths short and metal trace lengths matched to avoid propagation delay and data skew mismatch.

The MAX5858 includes three separate power-supply inputs: analog (AV

), digital (DVDD), and clock (CVDD). Use a single linear regulator power source to branch out to three separate power-supply lines (AVDD, DVDD, CVDD) and returns (AGND, DGND, CGND). Filter each power-supply line to the respective return line using LC filters comprising ferrite beads and 10µF capacitors. Filter each supply input locally with 0.1µF ceramic capacitors to the respective return lines.

Note: To maintain the dynamic performance of the Electrical Characteristics, ensure the voltage difference between DV

, AVDD, and CVDDdoes not

exceed 150mV.

Thermal Characteristics and Packaging

Thermal Resistance

48-lead TQFP-EP:

= 37°C/W

Keep the device junction temperature below +125°C to meet specified electrical performance. Lower the power-supply voltage to maintain specified performance when the DAC update rate approaches 300Msps and the ambient temperature equals +85°C.

The MAX5858 is packaged in a 48-pin TQFP-EP package, providing greater design flexibility, increased thermal efficiency, and optimized AC performance of the DAC. The EP enables the implementation of grounding techniques, which are necessary to ensure highest performance operation.

In this package, the data converter die is attached to an EP leadframe with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the PC board with standard infrared (IR)flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP (5mm

✕ 5mm), ensures the proper attachment and grounding

of the DAC. Designing vias* into the land area and

implementing large ground planes in the PC board design will allow for highest performance operation of the DAC. Use an array of 3

✕ 3 (or greater) vias

(≤0.3mm diameter per via hole and 1.2mm pitch between via holes) for this 48-pin TQFP-EP package.

Dynamic Performance Parameter

Definitions

Adjacent Channel Leakage Ratio (ACLR)

Commonly used in combination with wideband codedivision multiple-access (WCDMA), ACLR reflects the leakage power ratio in dB between the measured power within a channel relative to its adjacent channel. ACLR provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited RF signal passes through a nonlinear device.

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of all essential harmonics (within a Nyquist window) of the input signal to the fundamental itself. This can be expressed as:

where V1is the fundamental amplitude, and V2through V

are the amplitudes of the 2nd through Nth order har-

monics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of their next-largest spectral component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dB FS with respect to the DAC’s full-scale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist.

Multitone Power Ratio (MTPR)

A series of equally spaced tones are applied to the DAC with one tone removed from the center of the range. MTPR is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequencies), which appears as the largest spur at the frequency of the missing tone in the sequence. This test can be performed with any number of input tones; however, four and eight tones are among the most common test conditions for CDMA- and GSM/EDGE-type applications.

THD V V V VN V=× ++ +

()

 



 



log ... ... /20 234 1

222 2

*Vias connect the land pattern to internal or external copper planes.

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters

22 ______________________________________________________________________________________

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in dBc of either output tone to the worst 3rd-order (or higher) IMD products.

Static Performance Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification no more negative than -1 LSB guarantees monotonic transfer function.

Offset Error

Offset error is the current flowing from positive DAC output when the digital input code is set to zero. Offset error is expressed in LSBs.

Gain Error

A gain error is the difference between the ideal and the actual full-scale output current on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. The ideal current is defined by reference voltage at V

REFO

/ I

REF

x 32.

Settling Time

The settling time is the amount of time required from the start of a transition until the DAC output settles to its new output value to within the converter’s specified accuracy.

Glitch Impulse

A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011…111 to 100…000. This occurs due to timing variations between the bits. The glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. The glitch impulse is usually specified in pV-s.

Chip Information

TRANSISTOR COUNT: 178,376

PROCESS: CMOS

MAX5858

Dual, 10-Bit, 300Msps, Current-Output DAC with

4x/2x/1x Interpolation Filters

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

48L,TQFP.EPS

Rainbow Electronics MAX5858 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual