General Description
The MAX5842 is a quad, 12-bit voltage-output, digitalto-analog converter (DAC) with an I2C™-compatible,
2-wire interface that operates at clock rates up to
400kHz. The device operates from a single 2.7V to 5.5V
supply and draws only 230µA at VDD= 3.6V. A powerdown mode decreases current consumption to less
than 1µA. The MAX5842 features three software-selectable power-down output impedances: 100kΩ, 1kΩ,
and high impedance. Other features include internal
precision Rail-to-Rail®output buffers and a power-on
reset (POR) circuit that powers up the DAC in the
100kΩ power-down mode.
The MAX5842 features a double-buffered I2C-compatible serial interface that allows multiple devices to share
a single bus. All logic inputs are CMOS-logic compatible and buffered with Schmitt triggers, allowing direct
interfacing to optocoupled and transformer-isolated
interfaces. The MAX5842 minimizes digital noise
feedthrough by disconnecting the clock (SCL) signal
from the rest of the device when an address mismatch
is detected.
The MAX5842 is specified over the extended temperature range of -40°C to +85°C and is available in a
miniature 10-pin µMAX package. Refer to the MAX5841
data sheet for the 10-bit version.
Applications
Digital Gain and Offset Adjustments
Programmable Voltage and Current Sources
Programmable Attenuation
VCO/Varactor Diode Control
Low-Cost Instrumentation
Battery-Powered Equipment
ATE
Features
♦ Ultra-Low Supply Current
230µA at V
DD
= 3.6V
280µA at VDD= 5.5V
♦ 300nA Low-Power Power-Down Mode
♦ Single 2.7V to 5.5V Supply Voltage
♦ Fast 400kHz I
2
C-Compatible 2-Wire Serial
Interface
♦ Schmitt-Trigger Inputs for Direct Interfacing to
Optocouplers
♦ Rail-to-Rail Output Buffer Amplifiers
♦ Three Software-Selectable Power-Down Output
Impedances
100kΩ, 1kΩ, and High Impedance
♦ Read-Back Mode for Bus and Data Checking
♦ Power-On Reset to Zero
♦ 10-Pin µMAX Package
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
________________________________________________________________ Maxim Integrated Products 1
Pin Configuration
Ordering Information
R
P
R
P
V
DD
µC
SDA
SCL
SDA
SDA
REF
REF
REF
SCL
SCL
V
DD
V
DD
R
S
R
S
V
DD
OUTA
OUTB
MAX5842
MAX5842
R
S
R
S
OUTC
OUTD
OUTB
OUTC
OUTD
OUTA
Typical Operating Circuit
19-2317; Rev 0; 1/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
I
2
C is a trademark of Philips Corp.
PART
MAX5842LEUB -40
TEMP
RANGE
o
C to +85oC 10 µMAX 0111 10X
MAX5842MEUB -40oC to +85oC 10 µMAX 1011 10X
PINPACKAGE
ADDRESS
µMAX
10
OUTD
9
OUTC
8
OUTB
7
OUTAGND
REFSDA
6
TOP VIEW
ADD
1
SCL
2
V
DD
MAX5842
3
4
5
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= +2.7V to +5.5V, GND = 0, V
REF
= VDD, RL= 5kΩ, CL= 200pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at V
DD
= +5V, TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, SCL, SDA to GND............................................-0.3V to +6V
OUT_, REF, ADD to GND..............................-0.3V to V
DD
+ 0.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T
A
= +70°C)
10-Pin µMAX (derate 5.6mW above +70°C) .................444mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY (NOTE 2)
Resolution N 12 Bits
Integral Nonlinearity INL (Note 3) ±2 ±16 LSB
Differential Nonlinearity DNL Guaranteed monotonic (Note 3) ±1 LSB
Zero-Code Error ZCE Code = 000 hex, VDD = 2.7V 6 40 mV
Zero-Code Error Tempco 2.3 ppm/oC
Gain Error GE Code = FFF hex -0.8 -3 %FSR
Gain-Error Tempco 0.26 ppm/oC
Power-Supply Rejection Ratio PSRR Code = FFF hex, VDD = 4.5V to 5.5V 58.8 dB
DC Crosstalk 30 µV
REFERENCE INPUT
Reference Input Voltage Range V
Reference Input Impedance 32 45 kΩ
Reference Current Power-down mode ±0.3 ±1 µA
DAC OUTPUT
Output Voltage Range No load (Note 4) 0 V
DC Output Impedance Code = 800 hex 1.2 Ω
Short-Circuit Current
Wake-Up Time
DAC Output Leakage Current
DIGITAL INPUTS (SCL, SDA)
Input High Voltage V
Input Low Voltage V
REF
VDD = 5V, V
V
= 3V, V
DD
VDD = 5V 8
V
= 3V 8
DD
Power-down mode = high impedance,
= 5.5V, V
V
DD
IH
IL
= full scale (short to GND) 42.2
OUT
= full scale (short to GND) 15.1
OUT
OUT
_ = V
DD
or GND
0V
±0.1 ±1 µA
0.7 ✕
V
DD
DD
DD
0.3 ✕
V
DD
V
V
mA
µs
V
V
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +2.7V to +5.5V, GND = 0, V
REF
= VDD, RL= 5kΩ, CL= 200pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at V
DD
= +5V, TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Hysteresis
Input Leakage Current Digital inputs = 0 or V
Input Capacitance 6pF
DIGITAL OUTPUT (SDA)
Output Logic Low Voltage V
Three-State Leakage Current I
Three-State Output Capacitance 6pF
DYNAMIC PERFORMANCE
Voltage Output Slew Rate SR 0.5 V/µs
Voltage Output Settling Time
Digital Feedthrough Code = 000 hex, digital inputs from 0 to V
Digital-to-Analog Glitch Impulse
DAC-to-DAC Crosstalk 2.4 nV-s
POWER SUPPLIES
Supply Voltage Range V
Supply Current with No Load I
Power-Down Supply Current I
TIMING CHARACTERISTICS (FIGURE 1)
Serial Clock Frequency f
Bus Free Time Between STOP
and START Conditions
START Condition Hold Time t
SCL Pulse Width Low t
SCL Pulse Width High t
Repeated START Setup Time t
Data Hold Time t
Data Setup Time t
SDA and SCL Receiving Rise
Time
SDA and SCL Receiving Fall Time t
SDA Transmitting Fall Time t
STOP Condition Setup Time t
I
OL
L
DD
DD
DDPD
SCL
t
BUF
HD,STA
LOW
HIGH
SU,STA
HD,DAT
SU,DAT
t
r
f
f
SU,STO
= 3mA 0.4 V
SINK
Digital inputs = 0 or V
To 1/2LSB code 400 hex to C00 hex or C00
hex to 400 hex (Note 5)
Major carry transition (code = 7FF hex to
800 hex and 800 hex to 7FF hex)
All digital inputs at 0 or VDD = 3.6V 230 395
All digital inputs at 0 or VDD = 5.5V 280 420
All digital inputs at 0 or VDD = 5.5V 0.3 1 µA
(Note 5) 0 300 ns
(Note 5) 0 300 ns
(Note 5)
DD
DD
0.05
✕
V
DD
±0.1 ±1µA
±0.1 ±1µA
412µs
DD
2.7 5.5 V
0 400 kHz
1.3 µs
0.6 µs
1.3 µs
0.6 µs
0.6 µs
0 0.9 µs
100 ns
20 +
0.1C
0.6 µs
0.2 nV-s
12 nV-s
b
V
µA
250 ns
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD= +5V, RL= 5kΩ.)
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +2.7V to +5.5V, GND = 0, V
REF
= VDD, RL= 5kΩ, CL= 200pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at V
DD
= +5V, TA= +25°C.) (Note 1)
Note 1: All devices are 100% production tested at TA= +25°C and are guaranteed by design for TA= T
MIN
to T
MAX
.
Note 2: Static specifications are tested with the output unloaded.
Note 3: Linearity is guaranteed from codes 115 to 3981.
Note 4: Offset and gain error limit the FSR.
Note 5: Guaranteed by design. Not production tested.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Bus Capacitance C
Maximum Duration of Suppressed
Pulse Widths
INTEGRAL NONLINEARITY
vs. INPUT CODE
4
3
2
1
0
INL (LSB)
-1
-2
-3
-4
0 4096
INPUT CODE
307220481024
(Note 5) 400 pF
b
t
SP
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
5
MAX5842 toc01
4
3
INL (LSB)
2
1
0
2.7 5.5
SUPPLY VOLTAGE (V)
050ns
5
MAX5842 toc02
4.84.13.4
4
3
INL (LSB)
2
1
0
-40 85
INTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE (°C)
MAX5842 toc03
603510-15
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
1.00
0.75
0.50
0.25
0
DNL (LSB)
-0.25
-0.50
-0.75
-1.00
0 4096
INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
0
MAX5842 toc04
-0.25
-0.50
DNL (LSB)
-0.75
-1.00
307220481024
2.7 5.5
SUPPLY VOLTAGE (V)
4.84.13.4
MAX5842 toc05
-0.25
-0.50
DNL (LSB)
-0.75
-1.00
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
0
-40 85
TEMPERATURE (°C)
MAX5842 toc06
603510-15
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(VDD= +5V, RL= 5kΩ.)
ZERO-CODE ERROR
vs. SUPPLY VOLTAGE
10
8
6
4
ZERO-CODE ERROR (mV)
2
0
2.7 5.5
SUPPLY VOLTAGE (V)
GAIN ERROR vs. TEMPERATURE
-2.0
-1.6
-1.2
-0.8
GAIN ERROR (%FSR)
-0.4
0
-40 85
TEMPERATURE (°C)
SUPPLY CURRENT vs. INPUT CODE
320
NO LOAD
4.84.13.4
603510-15
NO LOAD
ZERO-CODE ERROR
10
MAX5842 toc07
MAX5842 toc10
8
6
4
ZERO-CODE ERROR (mV)
2
0
-40 85
6
5
4
3
2
DAC OUTPUT VOLTAGE (V)
1
0
320
vs. TEMPERATURE
MAX5842 toc08
NO LOAD
603510-15
TEMPERATURE (°C)
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT (NOTE 6)
MAX5842 toc11
CODE = FFF hex
010
OUTPUT SOURCE CURRENT (mA)
8642
SUPPLY CURRENT vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
-2.0
-1.6
-1.2
-0.8
GAIN ERROR (%FSR)
-0.4
0
2.7 5.5
SUPPLY VOLTAGE (V)
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT (NOTE 6)
2.5
2.0
1.5
1.0
DAC OUTPUT VOLTAGE (V)
0.5
CODE = 400 hex
0
010
OUTPUT SINK CURRENT (mA)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
320
MAX5842 toc09
NO LOAD
4.84.13.4
MAX5842 toc12
8642
300
280
SUPPLY CURRENT (µA)
260
240
0 4096
INPUT CODE
MAX5842 toc13
300
280
SUPPLY CURRENT (µA)
260
N0 LOAD
CODE = FFF hex
240
327624571638819
-40 85
TEMPERATURE (°C)
603510-15
MAX5842 toc14
300
280
SUPPLY CURRENT (µA)
260
CODE = FFF hex
NO LOAD
240
2.7 5.5
SUPPLY VOLTAGE (V)
4.84.13.4
MAX5842 toc15
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD= +5V, RL= 5kΩ.)
SETTLING TIME
(POSITIVE)
MAX5842 toc21
2µs/div
OUT_
500mV/div
C
LOAD
= 200pF
CODE = 400 hex TO C00 hex
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
500
Z
= HIGH IMPEDANCE
OUT
NO LOAD
400
MAX5842 toc16
POWER-UP GLITCH
V
DD
MAX5842 toc17
5V
300
200
100
POWER-DOWN SUPPLY CURRENT (nA)
OUT_
TA = +25°C
0
2.7 5.5
TA = -40°C
TA = +85°C
SUPPLY VOLTAGE (V)
EXITING SHUTDOWN
C
LOAD
CODE = 800 hex
2µs/div
4.84.13.4
MAX5842 toc18
= 200pF
500mV/div
OUT_
OUT_
100µs/div
MAJOR CARRY TRANSITION
(POSITIVE)
C
= 200pF
LOAD
CODE = 7FF hex TO 800 hex
2µs/div
R
MAX5842 toc19
= 5kΩ
L
0
10mV/div
5mV/div
MAJOR CARRY TRANSITION
(NEGATIVE)
OUT_
CODE = 800 hex TO 7FF hex
2µs/div
C
LOAD
MAX5842 toc20
= 200pF
= 5kΩ
R
L
5mV/div
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(VDD= +5V, RL= 5kΩ.)
Note 6: The ability to drive loads less than 5kΩ is not implied.
OUT_
SETTLING TIME
(NEGATIVE)
C
CODE = C00 hex TO 400 hex
2µs/div
LOAD
MAX5842 toc22
= 200pF
V
OUTA
500mV/div
CROSSTALK
DIGITAL FEEDTHROUGH
SCL
OUT_
40µs/div
MAX5842 toc24
2V/div
MAX5842 toc23
C
= 200pF
LOAD
= 12kHz
f
SCL
CODE = 000 hex
2V/div
2mV/div
V
OUTB
1mV/div
4µs/div
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
8 _______________________________________________________________________________________
Detailed Description
The MAX5842 is a quad, 12-bit, voltage-output DAC
with an I2C/SMBus-compatible 2-wire interface. The
device consists of a serial interface, power-down circuitry, four input and DAC registers, four 12-bit resistor
string DACs, four unity-gain output buffers, and output
resistor networks. The serial interface decodes the
address and control bits, routing the data to the proper
input or DAC register. Data can be directly written to
the DAC register, immediately updating the device output, or can be written to the input register without
changing the DAC output. Both registers retain data as
long as the device is powered.
DAC Operation
The MAX5842 uses a segmented resistor string DAC
architecture, which saves power in the overall system
and guarantees output monotonicity. The MAX5842’s
input coding is straight binary, with the output voltage
given by the following equation:
where N = 12 (bits), and D = the decimal value of the
input code (0 to 4095).
Output Buffer
The MAX5842 analog outputs are buffered by precision, unity-gain followers that slew 0.5V/µs. Each buffer
output swings rail-to-rail, and is capable of driving 5kΩ
in parallel with 200pF. The output settles to ±0.5LSB
within 4µs.
Power-On Reset
The MAX5842 features an internal POR circuit that initializes the device upon power-up. The DAC registers
are set to zero scale and the device is powered down,
with the output buffers disabled and the outputs pulled
to GND through the 100kΩ termination resistor.
Following power-up, a wake-up command must be initiated before any conversions are performed.
Power-Down Modes
The MAX5842 has three software-controlled, lowpower, power-down modes. All three modes disable
the output buffers and disconnect the DAC resistor
strings from REF, reducing supply current draw to 1µA
and the reference current draw to less than 1µA. In
power-down mode 0, the device output is high impedance. In power-down mode 1, the device output is
internally pulled to GND by a 1kΩ termination resistor.
In power-down mode 2, the device output is internally
pulled to GND by a 100kΩ termination resistor. Table 1
shows the power-down mode command words.
Upon wake-up, the DAC output is restored to its previous value. Data is retained in the input and DAC registers during power-down mode.
Digital Interface
The MAX5842 features an I2C/SMBus-compatible
2-wire interface consisting of a serial data line (SDA)
and a serial clock line (SCL). The MAX5842 is SMBus
compatible within the range of VDD= 2.7V to 3.6V. SDA
and SCL facilitate bidirectional communication between
the MAX5842 and the master at rates up to 400kHz.
Figure 1 shows the 2-wire interface timing diagram. The
MAX5842 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on
the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5842 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed
Pin Description
PIN NAME FUNCTION
1 ADD Address Select. A logic high sets the address LSB to 1; a logic low sets the address LSB to zero.
2 SCL Serial Clock Input
3VDDPower Supply
4 GND Ground
5 SDA Bidirectional Serial Data Interface
6 REF Reference Input
7 OUTA DAC A Output
8 OUTB DAC B Output
9 OUTC DAC C Output
10 OUTD DAC D Output
VD
×
_()=
REF
N
2
V
OUT
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 9
by a START (S) or REPEATED START (Sr) condition and
a STOP (P) condition. Each word transmitted over the
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
The MAX5842 SDA and SCL drivers are open-drain
outputs, requiring a pullup resistor to generate a logic
high voltage (see Typical Operating Circuit). Series
resistors RSare optional. These series resistors protect
the input stages of the MAX5842 from high-voltage
spikes on the bus lines, and minimize crosstalk and
undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see START and
STOP Conditions). Both SDA and SCL idle high when
the I2C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA, while SCL is high
(Figure 2). A START condition from the master signals
the beginning of a transmission to the MAX5842. The
master terminates transmission by issuing a not
acknowledge followed by a STOP condition (see
Acknowledge Bit (ACK)). The STOP condition frees the
bus. If a repeated START condition (Sr) is generated
instead of a STOP condition, the bus remains active.
When a STOP condition or incorrect address is detected, the MAX5842 internally disconnects SCL from the
serial interface until the next START condition, minimizing digital noise and feedthrough.
Early STOP Conditions
The MAX5842 recognizes a STOP condition at any
point during transmission except if a STOP condition
occurs in the same high pulse as a START condition
(Figure 3). This condition is not a legal I2C format; at
least one clock pulse must separate any START and
STOP conditions.
Repeated START Conditions
A REPEATED START (S
r
) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. Srmay also be used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX5842 serial interface supports continuous write operations with
or without an Srcondition separating them. Continuous
Table 1. Power-Down Command Bits
Figure 1. 2-Wire Serial Interface Timing Diagram
POWER-DOWN
COMMAND BITS
PD1 PD0
00
01
10
11
Power-up device. DAC output
restored to previous value.
Power-down mode 0. Power down
device with output floating.
Power-down mode 1. Power down
device with output terminated with
1kΩ to GND.
Power-down mode 2. Power down
device with output terminated with
100kΩ to GND.
MODE/FUNCTION
SDA
t
SU, DAT
t
LOW
SCL
t
HIGH
t
HD, STA
t
t
R
F
t
HD, DAT
t
SU, STA
t
HD, STA
REPEATED START CONDITIONSTART CONDITION
t
t
SP
SU, STO
STOP
CONDITION
t
BUF
START
CONDITION
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
10 ______________________________________________________________________________________
read operations require Srconditions because of the
change in direction of data flow.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5842 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5842 waits for the receiving device to generate
an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication at a later time.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the
7-bit slave address (Figure 4). When idle, the MAX5842
waits for a START condition followed by its slave
address. The serial interface compares each address
value bit by bit, allowing the interface to power down
immediately if an incorrect address is detected. The
LSB of the address word is the Read/Write (R/W) bit.
R/W indicates whether the master is writing to or reading from the MAX5842 (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After
receiving the proper address, the MAX5842 issues an
ACK by pulling SDA low for one clock cycle.
The MAX5842 has four different factory/user-programmed addresses (Table 2). Address bits A6
through A1 are preset, while A0 is controlled by ADD.
Connecting ADD to GND sets A0 = 0. Connecting ADD
to VDDsets A0 = 1. This feature allows up to four
MAX5842s to share the same bus.
Write Data Format
In write mode (R/W = 0), data that follows the address
byte controls the MAX5842 (Figure 5). Bits C3-C0 configure the MAX5842 (Table 3). Bits D11-D0 are DAC
data. Input and DAC registers update on the falling
edge of SCL during the acknowledge bit. Should the
write cycle be prematurely aborted, data is not updated
and the write cycle must be repeated. Figure 6 shows
two example write data sequences.
Extended Command Mode
The MAX5842 features an extended command mode
that is accessed by setting C3-C0 = 1 and D11-D8 = 0.
The next data byte writes to the shutdown registers
(Figure 7). Setting bits A, B, C, or D to 1 sets that DAC
Figure 2. START and STOP Conditions
Figure 3. Early STOP Conditions
Figure 4. Slave Address Byte Definition
Figure 5. Command Byte Definition
Table 2. MAX5842 I2C Slave Addresses
SCL
SDA
SS
r
P
SCL
SDA
STOP START
LEGAL STOP CONDITION
SCL
SDA
START
ILLEGAL EARLY STOP CONDITION
ILLEGAL
STOP
PART V
MAX5842L GND 0111 100
MAX5842L V
MAX5842M GND 1011 100
MAX5842M V
ADD
DD
DD
DEVICE ADDRESS
(A6...A0)
0111 101
1011 101
S A6A5A4A3A2A1A0R/W
C3 C2 C1 C0 D11 D10 D9 D8
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
______________________________________________________________________________________ 11
to the selected power-down mode based on the states
of PD0 and PD1 (Table 1). Any combination of the four
DACs can be controlled with a single write sequence.
Read Data Format
In read mode (R/W = 1), the MAX5842 writes the contents of the DAC register to the bus. The direction of
data flow reverses following the address acknowledge
by the MAX5842. The device transmits the first byte of
data, waits for the master to acknowledge, then transmits the second byte. Figure 8 shows an example read
data sequence.
I2C Compatibility
The MAX5842 is compatible with existing I2C systems.
SCL and SDA are high-impedance inputs; SDA has an
open drain that pulls the data line low during the ninth
clock pulse. The Typical Operating Circuit shows a typical I2C application. The communication protocol supports the standard I2C 8-bit communications. The
general call address is ignored. The MAX5842 address
is compatible with the 7-bit I2C addressing protocol
only. No 10-bit address formats are supported.
Digital Feedthrough Suppression
When the MAX5842 detects an address mismatch, the
serial interface disconnects the SCL signal from the
core circuitry. This minimizes digital feedthrough
caused by the SCL signal on a static output. The serial
interface reconnects the SCL signal once a valid
START condition is detected.
Applications Information
Digital Inputs and Interface Logic
The MAX5842 2-wire digital interface is I2C/SMBus
compatible. The two digital inputs (SCL and SDA) load
the digital input serially into the DAC. Schmitt-trigger
buffered inputs allow slow-transition interfaces such as
optocouplers to interface directly to the device. The
digital inputs are compatible with CMOS logic levels.
Power-Supply Bypassing and
Ground Management
Careful PC board layout is important for optimal system
performance. Keep analog and digital signals separate
to reduce noise injection and digital feedthrough. Use a
ground plane to ensure that the ground return from
GND to the power-supply ground is short and low
impedance. Bypass VDDwith a 0.1µF capacitor to
ground as close to the device as possible.
Chip Information
TRANSISTOR COUNT: 17,213
PROCESS: BiCMOS
Figure 6. Example Write Command Sequences
Figure 7. Extended Command Byte Definition
MSB
S
A6 A5 A4 A3 A2 A1 A0 C3 C2 C1 C0 D11 D10 D9 D8
MSB
D7 D6 D5 D4 D3 D2 D1 D0 P
MSB
S
A6 A5 A4 A3 A2 A1 A0 C3 C2 C1 C0 D11 D10 D9 D8
MSB
X X D C B A PD1 PD0 P
EXAMPLE WRITE TO POWER-DOWN REGISTER SEQUENCE
LSB MSB LSB
R/W ACK
EXAMPLE WRITE DATA SEQUENCE
LSB MSB LSB
R/W ACK
ACK
LSB
ACK
ACK
LSB
ACK
X X D C B A PD1 PD0
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
12 ______________________________________________________________________________________
Table 3. Command Byte Definitions
C3 C2 C1 C0 D11 D10 D9 D8
0000
0001
0010
0011
0100
0101
0110
0111
1000
SERIAL DATA INPUT
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
FUNCTION
Load DAC A input and DAC registers with new data.
Contents of DAC B, C, and D input registers are transferred
to the respective DAC registers. All outputs are updated.
Load DAC B input and DAC registers with new data.
Contents of DAC A, C, and D input registers are transferred
to the respective DAC registers. All outputs are updated.
Load DAC C input and DAC registers with new data.
Contents of DAC A, B, and D input registers are transferred
to the respective DAC registers. All outputs are updated.
Load DAC D input and DAC registers with new data.
Contents of DAC A, B, and C input registers are transferred
to the respective DAC registers. All outputs are updated
simultaneously.
Load DAC A input register with new data. DAC outputs
remain unchanged.
Load DAC B input register with new data. DAC outputs
remain unchanged.
Load DAC C input register with new data. DAC outputs
remain unchanged.
Load DAC D input register with new data. DAC outputs
remain unchanged.
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously. New
data is loaded into DAC A input register.
1001
1010
1011
1100
1101
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously. New
data is loaded into DAC B input register.
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously. New
data is loaded into DAC C input register.
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously. New
data is loaded into DAC D input register.
Load all DACs with new data and update all DAC outputs
simultaneously. Both input and DAC registers are updated
with new data.
Load all input registers with new data. DAC outputs remain
unchanged.
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
______________________________________________________________________________________ 13
Table 3. Command Byte Definitions (continued)
Figure 8. Example Read Word Data Sequence
SERIAL DATA INPUT
C3 C2 C1 C0 D11 D10 D9 D8
1110 X X X X
1111 0 0 0 0
1111 0 0 0 1
1111 0 0 1 0
1111 0 1 0 0
1111 1 0 0 0
MSB LSB MSB LSB
SA6
A4 A3 A2 A1 A0 C3 C2
A5
R/W
= 0
ACK
FUNCTION
Update all DAC outputs simultaneously. Device ignores
D11-D8. Do not send the data byte.
E xtend ed com m and m od e. The next w or d w r i tes to the p ow er d ow n r eg i ster s ( E xtend ed C om m and M od e) .
Read DAC A data. The device expects an S
condition
r
followed by an address word with R/W = 1.
Read DAC B data. The device expects an S
condition
r
followed by an address word with R/W = 1.
Read DAC C data. The device expects an S
condition
r
followed by an address word with R/W = 1.
Read DAC D data. The device expects an S
condition
r
followed by an address word with R/W = 1.
C0 D11 D10 D9 D8
C1
ACK
DATA BYTES GENERATED BY MASTER DEVICE
Sr A6
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
A4 A3 A2 A1 A0
A5
DATA BYTES GENERATED BY MAX5842
LSBMSB
R/W
= 1
ACK
ACK P
MSB LSB
XX
PD0 D11 D10 D9 D8
PD1
ACK GENERATED BY
MASTER DEVICE
ACK
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
14 ______________________________________________________________________________________
Functional Diagram
REF
INPUT
REGISTER
A
INPUT
REGISTER
B
INPUT
REGISTER
C
INPUT
REGISTER
D
SERIAL
INTERFACE
SDA ADD SCL V
MUX AND DAC
MUX AND DAC
MUX AND DAC
MUX AND DAC
REGISTER
REGISTER
REGISTER
REGISTER
DD
GND
12-BIT
DAC
A
12-BIT
DAC
B
12-BIT
DAC
C
12-BIT
DAC
D
POWER-DOWN
CIRCUITRY
MAX5842
OUTA
RESISTOR
NETWORK
OUTB
RESISTOR
NETWORK
OUTC
RESISTOR
NETWORK
OUTD
RESISTOR
NETWORK
MAX5842
Quad, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
10LUMAX.EPS
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