General Description
The MAX5822 is a dual, 12-bit, voltage-output, digital-toanalog converter (DAC) with an I2C™-compatible, 2-wire
interface that operates at clock rates up to 400kHz. The
device operates from a single 2.7V to 5.5V supply and
draws only 115µA at VDD= 3.6V. A power-down mode
decreases current consumption to less than 1µA. The
MAX5822 features three software-selectable powerdown output impedances: 100kΩ, 1kΩ, and high impedance. Other features include internal precision
Rail-to-Rail®output buffers and a power-on reset (POR)
circuit that powers up the DAC in the 100kΩ power-down
mode.
The MAX5822 features a double-buffered I2C-compatible
serial interface that allows multiple devices to share a
single bus. All logic inputs are CMOS-logic compatible
and buffered with Schmitt triggers, allowing direct interfacing to optocoupled and transformer-isolated interfaces. The MAX5822 minimizes digital noise feedthrough
by disconnecting the clock (SCL) signal from the rest of
the device when an address mismatch is detected.
The MAX5822 is specified over the extended temperature range of -40°C to +85°C and is available in a miniature 8-pin µMAX package. Refer to the MAX5821 data
sheet for the 10-bit version.
Applications
Digital Gain and Offset Adjustments
Programmable Voltage and Current Sources
Programmable Attenuation
VCO/Varactor Diode Control
Low-Cost Instrumentation
Battery-Powered Instrumentation
Features
♦ Ultra-Low Supply Current
115µA at V
DD
= 3.6V
135µA at VDD= 5.5V
♦ 300nA Low-Power Power-Down Mode
♦ Single 2.7V to 5.5V Supply Voltage
♦ Fast 400kHz I
2
C-Compatible 2-Wire Serial
Interface
♦ Schmitt-Trigger Inputs for Direct Interfacing to
Optocouplers
♦ Rail-to-Rail Output Buffer Amplifiers
♦ Three Software-Selectable Power-Down Output
Impedances
100kΩ, 1kΩ, and High Impedance
♦ Read-Back Mode for Bus and Data Checking
♦ Power-On Reset to Zero
♦ 8-Pin µMAX Package
MAX5822
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
________________________________________________________________ Maxim Integrated Products 1
Pin Configuration
Ordering Information
R
P
R
P
V
DD
µC
SDA
SCL
SDA
SDA
REF
REF
REF
SCL
SCL
V
DD
V
DD
R
S
R
S
V
DD
OUTA
OUTB
OUTA
OUTB
MAX5822
MAX5822
R
S
R
S
Typical Operating Circuit
19-2315; Rev 0; 1/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
I
2
C is a trademark of Philips Corp.
PART
MAX5822LEUA -40
MAX5822MEUA -40oC to +85oC 8 µMAX 1011 00X
TEMP
RANGE
o
C to +85oC 8 µMAX 0111 00X
PINPACKAGE
ADDRESS
TOP VIEW
87OUTB
OUTAGND
REF
6
SDASCL
5
1
V
DD
2
ADD
MAX5822
3
4
µMAX
MAX5822
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= +2.7V to +5.5V, GND = 0, V
REF
= VDD, RL= 5kΩ, CL= 200pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at V
DD
= +5V, TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, SCL, SDA to GND............................................-0.3V to +6V
OUT_, REF, ADD to GND..............................-0.3V to V
DD
+ 0.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T
A
= +70°C)
8-Pin µMAX (derate 4.5mW above +70°C) ..................362mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY (NOTE 2)
Resolution N 12 Bits
Integral Nonlinearity INL (Note 3) ±2 ±16 LSB
Differential Nonlinearity DNL Guaranteed monotonic (Note 3) ±1 LSB
Zero-Code Error ZCE Code = 000 hex, VDD = 2.7V 6 40 mV
Zero-Code Error Tempco 2.3 ppm/oC
Gain Error GE Code = FFF hex -0.8 -3 %FSR
Gain-Error Tempco 0.26 ppm/oC
Power-Supply Rejection Ratio PSRR Code = FFF hex, VDD = 4.5V to 5.5V 58.8 dB
DC Crosstalk 30 µV
REFERENCE INPUT
Reference Input Voltage Range V
Reference Input Impedance 65 90 kΩ
Reference Current Power-down mode 0.3 1 µA
DAC OUTPUT
Output Voltage Range No load (Note 4) 0 V
DC Output Impedance Code = 800 hex 1.2 Ω
Short-Circuit Current
Wake-Up Time
DAC Output Leakage Current
DIGITAL INPUTS (SCL, SDA)
Input High Voltage V
Input Low Voltage V
REF
VDD = 5V, V
V
DD
VDD = 5V 8
V
DD
Power-down mode = high impedance,
V
DD
IH
IL
OUT
= 3V, V
OUT
= 3V 8
= 5.5V, V
= full scale (short to GND) 42.2
= full scale (short to GND) 15.1
= VDD to GND
OUT
_
0V
±0.1 ±1µA
0.7 ✕
V
DD
0.3 ✕
DD
DD
V
DD
V
V
mA
µs
V
V
MAX5822
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +2.7V to +5.5V, GND = 0, V
REF
= VDD, RL= 5kΩ, CL= 200pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at V
DD
= +5V, TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Hysteresis
Input Leakage Current Digital inputs = 0 or V
Input Capacitance 6pF
DIGITAL OUTPUT (SDA)
Output Logic Low Voltage V
Three-State Leakage Current I
Three-State Output Capacitance 6pF
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate SR 0.5 V/µs
Voltage-Output Settling Time
Digital Feedthrough Code = 000 hex, digital inputs from 0 to V
Digital-to-Analog Glitch Impulse
DAC to DAC Crosstalk 2.4 nV-s
POWER SUPPLIES
Supply Voltage Range V
Supply Current with No Load I
Power-Down Supply Current I
TIMING CHARACTERISTICS (FIGURE 1)
Serial Clock Frequency f
Bus Free Time Between STOP
and START Conditions
START Condition Hold Time tHD,
SCL Pulse Width Low t
SCL Pulse Width High t
Repeated START Setup Time tSU,
Data Hold Time tHD,
Data Setup Time tSU,
SDA and SCL Receiving
Rise Time
SDA and SCL Receiving
Fall Time
SDA Transmitting Fall Time t
I
OL
L
DD
DD
DDPD
SCL
t
BUF
STA
LOW
HIGH
STA
DAT
DAT
t
r
t
f
f
= 3mA 0.4 V
SINK
Digital inputs = 0 or V
To 1/2LSB code 400 hex to C00 hex or
C00 hex to 400 hex (Note 5)
Major carry transition (code = 7FF hex to 800
hex and 800 hex to 7FF hex)
All digital inputs at 0 or VDD = 3.6V 115 205 µA
All digital inputs at 0 or VDD = 5.5V 135 215
All digital inputs at 0 or VDD = 5.5V 0.3 1 µA
(Note 5) 0 300 ns
(Note 5) 0 300 ns
(Note 5)
DD
DD
0.05
✕
V
DD
±0.1 ±1µA
±0.1 ±1µA
412µs
DD
2.7 5.5 V
0 400 kHz
1.3 µs
0.6 µs
1.3 µs
0.6 µs
0.6 µs
00.9µs
100 ns
20 +
0.1C
0.2 nV-s
12 nV-s
b
V
250 ns
MAX5822
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD= +5V, RL= 5kΩ, TA= +25°C.)
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +2.7V to +5.5V, GND = 0, V
REF
= VDD, RL= 5kΩ, CL= 200pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at V
DD
= +5V, TA= +25°C.) (Note 1)
Note 1: All devices are 100% production tested at TA= +25°C and are guaranteed by design at TA= T
MIN
to T
MAX
.
Note 2: Static specifications are tested with the output unloaded.
Note 3: Linearity is guaranteed from codes 115 to 3981.
Note 4: Offset and gain error limit the FSR.
Note 5: Guaranteed by design. Not production tested.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STOP Condition Setup Time tSU,
Bus Capacitance C
Maximum Duration of
Suppressed Pulse Widths
STO
(Note 5) 400 pF
b
t
SP
INTEGRAL NONLINEARITY
vs. INPUT CODE
4
3
2
1
0
INL (LSB)
-1
-2
-3
-4
0 4096
INPUT CODE
5
MAX5822 toc01
307220481024
4
3
INL (LSB)
2
1
0
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
2.7 5.5
SUPPLY VOLTAGE (V)
4.84.13.4
MAX5822 toc02
5
4
3
INL (LSB)
2
1
0
0.6 µs
050ns
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX5822 toc03
-40 85
TEMPERATURE (°C)
603510-15
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
1.00
0.75
0.50
0.25
0
DNL (LSB)
-0.25
-0.50
-0.75
-1.00
0 4096
INPUT CODE
MAX5822 toc04
-0.25
-0.50
DNL (LSB)
-0.75
307220481024
-1.00
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
0
2.7 5.5
SUPPLY VOLTAGE (V)
4.84.13.4
MAX5822 toc05
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
0
-0.25
-0.50
DNL (LSB)
-0.75
-1.00
-40 85
TEMPERATURE (°C)
MAX5822 toc06
603510-15
MAX5822
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(VDD= +5V, RL= 5kΩ, TA= +25°C.)
ZERO-CODE ERROR
vs. SUPPLY VOLTAGE
10
8
6
4
ZERO-CODE ERROR (mV)
2
0
2.7 5.5
SUPPLY VOLTAGE (V)
NO LOAD
4.84.13.4
GAIN ERROR vs. TEMPERATURE
-2.0
-1.6
-1.2
-0.8
GAIN ERROR (%FSR)
-0.4
0
-40 85
TEMPERATURE (°C)
NO LOAD
603510-15
ZERO-CODE ERROR
10
MAX5822 toc07
MAX5822 toc10
8
6
4
ZERO-CODE ERROR (mV)
2
0
6
5
4
3
2
DAC OUTPUT VOLTAGE (V)
1
0
vs. TEMPERATURE
MAX5822 toc08
NO LOAD
-40 85
TEMPERATURE (°C)
603510-15
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT (NOTE 6)
MAX5822 toc11
CODE = FFF hex
010
OUTPUT SOURCE CURRENT (mA)
8642
GAIN ERROR vs. SUPPLY VOLTAGE
-2.0
-1.6
-1.2
-0.8
GAIN ERROR (%FSR)
-0.4
0
2.7 5.5
SUPPLY VOLTAGE (V)
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT (NOTE 6)
2.5
2.0
1.5
1.0
DAC OUTPUT VOLTAGE (V)
0.5
0
CODE = 400 hex
010
OUTPUT SINK CURRENT (mA)
MAX5822 toc09
NO LOAD
4.84.13.4
MAX5822 toc12
8642
SUPPLY CURRENT vs. INPUT CODE
180
160
140
SUPPLY CURRENT (µA)
120
100
0 4096
INPUT CODE
SUPPLY CURRENT
SUPPLY CURRENT vs. TEMPERATURE
MAX5822 toc14
180
160
140
SUPPLY CURRENT (µA)
120
100
2.7 5.5
180
MAX5822 toc13
160
140
SUPPLY CURRENT (µA)
120
NO LOAD
CODE = FFF hex
100
327624571638819
-40 85
TEMPERATURE (°C)
603510-15
vs. SUPPLY VOLTAGE
CODE = FFF hex
NO LOAD
SUPPLY VOLTAGE (V)
MAX5822 toc15
4.84.13.4
MAX5822
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD= +5V, RL= 5kΩ, TA= +25°C.)
Note 6: The ability to drive loads greater than 5kΩ is not implied.
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
500
Z
= HIGH IMPEDANCE
OUT
NO LOAD
400
300
TA = +25°C
200
100
POWER-DOWN SUPPLY CURRENT (nA)
0
2.7 5.5
TA = -40°C
SUPPLY VOLTAGE (V)
TA = +85°C
MAX5822 toc16
4.84.13.4
V
OUT_
DD
POWER-UP GLITCH
100µs/div
MAX5822 toc17
5V
0
10mV/div
OUT_
EXITING SHUTDOWN
C
LOAD
CODE = 800 hex
2µs/div
MAX5822 toc18
500mV/div
= 200pF
OUT_
OUT_
MAJOR-CARRY TRANSITION
(POSITIVE)
C
= 200pF
LOAD
R
CODE = 7FF hex TO 800 hex
2µs/div
L
SETTLING TIME
(NEGATIVE)
C
CODE = C00 hex TO 400 hex
2µs/div
LOAD
MAX5822 toc19
= 5kΩ
MAX5822 toc22
= 200pF
5mV/div
500mV/div
OUT_
SCL
OUT_
MAJOR-CARRY TRANSITION
(NEGATIVE)
CODE = 800 hex TO 7FF hex
2µs/div
DIGITAL FEEDTHROUGH
40µs/div
MAX5822 toc20
C
= 200pF
LOAD
R
L
MAX5822 toc23
C
LOAD
f
SCL
CODE = 000 hex
= 5kΩ
= 200pF
= 12kHz
5mV/div
2V/div
2mV/div
OUT_
V
OUTA
V
OUTB
SETTLING TIME
(POSITIVE)
C
CODE = 400 hex TO C00 hex
2µs/div
LOAD
CROSSTALK
4µs/div
MAX5822 toc21
500mV/div
= 200pF
MAX5822 toc24
2V/div
1mV/div
Detailed Description
The MAX5822 is a dual, 12-bit, voltage-output DAC with
an I2C/SMBus-compatible 2-wire interface. The device
consists of a serial interface, power-down circuitry, two
input and DAC registers, two 12-bit resistor string
DACs, two unity-gain output buffers, and output resistor
networks. The serial interface decodes the address and
control bits, routing the data to the proper input or DAC
register. Data can be directly written to the DAC register, immediately updating the device output, or can be
written to the input register without changing the DAC
output. Both registers retain data as long as the device
is powered.
DAC Operation
The MAX5822 uses a segmented resistor string DAC
architecture, which saves power in the overall system
and guarantees output monotonicity. The MAX5822’s
input coding is straight binary, with the output voltage
given by the following equation:
where N = 12 (bits), and D = the decimal value of the
input code (0 to 4095).
Output Buffer
The MAX5822 analog outputs are buffered by precision, unity-gain followers that slew 0.5V/µs. Each buffer
output swings rail-to-rail, and is capable of driving 5kΩ
in parallel with 200pF. The output settles to ±0.5LSB
within 4µs.
Power-On Reset
The MAX5822 features an internal POR circuit that initializes the device upon power-up. The DAC registers
are set to zero scale and the device is powered down,
with the output buffers disabled and the outputs pulled
to GND through the 100kΩ termination resistor.
Following power-up, a wake-up command must be initiated before any conversions are performed.
Power-Down Modes
The MAX5822 has three software-controlled, low-power
power-down modes. All three modes disable the output
buffers and disconnect the DAC resistor strings from
REF, reducing supply current draw to 1µA and the reference current draw to less than 1µA. In power-down
mode 0, the device output is high impedance. In
power-down mode 1, the device output is internally
pulled to GND by a 1kΩ termination resistor. In powerdown mode 2, the device output is internally pulled to
GND by a 100kΩ termination resistor. Table 1 shows
the power-down mode command words.
Upon wake-up, the DAC output is restored to its previous value. Data is retained in the input and DAC registers during power-down mode.
Digital Interface
The MAX5822 features an I2C/SMBus-compatible 2wire interface consisting of a serial data line (SDA) and
a serial clock line (SCL). The MAX5822 is SMBus compatible within the range of VDD= 2.7V to 3.6V. SDA and
SCL facilitate bidirectional communication between the
MAX5822 and the master at rates up to 400kHz. Figure
1 shows the 2-wire interface timing diagram. The
MAX5822 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on
the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5822 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed
by a START (S) or repeated START (S
r
) condition and a
STOP (P) condition. Each word transmitted over the
MAX5822
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 7
Pin Description
PIN NAME FUNCTION
1VDDPower Supply
2 GND Ground
3 ADD Address Select. A logic high sets the address LSB to 1; a logic low sets the address LSB to 0
4 SCL Serial Clock Input
5 SDA Bidirectional Serial Data Interface
6 REF Reference Input
7 OUTA DAC A Output
8 OUTB DAC B Output
VD
×
_()=
REF
N
2
V
OUT
MAX5822
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
The MAX5822 SDA and SCL drivers are open-drain outputs, requiring a pullup resistor to generate a logic high
voltage (see the Typical Operating Circuit). Series
resistors R
S
are optional. These series resistors protect
the input stages of the MAX5822 from high-voltage
spikes on the bus lines, and minimize crosstalk and
undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section). Both SDA and SCL idle
high when the I
2
C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA, while SCL is high
(Figure 2). A START condition from the master signals
the beginning of a transmission to the MAX5822. The
master terminates transmission by issuing a notacknowledge followed by a STOP condition (see
Acknowledge Bit (ACK)). The STOP condition frees the
bus. If a repeated START condition (S
r
) is generated
instead of a STOP condition, the bus remains active.
When a STOP condition or incorrect address is detected, the MAX5822 internally disconnects SCL from the
serial interface until the next START condition, minimizing digital noise and feedthrough.
Early STOP Conditions
The MAX5822 recognizes a STOP condition at any
point during transmission except if a STOP condition
occurs in the same high pulse as a START condition
(Figure 3). This condition is not a legal I2C format; at
least one clock pulse must separate any START and
STOP conditions.
Repeated START Conditions
A repeated START (Sr) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. Srmay also be used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX5822 serial interface supports continuous write operations with or
without an Srcondition separating them. Continuous
read operations require Srconditions because of the
change in direction of data flow.
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
8 _______________________________________________________________________________________
Table 1. Power-Down Command Bits
Figure 1. 2-Wire Serial Interface Timing Diagram
POWER-DOWN
COMMAND BITS
PD1 PD0
00
01
10
11
Power-up device. DAC output
restored to previous value.
Power-down mode 0. Power down
device with output floating.
Power-down mode 1. Power down
device with output terminated with
1kΩ to GND.
Power-down mode 2. Power down
device with output terminated with
100kΩ to GND.
MODE/FUNCTION
SDA
t
SU, DAT
t
LOW
SCL
t
HIGH
t
HD, STA
t
R
t
HD, DAT
t
F
t
SU, STA
t
t
HD, STA
REPEATED START CONDITIONSTART CONDITION
SP
t
SU, STO
STOP
CONDITION
t
BUF
START
CONDITION
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5822 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5822 waits for the receiving device to generate
an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication at a later time.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the 7bit slave address (Figure 4). When idle, the MAX5822
waits for a START condition followed by its slave
address. The serial interface compares each address
value bit by bit, allowing the interface to power down
immediately, if an incorrect address is detected. The
LSB of the address word is the Read/Write (R/W) bit.
R/W indicates whether the master is writing to or reading from the MAX5822 (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After
receiving the proper address, the MAX5822 issues an
ACK by pulling SDA low for one clock cycle.
The MAX5822 has four different factory/user-programmed addresses (Table 2). Address bits A6
through A1 are preset, while A0 is controlled by ADD.
Connecting ADD to GND sets A0 = 0. Connecting ADD
to V
DD
sets A0 = 1. This feature allows up to four
MAX5822s to share the same bus.
Write Data Format
In write mode (R/W = 0), data that follows the address
byte controls the MAX5822 (Figure 5). Bits C3–C0 configure the MAX5822 (Table 3). Bits D11–D0 are DAC
data. Input and DAC registers update on the falling
edge of SCL during the acknowledge bit. Should the
write cycle be prematurely aborted, data is not updated
and the write cycle must be repeated. Figure 6 shows
two example write data sequences.
Extended Command Mode
The MAX5822 features an extended command mode
that is accessed by setting C3–C0 = 1 and D11–D8 =
0. The next data byte writes to the shutdown registers
MAX5822
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 9
Figure 2. START and STOP Conditions
Figure 3. Early STOP Conditions
Figure 4. Slave Address Byte Definition
Figure 5. Command Byte Definition
Table 2. MAX5822 I2C Slave Addresses
SS
SCL
SDA
SCL
SDA
STOP START
LEGAL STOP CONDITION
SCL
SDA
r
P
PART V
MAX5822L GND 0111 000
MAX5822L V
MAX5822M GND 1011 000
MAX5822M V
ADD
DD
DD
DEVICE ADDRESS
(A6...A0)
0111 001
1011 001
START
ILLEGAL EARLY STOP CONDITION
ILLEGAL
STOP
S A6A5A4A3A2A1A0R/W
C3 C2 C1 C0 D11 D10 D9 D8
MAX5822
(Figure 7). Setting bits A or B to 1 sets that DAC to the
selected power-down mode based on the states of PD0
and PD1 (Table 1). Any combination of the DACs can
be controlled with a single write sequence.
Read Data Format
In read mode (R/W = 1), the MAX5822 writes the contents of the DAC register to the bus. The direction of
data flow reverses following the address acknowledge
by the MAX5822. The device transmits the first byte of
data, waits for the master to acknowledge, then transmits the second byte. Figure 8 shows an example-read
data sequence.
I2C Compatibility
The MAX5822 is compatible with existing I2C systems.
SCL and SDA are high-impedance inputs; SDA has an
open drain that pulls the data line low during the ninth
clock pulse. The Typical Operating Circuit shows a typical I2C application. The communication protocol supports the standard I2C 8-bit communications. The
general call address is ignored. The MAX5822 address
is compatible with the 7-bit I2C addressing protocol
only. No 10-bit address formats are supported.
Digital Feedthrough Suppression
When the MAX5822 detects an address mismatch, the
serial interface disconnects the SCL signal from the
core circuitry. This minimizes digital feedthrough
caused by the SCL signal on a static output. The serial
interface reconnects the SCL signal once a valid
START condition is detected.
Applications Information
Digital Inputs and Interface Logic
The MAX5822 2-wire digital interface is I2C/SMBus
compatible. The two digital inputs (SCL and SDA) load
the digital input serially into the DAC. Schmitt-trigger
buffered inputs allow slow-transition interfaces, such as
optocouplers to interface directly to the device. The
digital inputs are compatible with CMOS logic levels.
Power-Supply Bypassing and
Ground Management
Careful PC board layout is important for optimal system
performance. Keep analog and digital signals separate
to reduce noise injection and digital feedthrough. Use a
ground plane to ensure that the ground return from
GND to the power-supply ground is short and low
impedance. Bypass VDDwith a 0.1µF capacitor to
ground as close to the device as possible.
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
10 ______________________________________________________________________________________
Figure 6. Example Write-Command Sequences
Figure 7. Extended Command Byte Format
MSB
S
A6 A5 A4 A3 A2 A1 A0 C3 C2 C1 C0 D11 D10 D9 D8
MSB
D7 D6 D5 D4 D3 D2 D1 D0 P
MSB
S
A6 A5 A4 A3 A2 A1 A0 C3 C2 C1 C0 D11 D10 D9 D8
MSB
X X X X B A PD1 PD0 P
EXAMPLE-WRITE DATA SEQUENCE
EXAMPLE-WRITE TO POWER-DOWN REGISTER SEQUENCE
LSB MSB LSB
ACK
R/W
LSB
ACK
LSB MSB LSB
R/W
ACK
LSB
ACK
XXXXBAPD1PD0
ACK
ACK
Chip Information
TRANSISTOR COUNT: 11,186
PROCESS: BiCMOS
MAX5822
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
______________________________________________________________________________________ 11
Table 3. Command Byte Definitions
C3 C2 C1 C0 D11 D10 D9 D8
0000
0001
0100
0101
1000
1001
SERIAL DATA INPUT
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
FUNCTION
Load DAC A input and DAC registers with new data.
Contents of DAC B input registers are transferred to the
DAC register. Both outputs are updated.
Load DAC B input and DAC registers with new data.
Contents of DAC A input registers are transferred to the
DAC register. Both outputs are updated simultaneously.
Load DAC A input register with new data. DAC outputs
remain unchanged.
Load DAC B input register with new data. DAC outputs
remain unchanged.
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously.
New data is loaded into DAC A input register.
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously.
New data is loaded into DAC B input register.
1100
1101
1110 XXXX
1111 0000
1111 0001
1111 0010
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load all DACs with new data and update all DAC outputs
simultaneously. Both input and DAC registers are updated
with new data.
Load all input registers with new data. DAC outputs
remain unchanged.
Update all DAC outputs simultaneously. Device ignores
D11–D8. Do not send the data byte.
Extended command mode. The next word writes to the
power-down registers (Extended Command Mode).
Read DAC A data. The device expects an S
followed by an address word with R/W = 1.
Read DAC B data. The device expects an S
followed by an address word with R/W = 1.
condition
r
condition
r
MAX5822
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
12 ______________________________________________________________________________________
Figure 8. Example Read Word Data Sequence
Functional Diagram
MSB LSB MSB LSB
SA6
A4 A3 A2 A1 A0 C3 C2
A5
DATA BYTES GENERATED BY MASTER DEVICE
R/W
= 0
ACK
C0 D11 D10 D9 D8
C1
ACK
Sr A6
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
A4 A3 A2 A1 A0
A5
INPUT
REGISTER
A
INPUT
REGISTER
B
LSBMSB
R/W
ACK
= 1
DATA BYTES GENERATED BY MAX5822
ACK P
REF
MUX AND DAC
REGISTER
MUX AND DAC
REGISTER
12-BIT
DAC
A
12-BIT
DAC
B
MSB LSB
XX
PD0 D11 D10 D9 D8
PD1
ACK GENERATED BY
MASTER DEVICE
MAX5822
OUTA
RESISTOR
NETWORK
OUTB
ACK
RESISTOR
NETWORK
SERIAL
INTERFACE
SDA ADD SCL GND
V
DD
POWER-DOWN
CIRCUITRY
MAX5822
Dual, 12-Bit, Low-Power, 2-Wire Serial
Voltage Output DAC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
8LUMAXD.EPS
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