The MAX5822 is a dual, 12-bit, voltage-output, digital-toanalog converter (DAC) with an I2C™-compatible, 2-wire
interface that operates at clock rates up to 400kHz. The
device operates from a single 2.7V to 5.5V supply and
draws only 115µA at VDD= 3.6V. A power-down mode
decreases current consumption to less than 1µA. The
MAX5822 features three software-selectable powerdown output impedances: 100kΩ, 1kΩ, and high impedance. Other features include internal precision
Rail-to-Rail®output buffers and a power-on reset (POR)
circuit that powers up the DAC in the 100kΩ power-down
mode.
The MAX5822 features a double-buffered I2C-compatible
serial interface that allows multiple devices to share a
single bus. All logic inputs are CMOS-logic compatible
and buffered with Schmitt triggers, allowing direct interfacing to optocoupled and transformer-isolated interfaces. The MAX5822 minimizes digital noise feedthrough
by disconnecting the clock (SCL) signal from the rest of
the device when an address mismatch is detected.
The MAX5822 is specified over the extended temperature range of -40°C to +85°C and is available in a miniature 8-pin µMAX package. Refer to the MAX5821 data
sheet for the 10-bit version.
Applications
Digital Gain and Offset Adjustments
Programmable Voltage and Current Sources
Programmable Attenuation
VCO/Varactor Diode Control
Low-Cost Instrumentation
Battery-Powered Instrumentation
Features
♦ Ultra-Low Supply Current
115µA at V
DD
= 3.6V
135µA at VDD= 5.5V
♦ 300nA Low-Power Power-Down Mode
♦ Single 2.7V to 5.5V Supply Voltage
♦ Fast 400kHz I
2
C-Compatible 2-Wire Serial
Interface
♦ Schmitt-Trigger Inputs for Direct Interfacing to
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, SCL, SDA to GND............................................-0.3V to +6V
OUT_, REF, ADD to GND..............................-0.3V to V
DD
+ 0.3V
Maximum Current into Any Pin............................................50mA
Note 1: All devices are 100% production tested at TA= +25°C and are guaranteed by design at TA= T
MIN
to T
MAX
.
Note 2: Static specifications are tested with the output unloaded.
Note 3: Linearity is guaranteed from codes 115 to 3981.
Note 4: Offset and gain error limit the FSR.
Note 5: Guaranteed by design. Not production tested.
Note 6: The ability to drive loads greater than 5kΩ is not implied.
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
500
Z
= HIGH IMPEDANCE
OUT
NO LOAD
400
300
TA = +25°C
200
100
POWER-DOWN SUPPLY CURRENT (nA)
0
2.75.5
TA = -40°C
SUPPLY VOLTAGE (V)
TA = +85°C
MAX5822 toc16
4.84.13.4
V
OUT_
DD
POWER-UP GLITCH
100µs/div
MAX5822 toc17
5V
0
10mV/div
OUT_
EXITING SHUTDOWN
C
LOAD
CODE = 800 hex
2µs/div
MAX5822 toc18
500mV/div
= 200pF
OUT_
OUT_
MAJOR-CARRY TRANSITION
(POSITIVE)
C
= 200pF
LOAD
R
CODE = 7FF hex TO 800 hex
2µs/div
L
SETTLING TIME
(NEGATIVE)
C
CODE = C00 hex TO 400 hex
2µs/div
LOAD
MAX5822 toc19
= 5kΩ
MAX5822 toc22
= 200pF
5mV/div
500mV/div
OUT_
SCL
OUT_
MAJOR-CARRY TRANSITION
(NEGATIVE)
CODE = 800 hex TO 7FF hex
2µs/div
DIGITAL FEEDTHROUGH
40µs/div
MAX5822 toc20
C
= 200pF
LOAD
R
L
MAX5822 toc23
C
LOAD
f
SCL
CODE = 000 hex
= 5kΩ
= 200pF
= 12kHz
5mV/div
2V/div
2mV/div
OUT_
V
OUTA
V
OUTB
SETTLING TIME
(POSITIVE)
C
CODE = 400 hex TO C00 hex
2µs/div
LOAD
CROSSTALK
4µs/div
MAX5822 toc21
500mV/div
= 200pF
MAX5822 toc24
2V/div
1mV/div
Detailed Description
The MAX5822 is a dual, 12-bit, voltage-output DAC with
an I2C/SMBus-compatible 2-wire interface. The device
consists of a serial interface, power-down circuitry, two
input and DAC registers, two 12-bit resistor string
DACs, two unity-gain output buffers, and output resistor
networks. The serial interface decodes the address and
control bits, routing the data to the proper input or DAC
register. Data can be directly written to the DAC register, immediately updating the device output, or can be
written to the input register without changing the DAC
output. Both registers retain data as long as the device
is powered.
DAC Operation
The MAX5822 uses a segmented resistor string DAC
architecture, which saves power in the overall system
and guarantees output monotonicity. The MAX5822’s
input coding is straight binary, with the output voltage
given by the following equation:
where N = 12 (bits), and D = the decimal value of the
input code (0 to 4095).
Output Buffer
The MAX5822 analog outputs are buffered by precision, unity-gain followers that slew 0.5V/µs. Each buffer
output swings rail-to-rail, and is capable of driving 5kΩ
in parallel with 200pF. The output settles to ±0.5LSB
within 4µs.
Power-On Reset
The MAX5822 features an internal POR circuit that initializes the device upon power-up. The DAC registers
are set to zero scale and the device is powered down,
with the output buffers disabled and the outputs pulled
to GND through the 100kΩ termination resistor.
Following power-up, a wake-up command must be initiated before any conversions are performed.
Power-Down Modes
The MAX5822 has three software-controlled, low-power
power-down modes. All three modes disable the output
buffers and disconnect the DAC resistor strings from
REF, reducing supply current draw to 1µA and the reference current draw to less than 1µA. In power-down
mode 0, the device output is high impedance. In
power-down mode 1, the device output is internally
pulled to GND by a 1kΩ termination resistor. In powerdown mode 2, the device output is internally pulled to
GND by a 100kΩ termination resistor. Table 1 shows
the power-down mode command words.
Upon wake-up, the DAC output is restored to its previous value. Data is retained in the input and DAC registers during power-down mode.
Digital Interface
The MAX5822 features an I2C/SMBus-compatible 2wire interface consisting of a serial data line (SDA) and
a serial clock line (SCL). The MAX5822 is SMBus compatible within the range of VDD= 2.7V to 3.6V. SDA and
SCL facilitate bidirectional communication between the
MAX5822 and the master at rates up to 400kHz. Figure
1 shows the 2-wire interface timing diagram. The
MAX5822 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on
the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5822 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed
by a START (S) or repeated START (S
r
) condition and a
STOP (P) condition. Each word transmitted over the
3ADDAddress Select. A logic high sets the address LSB to 1; a logic low sets the address LSB to 0
4SCLSerial Clock Input
5SDABidirectional Serial Data Interface
6REFReference Input
7OUTADAC A Output
8OUTBDAC B Output
VD
×
_()=
REF
N
2
V
OUT
MAX5822
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
The MAX5822 SDA and SCL drivers are open-drain outputs, requiring a pullup resistor to generate a logic high
voltage (see the Typical Operating Circuit). Series
resistors R
S
are optional. These series resistors protect
the input stages of the MAX5822 from high-voltage
spikes on the bus lines, and minimize crosstalk and
undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the STARTand STOP Conditions section). Both SDA and SCL idle
high when the I
2
C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA, while SCL is high
(Figure 2). A START condition from the master signals
the beginning of a transmission to the MAX5822. The
master terminates transmission by issuing a notacknowledge followed by a STOP condition (see
Acknowledge Bit (ACK)). The STOP condition frees the
bus. If a repeated START condition (S
r
) is generated
instead of a STOP condition, the bus remains active.
When a STOP condition or incorrect address is detected, the MAX5822 internally disconnects SCL from the
serial interface until the next START condition, minimizing digital noise and feedthrough.
Early STOP Conditions
The MAX5822 recognizes a STOP condition at any
point during transmission except if a STOP condition
occurs in the same high pulse as a START condition
(Figure 3). This condition is not a legal I2C format; at
least one clock pulse must separate any START and
STOP conditions.
Repeated START Conditions
A repeated START (Sr) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. Srmay also be used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX5822 serial interface supports continuous write operations with or
without an Srcondition separating them. Continuous
read operations require Srconditions because of the
change in direction of data flow.
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
Power-up device. DAC output
restored to previous value.
Power-down mode 0. Power down
device with output floating.
Power-down mode 1. Power down
device with output terminated with
1kΩ to GND.
Power-down mode 2. Power down
device with output terminated with
100kΩ to GND.
MODE/FUNCTION
SDA
t
SU, DAT
t
LOW
SCL
t
HIGH
t
HD, STA
t
R
t
HD, DAT
t
F
t
SU, STA
t
t
HD, STA
REPEATED START CONDITIONSTART CONDITION
SP
t
SU, STO
STOP
CONDITION
t
BUF
START
CONDITION
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5822 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5822 waits for the receiving device to generate
an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication at a later time.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the 7bit slave address (Figure 4). When idle, the MAX5822
waits for a START condition followed by its slave
address. The serial interface compares each address
value bit by bit, allowing the interface to power down
immediately, if an incorrect address is detected. The
LSB of the address word is the Read/Write (R/W) bit.
R/W indicates whether the master is writing to or reading from the MAX5822 (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After
receiving the proper address, the MAX5822 issues an
ACK by pulling SDA low for one clock cycle.
The MAX5822 has four different factory/user-programmed addresses (Table 2). Address bits A6
through A1 are preset, while A0 is controlled by ADD.
Connecting ADD to GND sets A0 = 0. Connecting ADD
to V
DD
sets A0 = 1. This feature allows up to four
MAX5822s to share the same bus.
Write Data Format
In write mode (R/W = 0), data that follows the address
byte controls the MAX5822 (Figure 5). Bits C3–C0 configure the MAX5822 (Table 3). Bits D11–D0 are DAC
data. Input and DAC registers update on the falling
edge of SCL during the acknowledge bit. Should the
write cycle be prematurely aborted, data is not updated
and the write cycle must be repeated. Figure 6 shows
two example write data sequences.
Extended Command Mode
The MAX5822 features an extended command mode
that is accessed by setting C3–C0 = 1 and D11–D8 =
0. The next data byte writes to the shutdown registers
(Figure 7). Setting bits A or B to 1 sets that DAC to the
selected power-down mode based on the states of PD0
and PD1 (Table 1). Any combination of the DACs can
be controlled with a single write sequence.
Read Data Format
In read mode (R/W = 1), the MAX5822 writes the contents of the DAC register to the bus. The direction of
data flow reverses following the address acknowledge
by the MAX5822. The device transmits the first byte of
data, waits for the master to acknowledge, then transmits the second byte. Figure 8 shows an example-read
data sequence.
I2C Compatibility
The MAX5822 is compatible with existing I2C systems.
SCL and SDA are high-impedance inputs; SDA has an
open drain that pulls the data line low during the ninth
clock pulse. The Typical Operating Circuit shows a typical I2C application. The communication protocol supports the standard I2C 8-bit communications. The
general call address is ignored. The MAX5822 address
is compatible with the 7-bit I2C addressing protocol
only. No 10-bit address formats are supported.
Digital Feedthrough Suppression
When the MAX5822 detects an address mismatch, the
serial interface disconnects the SCL signal from the
core circuitry. This minimizes digital feedthrough
caused by the SCL signal on a static output. The serial
interface reconnects the SCL signal once a valid
START condition is detected.
Applications Information
Digital Inputs and Interface Logic
The MAX5822 2-wire digital interface is I2C/SMBus
compatible. The two digital inputs (SCL and SDA) load
the digital input serially into the DAC. Schmitt-trigger
buffered inputs allow slow-transition interfaces, such as
optocouplers to interface directly to the device. The
digital inputs are compatible with CMOS logic levels.
Power-Supply Bypassing and
Ground Management
Careful PC board layout is important for optimal system
performance. Keep analog and digital signals separate
to reduce noise injection and digital feedthrough. Use a
ground plane to ensure that the ground return from
GND to the power-supply ground is short and low
impedance. Bypass VDDwith a 0.1µF capacitor to
ground as close to the device as possible.
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
Load DAC A input and DAC registers with new data.
Contents of DAC B input registers are transferred to the
DAC register. Both outputs are updated.
Load DAC B input and DAC registers with new data.
Contents of DAC A input registers are transferred to the
DAC register. Both outputs are updated simultaneously.
Load DAC A input register with new data. DAC outputs
remain unchanged.
Load DAC B input register with new data. DAC outputs
remain unchanged.
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously.
New data is loaded into DAC A input register.
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously.
New data is loaded into DAC B input register.
1100
1101
1110 XXXX
1111 0000
1111 0001
1111 0010
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load all DACs with new data and update all DAC outputs
simultaneously. Both input and DAC registers are updated
with new data.
Load all input registers with new data. DAC outputs
remain unchanged.
Update all DAC outputs simultaneously. Device ignores
D11–D8. Do not send the data byte.
Extended command mode. The next word writes to the
power-down registers (Extended Command Mode).
Read DAC A data. The device expects an S
followed by an address word with R/W = 1.
Read DAC B data. The device expects an S
followed by an address word with R/W = 1.
condition
r
condition
r
MAX5822
Dual, 12-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13