The MAX5661 single 16-bit DAC with precision highvoltage amplifiers provides a complete solution for programmable current and voltage-output applications.
The output amplifiers swing to industry-standard levels
of ±10V (voltage output) or source from 0mA (or from
4mA) to 20mA (current output). The voltage output
(OUTV) drives resistive loads greater than 2kΩ and
capacitive loads of up to 1.2µF. Voltage-output forcesense connections compensate for series protection
resistors and field-wiring resistance. Short-circuit protection on the voltage output limits output current to
10mA (typ) sourcing or -11.5mA (typ) sinking. The current output (OUTI) drives resistive loads up to 37.5V
(max) and inductive loads up to 1H.
The MAX5661 provides either a current output or a voltage output. Only one output is active at any given time,
regardless of the configuration. The MAX5661 voltage
output operates with ±13.48V to ±15.75V supplies
(V
DDV
, V
SSV
) and the current output operates with a
single +13.48V to +40V supply (V
DDI
). A +4.75V to
+5.25V digital supply (V
CC
) powers the rest of the internal circuitry. A buffered reference input accepts an
external +4.096V reference voltage.
Update the DAC outputs using software commands or
the asynchronous LDAC input. An asynchronous CLR
input sets the DAC outputs to the value stored in the
clear register or to zero. The FAULT output asserts
when the DAC’s current output is an open circuit, the
DAC’s voltage output is a short circuit, or when the CLR
input is low.
The MAX5661 communicates through a 4-wire 10MHz
SPI™-/QSPI™-/MICROWIRE™-compatible serial interface. The DOUT output allows daisy chaining of multiple devices. The MAX5661 is available in a 10mm x
10mm, 64-pin, LQFP package and operates over the
-40°C to +105°C temperature range.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Applications
Industrial Analog Output Modules
Industrial Instrumentation
Programmable Logic Controls/Distributed
Control Systems
Process Control
Features
♦ 10-Bit Programmable Full-Scale Output
Adjustment for Up to ±25% Over Range
♦ Programmable Voltage Output
Unipolar Range: 0 to +10.24V ±25%
Bipolar Range: ±10.24V ±25%
♦ Programmable Current Output
Unipolar Low Range: 0 to 20.45mA
Unipolar High Range: 3.97mA to 20.45mA
♦ Flexible Analog Supplies (See Table 16)
±13.48V to ±15.75V for Voltage Output
+13.48V to +40V for Current Output
♦ Force-Sense Connections (Voltage Output)
for Differential Voltage-Output Remote Sensing
♦ Voltage-Output Current Limit
♦ Dropout Detector Senses Out-of-Regulation
Current Output
♦ CLR and LDAC Inputs for Asynchronous DAC
Updates
♦ CLR Input Resets Output to Programmed Value or
Zero Code
♦ FAULT Output Indicates Open-Circuited Current
Output, Short-Circuited Voltage Output, or Clear
State
♦ Temperature Drift
Voltage Output: ±0.4ppm FSR/°C
Current Output: ±7.9ppm FSR/°C
♦ Small 64-Pin LQFP Package (10mm x 10mm)
MAX5661
19-0741; Rev 0; 8/08
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Pin Configuration and Typical Operating Circuit appear at
end of data sheet.
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering,10s) ..................................+300°C
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC= +5V, C
COMPI
= 22nF, V
DDV
= V
DDCORE
= +15V, V
SSV
= -15V, V
DDI
= +24V, V
REF
= +4.096V, V
AGND
= V
DGND
= V
DUTGND
=
V
DACGND
= 0V, R
SERIES
= 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA= -40°C to +105°C,
unless otherwise noted. Typical values are at T
A
= +25°C. See the
Typical Operating Circuit
.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
= 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA= +25°C.)
14
13
12
11
10
9
FULL-SCALE VOLTAGE (V)
8
7
6
01024
PINNAMEFUNCTION
1, 3, 5, 7, 8,
10, 15–20,
29–34, 36, 38,
42, 44, 46–52,
58, 61–64
2OUTIDAC Current-Source Output. OUTI sources either from 0 to 20mA or from 4–20mA.
4V
6COMPI
9OUTI4/0
11REF
12DACGND
13DACGNDS
14CNF1
21CNF0
POSITIVE FULL-SCALE VOLTAGE
vs. FULL-SCALE OUTPUT TRIM CODE
UNIPOLAR OR BIPOLAR MODE
CODE
768512256
MAX5661 toc65
N.C.No Connection. Not internally connected.
DAC Current-Output Positive Supply. Connect V
DDI
+40V to power the DAC current-output (OUTI) buffer. Bypass V
AGND, as close as possible to the device.
OUTI Noise-Limiting Capacitor Connection. Connect a 22nF capacitor from COMPI to V
reduce transient noise at OUTI.
Current-Output Range Selection Input. Connect OUTI4/0 to AGND to select the 0 to 20mA OUTI
current-output range. Connect OUTI4/0 to V
The OUTI current range can also be set by software. When using software to set the OUTI current
range, connect OUTI4/0 to AGND.
Buffered Voltage Reference Input. Connect an external +4.096V voltage reference to REF. Bypass
REF with a 0.1µF capacitor to DACGND, as close as possible to the device. Use a 1kΩ resistor in
series to the reference input for optimum performance.
DAC Analog Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together on a
low-noise ground plane with a star connection.
DAC Analog Sense Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together
on a low-noise ground plane with a star connection.
Voltage/Current Configuration Input. CNF1 and CNF0 control the OUTV and OUTI outputs. See
Tables 13 and 14.
Voltage/Current Configuration Input. CNF0 and CNF1 control the OUTV and OUTI outputs. See
Tables 13 and 14.
NEGATIVE FULL-SCALE VOLTAGE
vs. FULL-SCALE OUTPUT TRIM CODE
-6
-7
-8
-9
-10
-11
FULL-SCALE VOLTAGE (V)
-12
-13
-14
01024
CODE
768512256
MAX5661 toc66
to a power supply between +13.48V and
DDI
to select the 4–20mA OUTI current-output range.
DDI
with a 0.1µF capacitor to
DDI
DDI
to
MAX5661
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
22DINSerial-Data Input. Data is clocked into the serial interface on the rising edge of SCLK.
23SCLKSerial-Clock Input
24CS
25DGNDDigital Ground
26V
27LDAC
28FAULT
35DOUT
37CLR
39V
40DUTGNDS
41DUTGND
43COMPV
45AGNDAnalog Ground
53SVP
54, 59I.C.Internal Connection. Leave unconnected.
55V
56OUTV
57V
60SVNRem ote V ol tag e S ense Inp ut. C onnect to the top ter m i nal of R
CC
DDCORE
SSV
DDV
Active-Low Chip-Select Input. Drive CS low to enable the serial interface. Drive CS high to disable
the serial interface. DOUT is high impedance when CS is high.
Digital Power Supply. Connect V
with a 0.1µF capacitor to DGND, as close as possible to the device.
Active-Low Asynchronous Load DAC Input. Drive LDAC low to transfer the contents of the input
register to the DAC register to immediately update the output. Connect LDAC to V
Active-Low Open-Drain Fault Output. FAULT asserts low for an OUTI open-circuit condition, an
OUTV short-circuit condition, or when the CLR input is low (see Table 12 and Figure 9).
Serial Data Output. Data transitions at DOUT on SCLK’s falling edge. DOUT is high impedance
when CS is high. Use DOUT to read the shift register contents or for daisy chaining multiple
MAX5661 devices.
Active-Low Clear Input. Drive CLR low to set the DAC code to the value stored in the clear
register, to 0V in voltage mode, or 0mA/4mA depending on the output current mode. Program the
contents of the clear register through the serial interface. Enable and disable the CLR input
through the control register’s CLREN bit (see Table 4).
DAC Core Positive Supply. Connect V
with a 0.1µF capacitor to AGND, as close as possible to the device.
DUT Analog Sense Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together
on a low-noise ground plane with a star connection.
DUT Analog Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together on a
low-noise ground plane with a star connection.
OUTV Amplifier Compensation Feedback Node. Connect a 3.3nF capacitor from OUTV to COMPV
when OUTV drives capacitive loads of up to 1.2µF. Leave COMPV open for faster response time.
Remote Ground Sense Input. Connect SVP to the bottom terminal of R
Operating Circuit.
D AC V ol tag e- Outp ut N eg ati ve P ow er S up p l y. Al w ays connect V
and -15.75V. Bypass V
DAC Unipolar/Bipolar Voltage Output. OUTV provides 0 to +10.48V in unipolar mode and -10.48V
to +10.48V in bipolar mode.
DAC Voltage-Output Positive Power Supply. Connect V
and +15.75V. Bypass V
with a 0.1µF capacitor to AGND, as close as possible to the device.
SSV
DDV
to a power supply between +4.75V and +5.25V. Bypass V
CC
CC
or V
DDCORE
with a 0.1µF capacitor to AGND, as close as possible to the device.
The MAX5661 single 16-bit DAC with precision high-voltage amplifiers provides a complete solution for programmable current and voltage-output applications. The
programmable output amplifiers swing to industry-standard voltage levels of ±10V or current levels from 0mA
(or from 4mA) to 20mA. The OUTV voltage output drives
resistive loads greater than 2kΩ and capacitive loads up
to 1.2µF. Force and sense connections on the voltage
output compensate for series protection resistors and
field wiring resistance. Short-circuit protection on the
voltage output limits output current. The OUTI current
output drives resistive loads from 0Ω and higher, up to a
compliance voltage of (V
DDI
- 2.5V). The OUTI current
output also drives inductive loads up to 1H.
The MAX5661 provides a current output or a voltage
output, with only one output active at any given time.
The MAX5661 operates with ±13.48V to ±15.75V dual
supplies (V
DDV
, V
SSV
) for the voltage output and a
+13.48V to +40V single supply (V
DDI
) for the current
output (see Table 16). The +4.75V to +5.25V digital supply (VCC) powers the digital circuitry and V
DDCORE
powers the rest of the internal analog circuitry. A buffered
reference input accepts a +4.096V reference voltage.
The LDAC and CLR inputs asynchronously update the
DAC outputs. CLR sets the DAC code to the value
stored in the clear register (software clear), or to zero
scale (hardware clear). The FAULT output asserts for
an open-circuit current output, a short-circuit voltage
output, or a clear state condition when CLR is low. The
power-on reset circuitry guarantees the outputs remain
off at power-up and all register bits are set to zero to
ensure a glitchless power-up sequence.
A 10MHz SPI-/QSPI-/MICROWIRE-compatible serial
interface programs the DAC outputs and configures the
device. The DOUT output allows shift-register reads or
daisy chaining of several devices. The double-buffered
interface includes an input register and a DAC register.
Use software commands or the asynchronous LDAC
input to transfer the input register contents to the DAC
register and update the DAC outputs.
4-Wire SPI-Compatible Serial Interface
The MAX5661 communicates through a serial interface
compatible with SPI, QSPI, and MICROWIRE devices.
For SPI, ensure that the SPI bus master (typically a
microcontroller (µC)) runs in master mode to generate
the serial-clock signal. Set the SCLK frequency to
10MHz or less, and set the clock polarity (CPOL) and
phase (CPHA) in the µC control registers to the same
value. The MAX5661 operates with SCLK idling high or
low, and thus operates with CPOL = CPHA = 0 (see
Figure 2) or CPOL = CPHA = 1 (see Figure 3). Force
CS low to input data at DIN on the rising edge of SCLK.
Output data at DOUT updates on the falling edge of
SCLK (see Figure 1).
A high-to-low transition on CS initiates the 24-bit data
input cycle. Once CS is low, write an 8-bit command
byte (MSB first) at DIN to send data to the appropriate
internal register (see Tables 1, 2, and 3). C7 is the MSB
of the command byte and C0 is the LSB. Following the
command byte, write 2 data bytes containing bits
D15–D0. D15 is the MSB of the 2 data bytes and D0 is
the LSB (see Figure 4 and the
Register Descriptions
sec-
tion). Data loads into the shift register 1 bit at a time.
Write the data as one continuous 24-bit stream, always
keeping CS low throughout the entire 24-bit word. The
MAX5661 stores the 24 most recent bits received,
including bits from previous transmission(s). Ensure
SCLK has 24 rising and falling edges between CS
falling low to CS returning high. Data loads into the shift
register on the rising edge of SCLK. Once CS returns
high, data transfers from the shift register into the
appropriate internal register.
When reading data, write an 8-bit command byte and
16 data bits at DIN. On the following 24-bit sequence,
read out the shift register’s contents (command byte
and the 16 data bits) at DOUT (see Figure 5). Data transitions at DOUT on the falling edge of SCLK. While
reading data at DOUT on the second 24-bit sequence,
load another command byte and 2 data bytes at DIN or
write a no-operation command. DOUT three-states
when CS is high. The DAC outputs update on the rising
edge of CS after writing to the DAC register or by
pulling LDAC low.
Daisy chain multiple devices by connecting the first
DOUT to the second DIN, and so forth. Daisy chaining
allows communication with multiple MAX5661 devices
using single CS and SCLK signals. See the
Daisy
Chaining Multiple MAX5661 Devices
section.
MAX5661
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
BITS WITH CAPITAL LETTERS REPRESENT DATA BEING WRITTEN TO THE SHIFT REGISTER.
BITS WITH LOWERCASE LETTERS REPRESENT DATA IN THE SHIFT REGISTER FROM THE PREVIOUS 24-BIT CYCLE.
CS
SCLK
DIN
DOUT
p IS DATA LEFT FROM THE PREVIOUS INSTRUCTION CYCLE.
BITS WITH CAPITAL LETTERS REPRESENT DATA BEING WRITTEN TO THE SHIFT REGISTER.
BITS WITH LOWERCASE LETTERS REPRESENT DATA IN THE SHIFT REGISTER FROM THE PREVIOUS 24-BIT CYCLE.
The MAX5661 communicates between its internal registers and the external bus lines through the 4-wire
SPI-/QSPI-/MICROWIRE-compatible serial interface.
Table 1 details the command bits (C7–C0) and the data
bits (D15–D0) of the serial input word. Tables 2 and 3
detail the command byte and the subsequent register
accessed. Tables 4–8 detail the various read/write
internal registers and their power-on reset states. When
updating the DAC register, allow 5µs before sending
the next command.
Control Register (Read/Write)
Write to the control register to enable the current or voltage output, set the voltage output for unipolar or bipolar
mode, and set the current-output range. The control
register also initializes the clear and fault modes. Set
the command byte to 0x01 to write to the control register. Set the command byte to 0x02 to read from the
control register. Write or read data bits D15–D5. D4–D0
are don’t-care bits for a write operation. D4, D3, and D2
are read-only bits. D1 and D0 are don’t-care bits for a
read operation (see Table 4).
Set the OUTVON bit (D15) to 1 to enable the OUTV
DAC voltage output. Set the OUTION bit (D14) to 1 to
enable the OUTI DAC current output. Always set bit
D13 to 0. Set the B/U bit (D12) to determine whether the
OUTV output operates in bipolar mode (B/U = 0) or
unipolar mode (B/U = 1).
X = Don’t care. All other commands are reserved for factory use. Do not use.
Set the OUTI4/0EN bit (D11) low to enable the OUTI4/0
hardware input. Set the I4TO20BIT bit (D10) high to
select the current-output range through the software.
Set the CLREN bit (D9) low to enable the CLR hardware
input. Set the CLRMODE bit (D8) high to force the output to the value in the clear register or the zero state
when the CLR hardware input is pulled low. Set the
RCLR bit (D7) high to remain in the clear state. Set the
FAULTEN bit (D6) high to enable the FAULT output
functionality. Set the CLRFLAGEN bit (D5) high to activate the FAULT output when the MAX5661 is in the
clear state.
Bits D4, D3, and D2 are read-only bits. The FAULTV bit
(D4) is set to 1 when OUTV is short circuited. The
FAULTI bit (D3) is set to 1 when OUTI is open circuited.
The CLEARST bit (D2) is set to 1 when the MAX5661 is
in the clear state.
Figure 4. Write Timing
Figure 5. Read Timing
DIN CLOCKED IN ON THE
SCLK RISING EDGE
CS
SCLK
DIN
CS
SCLK
DIN
DOUT
CS
WRITE COMMAND EXECUTED
C7C6C5C4C0D15D14D13D0
READ COMMAND EXECUTED
C7C6C5C4C0D15D14D13D0
DOUT READY
SCLK
DIN
DOUT
X = DON'T CARE.
XXXXXXXXX
C7C6C5C4C0D15D14D13D0
DOUT TRANSITIONS ON THE FALLING SCLK EDGE
MAX5661
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
OUTVOND150DAC OUTV output enable bit. Set to 1 to enable the OUTV output.
OUTIOND140DAC OUTI output enable bit. Set to 1 to enable the OUTI output.
—D130Reserved. Always set to 0.
B/UD120
OUTI4/0END110
I4TO20BITD100
CLREND90
CLRMODED80
RCLRD70
FAULTEND60
CLRFLAGEND50C l ear fl ag enab l e. S et to 1 to enab l e the FAU LT outp ut to r ep or t w hen the d evi ce i s i n the cl ear state.
FAULTVD40
FAULTID30
CLEARSTD20
XD1, D00Not used.
DATA
BIT
RESET
STATE
FUNCTION
Voltage-output unipolar/bipolar mode select bit. Set to 0 (default power-up state) to select the
bipolar output range (±10.48V). Set to 1 to select the unipolar output range (0 to +10.48V).
OUTI4/0 enable bit. Set to 0 (default power-up state) to enable the OUTI4/0 hardware input. Set
to 1 to disable the OUTI4/0 hardware input, thereby controlling the current-output range
through software commands.
OUTI current range bit. Set to 0 to set the OUTI current range from 0 to 20mA. Set to 1 to set
the OUTI current range from 4–20mA.
Clear enable bit. Set to 0 to enable the external CLR input. Set to 1 to disable the external CLR
input.
Clear mode bit. Set to 1 and drive the external CLR input low to force the DAC output to the
value stored in the clear register. Set to 0 and drive the external CLR input low to force the DAC
output to 0V in voltage mode or 0mA/4mA depending on output-current mode.
Remain in clear bit. Set to 1 to remain in the clear state. The RCLR bit determines the steps
CLR
required to exit the clear state. See the
Fault output enable. Set to 1 to enable the FAULT output functionality. Set to 0 to disable the
FAULT output functionality.
Output voltage fault bit (read only). The FAULTV bit is set to 1 when FAULT triggers due to an
OUTV short-circuit condition. The FAULTV bit is a don’t-care bit for control-register write
commands.
Output-current fault bit (read only). The FAULTI bit is set to 1 when FAULT triggers due to an
OUTI open-circuit condition. The FAULTI bit is a don’t-care bit for the control register write
commands.
C l ear state b i t ( r ead onl y) . The C LE ARS T b i t i s set to 1 w hen CLR i s l ow and C LRE N = 0. The C LRS T
b i t i s a d on’ t- car e b i t for contr ol r eg i ster w r i te com m and s.
Write to the input register to store the DAC code.
Transfer the value written to the input register to the
DAC register by pulling the LDAC input low or by writing to the load DAC register (0x05). Set the command
byte to 0x03 to write to the input register. Set the command byte to 0x07 to read from the input register. Bits
D15–D0 contain the straight binary data (see Table 5).
DAC Register (Read/Write)
Write to the DAC register to update the OUTV and OUTI
outputs after CS returns high. Set the command byte to
0x04 to write to the DAC register. Set the command
byte to 0x08 to read from the DAC register. Bits
D15–D0 contain the straight binary data (see Table 6).
Load DAC Register (Write)
Write to the load DAC register to transfer the input register data to the DAC register and update the DAC out-
put. Set the command byte to 0x05 to write to the load
DAC register. Bits D15–D0 are don’t-care bits.
Clear Register (Read/Write)
Write to the clear register to set the DAC output value
when the CLR hardware input is pulled low (forcing the
MAX5661 into the clear state). Set the command byte to
0x06 to write to the clear register. Set the command
byte to 0x09 to read the clear register. Bits D15–D0
contain the straight binary data (see Table 7).
No Operation
Set the command byte to 0x0F or 0x00 to perform a nooperation command. After writing the command byte
and 2 data bytes (16 don’t-care bits), read out the shift
register’s contents on the following 24-bit cycle.
Table 5. Input Register (Read/Write)
Table 6. DAC Register (Read/Write)
Table 7. Clear Register (Read/Write)
Table 8. Full-Scale Output Trim Register (Write)
BIT NAMEDATA BITRESET STATEFUNCTION
0000 0000 0000 0000
IN15–IN0D15–D0
(unipolar/current)
1000 0000 0000 0000
(bipolar)
IN15 is the MSB and IN0 is the LSB. Data format is straight binary.
BIT NAMEDATA BITRESET STATEFUNCTION
0000 0000 0000 0000
DAC15–DAC0D15–D0
(unipolar/current)
0000 0000 0000 0000
(bipolar)
DAC15 is the MSB and DAC0 is the LSB. Data format is straight
binary.
BIT NAMEDATA BITRESET STATEFUNCTION
0000 0000 0000 0000
CLR15–CLR0D15–D0
(unipolar/current)
1000 0000 0000 0000
(bipolar)
CLR15 is the MSB and CLR0 is the LSB. Data format is straight
binary.
BIT NAMEDATA BITRESET STATEFUNCTION
FS_EN +
FS_BIT9–
FS_BIT0
D9–D00000 0000 0000 0000
FS_EN (D15) enables the full-scale output adjustment feature. D9
is the MSB and D0 is the LSB. D9 is straight binary, D8–D0 are
inverted binary.
MAX5661
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Table 9. N to D: Full-Scale Output Trim Register Bits Map
Table 10. Full-Scale Output Variation vs.
N and B
Figure 6. Transfer Function of Bits (B) to Numerical (N)
Representation
Full-Scale Output
Current Trim Register (Write)
Write to the full-scale output trim register to adjust the
output voltage or current ±25%. Set command bits to
0x06 to write to the output trim register. Bit 15 enables
the output trim register. Bits D9–D0 program the 10-bit
trim DAC (Table 8).
Connect an external voltage reference in the +4V to
+4.2V range through a 1kΩ series resistor to
the buffered REF input. Use a high-accuracy, lownoise +4.096V voltage reference such as the
MAX6126AASA41 (3ppm/°C temperature drift and
0.02% initial accuracy) for best 16-bit static accuracy.
REF does not accept AC signals. See Table 17 for a listing of +4.096V references.
LDAC
Input
The MAX5661 features an active-low load DAC (LDAC)
logic input that allows asynchronous updates to the
DAC outputs. Drive LDAC high to VCCduring normal
operation while controlling the MAX5661 using only the
serial interface. Drive LDAC low to update the DAC output with the input register data. Hold LDAC low to make
the input register transparent and immediately update
the DAC output with the input register data. Figure 8
shows the LDAC timing with respect to OUT_.
LDAC
SOFTWARE
LOAD DAC
CONTROL
CS
SCLK
DIN
DOUT
SHIFT
REGISTER
MAX5661
REGISTER
INPUT
REGISTER
CLEAR
REGISTER
DAC
REGISTER
FULL-SCALE
ADJUST
REGISTER
DAC
2-TO-1
MUX
FULL-SCALE
OUTPUT ADJUST
TO OUTPUT
CIRCUITRY
OUTI
OUTV
LDAC
OUT_
t
LDL
± 2 LSB
t
DELAY
MAX5661
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
The active-low external CLR input asynchronously sets
the DAC code to the value in the clear register (software
clear) or to the zero state (hardware clear), depending
on the control register’s CLRMODE bit setting (see
Tables 4 and 11). Set the CLRMODE bit to 1 and drive
external CLR low to force the output to the value stored
in the clear register. Set the CLRMODE bit to 0 and
drive the external CLR input low to force the output to
the zero state. The zero state value is 0mA in 0 to 20mA
current mode, 3.97mA in 4–20mA current mode, or 0V
in voltage mode (unipolar or bipolar).
Disable the external CLR input functionality by setting
the control register’s CLREN bit to 1. Set the CLREN bit
to 0 to enable the external CLR input functionality.
After setting the CLREN bit to 0, force the external CLR
input low to set the MAX5661 into the clear state. The
control register’s read-only CLEARST bit is set to 1 while
in the clear state. The RCLR (remain in clear) bit determines the steps required to exit the clear state.
With the RCLR bit set to 1, exit the clear state in one of
three ways:
1) Pull the external CLR input high and then write to
the DAC register (0x04) or the load DAC register
(0x05) or force LDAC low.
2) Pull the external CLR input high and set the RCLR
bit low.
3) Initiate a power-on reset (POR) to reset the RCLR bit
to 0.
With the RCLR bit set to 0, exit the clear state one of
three ways:
1) Set the CLREN bit high.
2) Pull the external CLR input high.
3) Initiate a power-on reset (POR).
FAULT
Output
The open-drain active-low FAULT output asserts low for
a current-output open circuit or dropout condition, for a
voltage-output short circuit, or when the MAX5661 is in
the clear state (see the
CLR Input
section).
Enable and disable the FAULT output with the control
register’s FAULTEN and CLRFLAGEN bits (see Tables
4, 12, and Figure 9). Set the FAULTEN bit to 1 to enable
the FAULT output to report fault conditions on OUTV
and OUTI. Set FAULTEN to 0 to disable the FAULT out-
put for fault conditions on OUTV and OUTI. Set the
CLRFLAGEN bit to 1 to enable the FAULT output
to report when the device is in the clear state. Set
CLRFLAGEN to 0 to disable a hardware indication
of the clear state. The FAULT output asserts low if
CLRFLAGEN = 1 and CLEARST = 1.
Read the control register to determine the source of
a FAULT output condition. The FAULTV read-only bit
is set to 1 when the voltage output (OUTV) is shortcircuited. The FAULTI bit is set to 1 when the current
output (OUTI) is open circuited or in a dropout condition
(V
DDI
- V
OUTI
at 1.3V typ). The FAULT output asserts
low if FAULTEN is set to 1 and either the FAULTV bit or
FAULTI bit is set to 1.
Table 11. Hardware-Clear and Software-Clear Truth Table
X = Don’t care.
*
Zero state is 0V in unipolar voltage mode, -10.48V in bipolar voltage mode, and 0mA/4mA depending on output-current mode.
CLEARST BIT
(READ)
0 (not in clear state)XXX
1 (in clear state)0DAC code set to zero state*—
1 (in clear state)1—DAC code set by clear register data
The CNF0, CNF1, and OUTI4/0 hardware inputs determine whether the hardware or software controls the
MAX5661 DAC outputs (see Table 13). The CNF0 and
CNF1 inputs enable and disable the DAC outputs or
allow software control of the outputs (see Table 14).
The OUTI4/0 input sets the current range of the OUTI
output. Hardware inputs take precedence over the software commands.
The V
CC
digital supply powers the CNF1, CNF0, and
OUTI4/0 inputs. If VCC= 0V, the DAC outputs enter the
zero state and all register bits are set to 0. The zero
state of the voltage output (OUTV) is 0V. The zero state
of the current output (OUTI) is 0mA when OUTI4/0 =
AGND or 4mA when OUTI4/0 = V
DDI
.
Table 13. Output Configuration
CONTROL
SIGNAL
CNF1Hardware input
CNF0Hardware input
OUTI4/0Hardware inputSets the OUTI current range.
OUTI4/0ENSoftware bit
OUTVONSoftware bit
OUTIONSoftware bit
B/USoftware bit
I4TO20BITSoftware bit
HARDWARE
INPUT/SOFTWARE BIT
DESCRIPTIONDETAILS
Enables/disables the DAC
OUTV and OUTI outputs.
Enables and disables the
OUTI4/0 input.
Enables and disables the
DAC OUTV and OUTI
Sets the voltage output to
unipolar mode or bipolar
Sets the OUTI current range
through software.
outputs.
mode.
CNF1, CNF0:
00 = both outputs disabled
01 = OUTI active, set to 0 to 20mA range
10 = OUTV active, set to bipolar mode
11 = outputs controlled by serial interface
S et the OU TI4/0E N b i t to 0 ( d efaul t p ow er - up state) to enab l e
the O U TI4/0 har d w ar e i np ut. C onnect the OU TI4/0 har d w ar e
i np ut to AGN D to set the OU TI cur r ent r ang e to 0 to 20m A.
C onnect the O U TI4/0 har d w ar e i np ut to V
cur r ent r ang e to 4–20m A. S et the OU TI4/0E N b i t to 1 to
d i sab l e the O U T14/0 har d w ar e i np ut. C onnect OU TI4/0 to
AGN D w hen contr ol l i ng the cur r ent outp ut thr oug h softw ar e.
Set the OUTI4/0EN bit to 0 (default power-up state) to
enable the OUTI4/0 hardware input. Set to 1 to disable the
OUTI4/0 hardware input.
When the CNF1 and CNF0 hardware inputs are high, the
OUTION and OUTVON bits control the DAC output OUTI
and OUTV settings.
OUTVON, OUTION:
00 = both outputs powered down
01 = OUTI active
10 = OUTV active
11 = both outputs powered down
Set B/U to 0 to set the OUTV output to bipolar mode
(±10.48V). Set B/U to 1 to set the OUTV output to unipolar
mode (0 to +10.48V).
Set I4TO20BIT to 0 to set the OUTI current range from 0 to
20mA. Set I4TO20BIT to 1 to set the OUTI current range
from 4–20mA.
The CNF0 and CNF1 inputs enable the DAC’s voltage
(OUTV) or current (OUTI) outputs. Drive CNF0 and
CNF1 low to disable both the OUTV and OUTI outputs.
Drive CNF0 high and CNF1 low to enable the OUTI output. Drive CNF0 low and CNF1 high to enable the
OUTV output. Drive CNF0 and CNF1 high to control the
OUTV and OUTI outputs through the serial interface.
Table 14 summarizes the output behavior when programmed by the CNF0/CNF1 hardware inputs.
OUTI Current-Output Configuration
Drive CNF0 high and CNF1 low to enable the OUTI output through the hardware. Alternatively, drive CNF0 and
CNF1 high to control OUTI with the serial interface. With
CNF1 and CNF0 high, the control register’s
OUTION bit enables the OUTI output. Set OUTION to 1
to enable the OUTI output. Set OUTION to 0 (default
power-up state) to disable the OUTI output.
The OUTI current output derives power from V
DDI
and
V
DDCORE
(+13.48V to +40V). Connect V
DDCORE
to
V
DDI
when using the OUTI output.
The control register’s OUTI4/0EN bit (see Tables 4 and
13) determines whether the OUTI4/0 hardware input or
the control register’s I4TO20BIT bit controls the OUTI
current range. Set the OUTI4/0EN bit to 0 (default
power-up state) to control the current range through the
OUTI4/0 hardware input. Connect the OUTI4/0 hardware input to AGND to select the 0 to 20mA mode.
Connect the OUTI4/0 hardware input to V
DDI
to select
the 4–20mA mode.
Set the OUTI4/0EN bit to 1 to allow software control of
the OUTI current range through the I4TO20BIT bit (see
Table 13). Set I4TO20BIT to 0 to select the 0 to 20mA
mode. Set I4TO20BIT to 1 to select the 4–20mA mode.
OUTV Voltage-Output Configuration
Drive CNF0 low and CNF1 high to enable the OUTV
output through the hardware (see Table 14).
Alternatively, drive CNF0 and CNF1 high to control
OUTV with the serial interface. With CNF1 and CNF0
high, the control register’s OUTVON bit enables the
OUTV output. Set OUTVON to 1 to enable the OUTV
output. Set OUTVON to 0 (default power-up state) to
disable the OUTV output.
The OUTV output derives power from V
DDV
, V
SSV
, and
V
DDCORE
. Connect V
DDCORE
to V
DDV
(+13.48V to
+15.75V) when using the OUTV output. Always connect
a negative supply to V
SSV
(-13.48V to -15.75V) (see
Table 16).
The control register’s B/U bit sets OUTV for bipolar or
unipolar mode. Set B/U to 0 (default power-up state) to
select the bipolar output range (±10.48V). Set B/U to 1
to select the unipolar output range (0 to +10.48V).
Output Transfer Functions
The DAC output voltage/current is a function of the various hardware control inputs and digital inputs in the
control register (see Table 13). The transfer functions
below assume that the outputs are on, and a reference
voltage of +4.096V is applied to the reference input. For
the voltage output, the sense input is at the same
potential as the DAC output (OUTV = SVP and AGND =
SVN). Table 15a details the bipolar output voltage
transfer function. Table 15b details the unipolar output
voltage transfer function. Table 15c details the 0 to
20mA current-range transfer function. Table 15d details
the 4mA to 20mA current-range transfer function.
Table 14. CNF1/CNF0 Hardware Settings
CNF1CNF0OUTV, OUTI SETTING
DGNDDGNDBoth DAC outputs disabled.
DGNDV
V
CC
V
CC
DGNDOUTV enabled. OUTI disabled.
CC
V
CC
OUTI enabled. OUTV disabled.
DAC outputs controlled by the serial interface.
MAX5661
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Table 16. Application Modes and Supply-Voltage Limits
*
On-the-fly switching. Only one output is active at a time.
Measuring Zero-Code Current
(0 to 20mA Mode)
After setting the MAX5661 for 0 to 20mA current-range
mode, determine the LSB size as follows:
1) Measure I
OUT
at full scale (FS).
2) Measure I
OUT
at code 192.
3) Measure I
OUT
at code 193:
If I
OUT
(code 193) - I
OUT
(code 192) > 0.5 I
LSB
, I
OUT
(code 192) is inside the linear region of the I
OUT
trans-
fer curve.
Obtain the straight-line equation from I
OUT
(FS) and
I
OUT
(192) and substituting code 0 for I
OUT
(zero scale)
in the equation:
The expected current is -30µA (typ).
Applications Information
Power-Supply Sequencing and Bypassing
After connecting all ground inputs, apply the analog
supply voltages V
SSV
first followed by the most positive
supply, the second most positive supply, etc. Before
applying power, connect the V
DDCORE
supply to either
V
DDV
or V
DDI
, as shown in Table 16, depending on
whether the current output or voltage output is used. Do
not apply V
DDCORE
separate from the main supply
(V
DDV/VSSV
or V
DDI
) in the preferred configuration
(Table 16). Ensure that there are no unconnected
power-supply connections when powering the
MAX5661. If V
SSV
cannot be powered first, connect a
Schottky diode between V
SSV
and AGND.
Daisy Chaining Multiple MAX5661 Devices
In standard SPI-/QSPI-/MICROWIRE-compatible systems, a microcontroller (µC) communicates with its
slave devices through a 3- or 4-wire serial interface.
The typical interface includes a chip select signal (CS),
a serial clock (SCLK), a data input signal (DIN), and
sometimes a data signal output (DOUT). In this system,
the µC allots an independent chip-select signal to each
slave device so that they can be addressed individually
(see Figure 10). Only the slaves with their CS inputs
asserted low acknowledge and respond to the activity
on the serial clock and data lines. This is simple to
implement when there are very few slave devices in the
system. An alternative programming method is daisy
chaining. Daisy chaining, in serial-interface applications, is a method of propagating commands through
multiple devices connected in series (see Figure 11).
Daisy chaining reduces CS and DIN line routing, and
saves board space when using the MAX5661.
Daisy chain multiple MAX5661 devices by connecting
the DOUT of one device to the DIN of the next. Connect
the SCLK of all devices to a common clock and connect
the CS from all devices to a common chip-select line.
Data shifts out of DOUT 24.5 clock cycles after it is shifted into DIN on the falling edge of SCLK. Hold CS low
until each slave in the chain receives its 24-bit word (8
command bits and 16 data bits). In this configuration,
the µC only needs three signals (CS, SCLK, and DIN) to
control all the slaves in the network. The SPI-/QSPI/MICROWIRE-compatible serial interface normally works
at up to 10MHz, but must be slowed to 6MHz if daisy
chaining. DOUT is high impedance when CS is high.
Figure 10 details a method of controlling multiple
MAX5661 devices using separate CS lines. This
method allows writes to and reads from each device
without shifting data through the other device’s shift
register. Figure 10 shows the FAULT outputs shorted
together. This configuration requires a read from each
device to determine which one has the fault condition
and saves an optocoupler in isolated applications. It is
not necessary to short the FAULT outputs together.
()II at
IatFSI
OUT
OUTOUT
−=
−
192
aat
x code
I
OUT
()
192
65535 192
192
−
⎛
⎝
⎜
⎞
⎠
⎟
−
().at ZS IatIat FS x
OUTOUT
=−1920 00229383192+Iat
OUT
I
LSB
IatFSI at
OUTOUT
( )
=
−
−−
192
21192
16
APPLICATION MODEV
Voltage from OUTV+13.48V to +15.75V-13.48V to -15.75VV
Figure 11 shows a method of daisy chaining multiple
MAX5661 devices using a single CS and SCLK line with
the FAULT outputs shorted together. Connect DOUT
from IC1 to DIN of IC2, and DOUT from IC2 to DIN of
IC3. Hold CS low for three 24-bit write cycles to load
data into all three devices. Due to the latency of reading and writing to the different devices, using separate
lines for each FAULT output does not save time.
Figure 10. Address Two MAX5661 Devices Through Separate CS Lines
Driving Inductive Loads from I
OUT
When driving inductive loads > 275µH with the current
output (I
OUT
), connect a 1nF capacitor between V
DDI
and I
OUT
for optimal performance.
MAX5661
CSCS1
DINDIN
SCLKSCLK
LDACLDAC
CLRCLR
CSCS2
DIN
IC1
FAULT
DOUT
MAX5661
IC2
SCLK
LDAC
CLR
DOUT
FAULT
FAULT
DOUT
MAX5661
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
* SEE THE DAC FUNCTIONAL DIAGRAM IN FIGURE 7.
** REQUIRED TO DRIVE C
PROTECTION
OPTIONAL
SURGE
OPTIONAL
SURGE
OUTV
< 1nF.
MAX5661
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________