Rainbow Electronics MAX5559 User Manual

General Description

The MAX5556–MAX5559 stereo audio sigma-delta
digital-to-analog converters (DACs) offer a simple and
complete stereo digital-to-analog solution for media
servers, set-top boxes, video-game hardware, automo­tive rear-seat entertainment and other general consumer
audio applications. These DACs feature built-in digital
interpolation/filtering, sigma-delta digital-to-analog con­version and analog output filtering. Control logic and
mute circuitry minimize audible pops and clicks during
power-up, power-down, clock changes, or when invalid
clock conditions occur.

The MAX5556–MAX5559 receive input data over a flexi­ble 3-wire interface, supporting I

2

S-compatible, left-jus­tified, right-justified 16-bit, and right-justified 18-bit
audio data. Data can be clocked by either an external
or internal serial clock. The internal serial clock frequen­cy is programmable by selection of a master clock
(MCLK) and sample clock (LRCLK) ratio. Sampling
rates from 2kHz to 50kHz are supported.

The MAX5556–MAX5559 operate from a single +4.75V
to +5.5V analog supply with total harmonic distortion
plus noise below -87dB. These devices are available in
8-pin SO packages and are specified over the -40°C to
+85°C industrial temperature range.

Applications

Digital Video Recorders and Media Servers

Set-Top Boxes

Video-Game Hardware

Automotive Rear-Seat Entertainment

Features

♦ Simple and Complete Stereo Audio DAC

Solutions, No Controls to Set

♦ Sigma-Delta Stereo DACs with Built-In

Interpolation and Analog Output Filters

♦ I2S-Compatible Digital Audio Interface (MAX5556)

♦ Clickless/Popless Operation

♦ Output Voltage Swing: 3.5V

P-P

♦ -87dB THD+N

♦ +87dB Dynamic Range

♦ Sample Frequencies (fS) from 2kHz to 50kHz

♦ Master Clock (MCLK) up to 25MHz

♦ Automatic Detection of Clock Ratio (MCLK/

LRCLK)

MAX5556–MAX5559

Ordering Information

Typical Operating Circuit

19-0550; Rev 0; 5/06

Low-Cost Stereo Audio DACs

________________________________________________________________

Maxim Integrated Products

1

For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Note:

All devices are specified over the -40°C to +85°C oper-

ating temperature range. Contact factory for +105°C operation.

*

Future product—contact factory for availability.

Pin Configuration

PART

MAX5556ESA 8 SO S8-5 Left-justified I
M A X5 5 5 7 E S A* 8 SO S8-5 Left-justified data
M A X5 5 5 8 E S A* 8 SO S8-5 Ri g ht- j usti fi ed 16- Bi t d ata
M A X5 5 5 9 E S A* 8 SO S8-5 Ri g ht- j usti fi ed 18- Bi t d ata

PIN ­PA C K A G E

PKG

CODE

DATA FORMAT

2

S data

+5V

AUDIO

DECOMPRESSION

CLOCK

V

SDATA

SCLK

LRCLK

MCLK

SERIAL

INTERFACE

DD

MAX5556–MAX5559

GND

DAC

DAC

OUTL

OUTR

LINE-LEVEL

BUFFER

LINE-LEVEL

BUFFER

LEFT

OUTPUT

RIGHT

OUTPUT

TOP VIEW

SDATA

SCLK

LRCLK

1

2

87OUTL

MAX5556–

MAX5559

3

4

6

5

SO

V

DD

GND

OUTRMCLK

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

2 ________________________________________________________________________________________

VDDto GND...........................................................-0.3V to +6.0V

OUTL, OUTR, SDATA to GND................... -0.3V to (V

DD

+ 0.3V)

Current Into Any Pin (excluding V

DD

and GND)...............±10mA

OUTL, OUTR Shorted to GND....................................Continuous

SCLK, LRCLK, MCLK to GND ...............................-0.3V to +6.0V

Continuous Power Dissipation (T

A

= +70°C)

8-Pin SO (derate 5.88mW above +70°C)....................471mW

Package Thermal Resistance (θ

JA

) ...............................170°C/W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= +4.75V to +5.5V, GND = 0V, R

OUT

_ = 10kΩ, C

OUT

_ = 10pF, 0dBFS sine-wave signal at 997Hz, f

LRCLK(fS

) = 48kHz, f

MCLK

=

12.288MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified. T

A

= -40°C to +85°C, unless otherwise noted.

Outputs are unloaded, unless otherwise noted. Typical values at V

DD

= +5V, TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY

Supply Voltage V

Supply Current I

Power Dissipation

DYNAMIC PERFORMANCE (Note 2)

Dynamic Range, 16-Bit

Dynamic Range, 18-Bit to 24-Bit

Total Harmonic Distortion Plus
Noise, 16-Bit

Total Harmonic Distortion Plus
Noise, 18-Bit to 24-Bit

Interchannel Isolation 1kHz full-scale output (crosstalk) 94 dB

COMBINED DIGITAL AND INTEGRATED ANALOG FILTER FREQUENCY RESPONSE (Note 3)

Passband

Frequency Response/Passband
Ripple

Stopband 0.5465 f

Stopband Attenuation 52 dB

Group Delay

Passband Group-Delay Variation ∆t

DD

DD

THD+N

THD+N

gd

t

gd

Up to 48ksps 13 15

Static digital 6 8.5

Up to 48ksps 65 82.5

Static digital 30 44

Unweighted 84 86

A-weighted 86 90

Unweighted 87

A-weighted 91

0dBFS -86 -81

-20dBFS -67

-60dBFS -26 -24

0dBFS -87

-20dBFS -68

-60dBFS -27

-0.5dB corner 0.46

-3dB corner 0.49

-6dB corner 0.50

10Hz to 20kHz (fS = 48kHz) -0.025 +0.08

10Hz to 20kHz (fS = 44.1kHz) -0.025 +0.08

10Hz to 16kHz (f

20Hz to 20kHz ±0.4 / f

= 32kHz) -6.000 +0.073

S

20 / f

S

S

4.75 5.0 5.50 V

mA

mW

dB

dB

dB

dB

f

dB

S

S

s

s

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

_______________________________________________________________________________________

3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +4.75V to +5.5V, GND = 0V, R

OUT

_ = 10kΩ, C

OUT

_ = 10pF, 0dBFS sine-wave signal at 997Hz, f

LRCLK(fS

) = 48kHz, f

MCLK

=

12.288MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified. T

A

= -40°C to +85°C, unless otherwise noted.

Outputs are unloaded, unless otherwise noted. Typical values at V

DD

= +5V, TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC CHARACTERISTICS

Interchannel Gain Mismatch 0.1 0.4 dB

Gain Error -5 +5 %

Gain Drift 100 ppm/°C

ANALOG OUTPUTS

Full-Scale Output Voltage

DC Quiescent Output Voltage V

Minimum Load Resistance R

Maximum Load Capacitance C

Power-Supply Rejection Ratio PSRR

POP AND CLICK SUPPRESSION

Mute Attenuation 100 dB

Power-Up Until Bias Established Figure 14 360 ms

Valid Clock to Normal Operation Soft-start ramp time, Figure 15 (Note 5) 20 ms

DIGITAL AUDIO INTERFACE (SCLK, SDATA, MCLK, LRCLK)

Input-Voltage High V

Input-Voltage Low V

Input Leakage Current I

Input Capacitance 8pF

TIMING CHARACTERISTICS

Input Sample Rate f

MCLK Pulse-Width High t

EXTERNAL SCLK MODE

LRCLK Duty Cycle (Note 6) 25 75 %

SCLK Pulse-Width Low t

SCLK Pulse-Width High t

SCLK Period t

LRCLK Edge to SCLK Rising

LRCLK Edge to SCLK Rising

SDATA Valid to SCLK Rising

SCLK Rising to SDATA Hold Time t

V

OU T R

, V

OU T L

Q

L

L

IH

IL

IN

S

MCLKL

MCLKH

SCLKL

SCLKH

SCLK

t

SLRS

t

SLRH

t

SDS

SDH

3.25 3.5 3.75 V

Input code = 0 2.4 V

3kΩ

100 pF

V

RIPPLE

= 100mV

, frequency = 1kHz

P-P

66 dB

2.0 V

0.8 V

-10 +10 µA

2 50 kHz

MCLK/LRCLK = 512 10

MCLK/LRCLK = 384 20MCLK Pulse-Width Low t

MCLK/LRCLK = 256 20

MCLK/LRCLK = 512 10

MCLK/LRCLK = 384 20

MCLK/LRCLK = 256 20

20 ns

20 ns

1 / (128

x f

)

S

20 ns

20 ns

20 ns

20 ns

P-P

ns

ns

ns

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

4 ________________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +4.75V to +5.5V, GND = 0V, R

OUT

_ = 10kΩ, C

OUT

_ = 10pF, 0dBFS sine-wave signal at 997Hz, f

LRCLK(fS

) = 48kHz, f

MCLK

=

12.288MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified. T

A

= -40°C to +85°C, unless otherwise noted.

Outputs are unloaded, unless otherwise noted. Typical values at V

DD

= +5V, TA= +25°C.) (Note 1)

Note 1: 100% production tested at T

A

= +85°C. Limits to -40°C are guaranteed by design.

Note 2: 0.5 LSB of triangular PDF dither added to data.
Note 3: Guaranteed by design, not production tested.
Note 4: PSRR test block diagram shown in Figure 1 denotes the test setup used to measure PSRR.
Note 5: Volume ramping interval starts from establishment of a valid MCLK to LRCLK ratio. Total time is proportional to the sample

rate (f

S

). 20ms based on 48ksps operation.

Note 6: In external SCLK mode, LRCLK duty cycles are not limited, provided all data formatting requirements are met. See Figures

4–7.

Note 7: The LRCLK duty cycle must be 50% ±1/2 MCLK period in internal SCLK mode.
Note 8: The SCLK/LRCLK ratio can be set to 32, 48, or 64, depending on the device and the MCLK/LRCLK ratio selected. See

Figures 4–7.

Figure 1. PSRR Test Block Diagram

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

INTERNAL SCLK MODE

LRCLK Duty Cycle (Note 7) 50 %

Internal SCLK Period t

LRCLK Edge to Internal SCLK

SDATA Valid to Internal SCLK

SDATA Valid to Internal SCLK

ISCLK

t

ISCLKR

t

ISDS

t

ISDH

(Note 8) 1 / f

MCLK period = t

MCLK period = t

MCLK

MCLK

t

MCLK

t

/ 2 ns

SCLK

t

ISCLK

+ 10 ns

MCLK

ns

ns

V

DD

LOUT, ROUT

SPECTRUM
ANALYZER

AUDIO SIGNAL

GENERATOR

AT 1kHz)

(100mV

P-P

DC POWER SUPPLY

(5VDC)

Z

G

SCLK

LRCLK

MCLK

ACTIVE CLOCKS

+

-

SD ATA

MAX5556–MAX5559

GND

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

_______________________________________________________________________________________

5

(VDD= +5V, GND = 0V, R

OUT_

= 10kΩ, C

OUT_

= 10pF, TA = +25°C, unless otherwise noted.)

Typical Operating Characteristics

-0.25

-0.15

-0.20

-0.05

-0.10

0.05

0

0.10

0.20

0.15

0.25

0 0.1 0.2 0.3 0.4 0.5

PASSBAND RIPPLE

MAX5556 toc04

FREQUENCY (NORMALIZED TO fS)

AMPLITUDE (dB)

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-130

-120

-140
0 2 4 6 8 101214161820

FREQUENCY (kHz)

AMPLITUDE (dBr)

0dBFS FFT

MAX5556 toc05

16,000-SAMPLE FFT USING 1kHz INPUT

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-130

-120

-140
0 2 4 6 8 101214161820

FREQUENCY (kHz)

AMPLITUDE (dBr)

-60dBFS FFT

MAX5556 toc06

16,000-SAMPLE FFT USING 1kHz INPUT

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 0.2 0.3 0.40.1 0.5 0.6 0.7 0.90.8 1.0

STOPBAND REJECTION

MAX5556 toc01

FREQUENCY (NORMALIZED TO fS)

AMPLITUDE (dB)

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0.40 0.44 0.48 0.52 0.56 0.60

TRANSITION BAND

MAX5556 toc02

FREQUENCY (NORMALIZED TO fS)

AMPLITUDE (dB)

-10

-7

-8

-9

-6

-5

-4

-3

-2

-1

0

0.40 0.440.42 0.46 0.48 0.50 0.52

TRANSITION BAND DETAIL

MAX5556 toc03

FREQUENCY (NORMALIZED TO fS)

AMPLITUDE (dB)

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-130

-120

-140
0 2 4 6 8 101214161820

FREQUENCY (kHz)

AMPLITUDE (dBr)

IDLE-CHANNEL NOISE FFT

MAX5556 toc07

16,000-SAMPLE FFT WITH NO INPUT

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-130

-120

-140
0 2 4 6 8 101214161820

FREQUENCY (kHz)

AMPLITUDE (dBr)

TWIN-TONE IMD FFT

MAX5556 toc08

16,000-SAMPLE FFT
WITH 13kHz AND
14kHz INPUT SIGNALS

-110

-100

-80

-90

-70

-60

-60 -40-50 -30 -20 -10 0

THD+N vs. AMPLITUDE

MAX5556 toc09

AMPLITUDE (dBFS)

THD+N (dBr)

UNWEIGHTED

A-WEIGHTED

INPUT = 1kHz 18-BIT SIGNAL

INTEGRATION BANDWIDTH = 20Hz TO 20kHz

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

6 ________________________________________________________________________________________

(VDD= +5V, GND = 0V, R

OUT_

= 10kΩ, C

OUT_

= 10pF, TA = +25°C, unless otherwise noted.)

Typical Operating Characteristics (continued)

-110

-100

-90

-80

-70

-60

0810462 1214161820

UNWEIGHTED THD+N

vs. FREQUENCY

MAX5556 toc10

FREQUENCY (kHz)

THD+N (dBr)

INPUT = 1kHz 18-BIT SIGNAL,
INTEGRATION BANDWIDTH = 20Hz TO 20kHz

0

20

10

40

30

60

50

70

02010 30 40 50

POWER DISSIPATION

vs. SAMPLE FREQUENCY

MAX5556 toc11

SAMPLE FREQUENCY (kHz)

POWER DISSIPATION (mW)

VDD = +5V
INPUT = 1kHz, 0dBFS SIGNAL

5

8

7

6

9

10

11

12

13

14

15

4.75 5.054.90 5.20 5.35 5.50

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX5556 toc12

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

INPUT = 1kHz, 0dBFS SIGNAL
NORMAL OPERATION

STATIC DIGITAL INPUT
MUTE OPERATION

5

7

6

10

9

8

11

12

14

13

15

0 1.0 1.50.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

SUPPLY CURRENT

vs. DIGITAL INPUT VOLTAGE (V

DIG

)

MAX5556 toc13

DIGITAL INPUT VOLTAGE (V

DIG

) (V)

SUPPLY CURRENT (mA)

V

IH

V

DIG

< V

IH

MUTE
ENGAGED

VDD = +5.5V
DC OUTPUT

V

DIG

< V

IH

NORMAL OPERATION

5ms/div

CLOCK-LOSS MUTE RECOVERY

V

OUT

1V/div

2.4V

MAX5556 toc14

CLOCK
RESTORED

LOSS
OF CLOCK

100ms/div

POWER-UP RESPONSE

V

OUT

1V/div

0V

MAX5556 toc15

MAX5556–MAX5559

Detailed Description

The MAX5556–MAX5559 stereo audio sigma-delta DACs
offer a complete stereo digital-to-analog system for con­sumer audio applications. The MAX5556–MAX5559 fea­ture built-in digital interpolation/filtering, sigma-delta
digital-to-analog conversion and analog output filters
(Figure 2). Control logic and mute circuitry minimize
audible pops and clicks during power-up, power-down,
and whenever invalid clock conditions occur.

These stereo audio DACs receive input data over a 3­wire interface that supports up to 24 bits of left-justified,
right-justified, or I2S-compatible audio data. The
MAX5556 accepts left-justified I2S data, up to 24 bits.
The MAX5557 accepts left-justified data, up to 24 bits.
The MAX5558 accepts right-justified 16-bit data. The
MAX5559 accepts right-justified 18-bit data. These
DACs also support a wide range of sample rates from
2kHz to 48kHz. Direct analog output data is routed to
the right or left output by driving LRCLK high or low.
See the

Clock and Data Interface

section.

The MAX5556–MAX5559 support MCLK/LRCLK ratios
of 256, 384, or 512. These devices allow a change to
the clock speed ratio without causing glitches on the
analog outputs by internally muting the audio during
invalid clock conditions. The internal mute function
ramps down the audio amplitude and forces the analog

outputs to a 2.4V quiescent voltage immediately upon
clock loss or change of ratio. A soft-start routine is then
engaged when a valid clock ratio is re-established, pro­ducing clickless and popless continuous operation.

The MAX5556–MAX5559 operate from a +4.75V to
+5.5V analog supply and feature +87dB dynamic
range with total harmonic distortion typically below

-87dB.

Interpolator

The digital interpolation filter eliminates images of the
baseband audio signal that exist at multiples of the input
sample rate (fS). The resulting upsampled frequency
spectrum has images of the input signal at multiples of 8
x fS. An additional upsampling sinc filter further reduces
upsampling images up to 64 x f

S

. These images are ulti­mately removed through the internal analog lowpass filter
and the external analog output filter.

Sigma-Delta Modulator/DAC

The MAX5556–MAX5559 use a multibit sigma-delta DAC
with an oversampling ratio (OSR) of 64 to achieve a wide
dynamic range. The sigma-delta modulator accepts a 3­bit data stream from the interpolation filter at a rate of 64
x fS(fS= LRCLK frequency) and provides an analog volt­age representation of that data stream.

Pin Description

Low-Cost Stereo Audio DACs

_______________________________________________________________________________________

7

PIN NAME FUNCTION

Serial Audio Data Input. Data is clocked into the MAX5556–MAX5559 on the rising edge of the

1 SDATA

2 SCLK External Serial Clock Input. Data is strobed on the rising edge of SCLK.

3 LRCLK

4 MCLK Master Clock Input. The MCLK/LRCLK ratio must equal to 256, 384, or 512.

5 OUTR Right-Channel Analog Output

6 GND Ground

7V

8 OUTL Left-Channel Analog Output

DD

internal or external SCLK. Data is input in two’s complement format, MSB first. The state of LRCLK
determines whether data is directed to OUTL or OUTR.

Left-/Right-Channel Select Clock. For the MAX5556, drive LRCLK low to direct data to OUTL or
LRCLK high to direct data to OUTR. For the MAX5557/MAX5558/MAX5559, drive LRCLK high to
direct data to OUTL or LRCLK low to direct data to OUTR.

Power-Supply Input. Bypass VDD to GND with a 0.1µF capacitor in parallel with a 4.7µF capacitor as
close to V

as possible. Place the 0.1µF capacitor closest to V

DD

DD.

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

8 ________________________________________________________________________________________

Integrated Analog Lowpass Filter

The DAC output of the sigma-delta modulator is fol­lowed by an analog smoothing filter that attenuates
high-frequency quantization noise. The corner frequen­cy of the filter is approximately 2 x fS.

Integrated Analog Output Buffer

Following the analog lowpass filter, the analog signal is
routed through internal buffers to OUTR and OUTL. The
buffer can directly drive load resistances larger than
3kΩ and load capacitances up to 100pF (Figure 3).

Figure 2. Functional Diagram

Figure 3. Load-Impedance Operating Region

V

DD

INTERPOLATOR

SDATA

SCLK

SERIAL

LRCLK

MCLK

INTERFACE

INTERPOLATOR

MAX5556–MAX5559

125

100

(pF)

L

75

SIGMA-DELTA

MODULATOR

SIGMA-DELTA

MODULATOR

GND

DAC

INTERNAL

REFERENCE

DAC

ANALOG

LOWPASS

FILTER

ANALOG

LOWPASS

FILTER

OUTL

BUFFER

OUTR

BUFFER

LOAD CAPACITANCE C

50

25

3

5101520

LOAD RESISTANCE RL (kΩ)

SAFE OPERATING REGION

25

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

_______________________________________________________________________________________

9

Clock and Data Interface

The MAX5556–MAX5559 strobe serial data (SDATA) in
on the rising edge of SCLK. LRCLK routes data to the
left or right outputs and, along with SCLK, defines the
number of bits per sample transferred. The digital inter­polators filter data at internal clock rates derived from
the MCLK frequency. Each device supports both inter­nal and external serial clock (SCLK) modes.

SDATA Input

The serial interface strobes data (SDATA) in on the ris­ing edge of SCLK, MSB first. The MAX5556–MAX5559
support four different data formats, as detailed in
Figures 4–7.

Figure 4. MAX5556 Data Format Timing

Figure 5. MAX5557 Data Format Timing

LRCLK

SCLK

SDATA

-2 -3 -4 -5 +5 +4 +3 +2 +1 -1 -2 -3 -4 +5 +4 +3 +2 +1

-1

MSB

INTERNAL SERIAL CLOCK MODE EXTERNAL SERIAL CLOCK MODE

2

• I

S, 16-BIT DATA AND INTERNAL SCLK =

IF MCLK/ LRCLK = 256 OR 512

32 x f

S

2

S, UP TO 24 BITS OF DATA AND INTERNAL

• I
SCLK = 48 X f

DATA DIRECTED TO OUTL

IF MCLK/ LRCLK = 384

S

DATA DIRECTED TO OUTR

MSBLSB LSB

• I2S, UP TO 24 BITS OF DATA

• DATA VALID ON RISING EDGE OF SCLK

LRCLK

SCLK

-2

SDATA

MSB MSBLSB LSB

-3 -4 -5 +5 +4 +3 +2 +1 -1 -2 -3 -4 +5 +4 +3 +2 +1

-1

INTERNAL SERIAL CLOCK MODE EXTERNAL SERIAL CLOCK MODE

• LEFT-JUSTIFIED, UP TO 24 BITS OF DATA

• INTERNAL SCLK = 64 x f

• INTERNAL SCLK = 48 x f

DATA DIRECTED TO OUTL

S IF MCLK / LRCLK = 256 OR 512

IF MCLK / LRCLK = 384

S

• LEFT-JUSTIFIED, UP TO 24 BITS OF DATA

• DATA VALID ON RISING EDGE OF SCLK

DATA DIRECTED TO OUTR

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

10 _______________________________________________________________________________________

Serial Clock (SCLK)

SCLK strobes the individual data bits at SDATA into the
DAC. The MAX5556–MAX5559 operate in one of two
modes: internal serial clock mode or external serial
clock mode.

External SCLK Mode

The MAX5556–MAX5559 operate in external serial clock
mode when SCLK activity is detected. All four devices
return to internal serial clock mode if no SCLK signal is
detected for one LRCLK period. Figure 8 details the
external serial clock mode timing parameters.

Internal SCLK Mode

The MAX5556–MAX5559 transition from external serial
clock mode to internal serial clock mode if no SCLK
signal is detected for one LRCLK period. In internal
clock mode, SCLK is derived from and is synchronous
with MCLK and LRCLK (operation in internal clock
mode is identical to an external clock mode when
LRCLK is synchronized with MCLK). Figure 9 details
the internal serial clock mode timing parameters. Figure
10 details the generation of the internal clock.

Figure 6. MAX5558 Data Format Timing

Figure 7. MAX5559 Data Format Timing

LRCLK

SCLK

SDATA

DATA DIRECTED TO OUTL

89 76543210

INTERNAL SERIAL CLOCK MODE EXTERNAL SERIAL CLOCK MODE

• RIGHT-JUSTIFIED, 16-BIT DATA

• INTERNAL SCLK = 32 x f

• INTERNAL SCLK = 48 x f

S IF MCLK / LRCLK = 256 OR 512

IF MCLK / LRCLK = 384

S

LRCLK

SCLK

SDATA

MSB LSB LSBMSB

DATA DIRECTED TO OUTL

10 89 76543210111215 131417 16 17 16

DATA DIRECTED TO OUTR

15 14 13 12 11 1015 14 13 12 11 10

LSBMSB LSBMSB

• RIGHT-JUSTIFIED, 16-BIT DATA

• DATA VALID ON RISING EDGE OF SCLK

• SCLK MUST HAVE AT LEAST 32 CYCLES PER LRCLK PERIOD

DATA DIRECTED TO OUTR

15 10 89 7654321011121314

89 76543 210

INTERNAL SERIAL CLOCK MODE EXTERNAL SERIAL CLOCK MODE

• RIGHT-JUSTIFIED, 18-BIT DATA

• INTERNAL SCLK = 64 x f

• INTERNAL SCLK = 48 x f

S IF MCLK / LRCLK = 256 OR 512

IF MCLK / LRCLK = 384

S

• RIGHT-JUSTIFIED, 18-BIT DATA

• DATA VALID ON RISING EDGE OF SCLK

• SCLK MUST HAVE AT LEAST 36 CYCLES PER LRCLK PERIOD

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

______________________________________________________________________________________

11

LRCLK

Figure 8. External SCLK Serial Timing Diagram

Figure 9. Internal SCLK Serial Timing Diagram

Figure 10. Internal Serial Clock Generation

SCLK

SDATA

LRCLK

t

t

SLRH

t

SLRS

t

SDS

t

ISCLKR

SCLK

t

SCLKLtSCLKH

t

SDH

SD ATA

INTERNAL

SCLK

LRCLK

MCLK

INTERNAL

SCLK

SD ATA

1

*N = MCLK / SCLK.

N / 2*

t

ISDS

t

ISDH

t

ISCLK

N*

MAX5556–MAX5559

Left/Right Clock Input (LRCLK)

LRCLK is the left/right clock input signal for the 3-wire
interface and sets the sample frequency (f

S

). On the
MAX5556, drive LRCLK low to direct data to OUTL or
LRCLK high to direct data to OUTR (Figure 4). On the
MAX5557/MAX5558/MAX5559, drive LRCLK high to
direct data to OUTL or LRCLK low to direct data to
OUTR (Figures 5, 6, 7). LRCLK is internally resampled
on each SCLK rising edge. The MAX5556–MAX5559
accept data at LRCLK audio sample rates from 2kHz to
50kHz.

Master Clock (MCLK)

MCLK accepts the master clock signal from an external
clocking device and is used to derive internal clock fre­quencies. Set the MCLK/LRCLK ratio to 256, 384, or
512 to achieve the internal serial clock frequencies list­ed in Table 1. Table 2 details the MCLK/LRCLK ratios
for three sample audio rates.

The MAX5556–MAX5559 detect the MCLK/LRCLK ratio
during the initialization sequence by counting the num­ber of MCLK transitions during a single LRCLK period.
MCLK, SCLK, and LRCLK must be synchronous sig­nals.

Data Formats

MAX5556 I2S Left-Justified Data Format

The MAX5556 accepts data with an I2S left-justified
data format, accepting up to 24 bits of data. SDATA
accepts data in two’s complement format with the MSB
first. The MSB is valid on the second SCLK rising edge
after LRCLK transitions low to high or high to low
(Figure 4). Drive LRCLK low to direct data to OUTL.
Drive LRCLK high to direct data to OUTR. The number
of SCLK pulses with LRCLK high or low determines the
number of bits transferred per sample. If fewer than 24
bits of data are written, the remaining LSBs are set to 0.
If more than 24 bits are written, any bits after the LSB
are ignored.

The MAX5556 accepts up to 24 bits of data in external
serial clock mode or when the MCLK/LRCLK ratio is
384 (internal serial clock = 48 x fS) in internal serial
clock mode. The DAC also accepts 16 bits of data in
internal serial clock mode when the MCLK/LRCLK ratio
is 256 or 512 (internal serial clock = 32 x fS).

MAX5557 Left-Justified Data Format

The MAX5557 accepts data with a left-justified data for­mat, allowing for up to 24 bits of data. SDATA accepts
data in two’s complement format with the MSB first. The
MSB is valid on the first SCLK rising edge after LRCLK
transitions low to high or high to low (Figure 5). Drive
LRCLK high to direct data to OUTL. Drive LRCLK low to
direct data to OUTR. The number of SCLK pulses with
LRCLK high or low determines the number of bits trans­ferred per sample. If fewer than 24 bits of data are writ­ten, the remaining LSBs are set to 0. If more than 24
bits are written, the bits after the LSB are ignored.

The MAX5557 accepts up to 24 bits of data in external
serial clock mode and internal serial clock mode.
Program the MCLK/LRCLK ratio to 384 to operate the
internal serial clock at 48 x f

S

. Program the
MCLK/LRCLK ratio to 256 or 512 to operate the internal
serial clock at 64 x f

S

.

MAX5558 16-Bit Right-Justified Data Format

The MAX5558 operates from a 16-bit right-justified data
format. The LSB is valid on the final SCLK rising edge
prior to LRCLK transitioning low to high or high to low
(Figure 6). In external serial clock mode, the MAX5558
requires a minimum of 32 SCLK cycles per LRCLK peri­od (16 SCLK cycles with LRCLK low and 16 SCLK
cycles with LRCLK high). Drive LRCLK high to direct
data to OUTL. Drive LRCLK low to direct data to OUTR.
Any additional SDATA bits prior to the MSB are ignored.

Low-Cost Stereo Audio DACs

12 _______________________________________________________________________________________

Table 1. Internal and External Clock
Frequencies

Table 2. MCLK/LRCLK Ratios

INTERNAL SERIAL

PART

MAX5556 32 x f

MAX5557 64 x f

MAX5558 32 x f

MAX5559 64 x f

CLOCK FREQUENCY

M C L K /L R C L K

= 2 5 6 O R 51 2

S

S

S

S

M C L K /L R C L K

= 3 8 4

48 x f

S

48 x f

S

48 x f

S

48 x f

S

EXTERNAL

SERIAL

CLOCK

FREQUENCY

User defined

(Figure 4)

User defined

(Figure 5)

User defined

(Figure 6)

User defined

(Figure 7)

LRCLK

(kHz)

32 8.1920 12.2880 16.3840

44.1 11.2896 16.9344 22.5792

48 12.2880 18.4320 24.5760

MCLK/LRCLK

= 256

MCLK (MHz)

MCLK/LRCLK

= 384

MCLK/LRCLK

= 512

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

______________________________________________________________________________________

13

The MAX5558 accepts 16 bits of data in external serial
clock mode and internal serial clock mode. Program the
MCLK/LRCLK ratio to 384 to operate the internal serial
clock at 48 x f

S

. Program the MCLK/LRCLK ratio to 256

or 512 to operate the internal serial clock at 32 x fS.

MAX5559 18-Bit Right-Justified Data Format

The MAX5559 accepts data with an 18-bit right-justified
data format. The LSB is valid on the final SCLK rising
edge prior to LRCLK transitioning low to high or high to
low (Figure 7). In external serial clock mode, the
MAX5559 requires a minimum of 36 SCLK cycles per
LRCLK period (18 SCLK cycles with LRCLK low and 18
SCLK cycles with LRCLK high). Drive LRCLK high to
direct data to OUTL. Drive LRCLK low to direct data to
OUTR. Any additional SDATA bits prior to the MSB
are ignored.

The MAX5559 accepts 18 bits of data in external serial
clock mode and internal serial clock mode. Program the
MCLK/LRCLK ratio to 384 to operate the internal serial
clock at 48 x f

S

. Program the MCLK/LRCLK ratio to 256

or 512 to operate the internal serial clock at 64 x fS.

External Analog Filter

Use an external lowpass analog filter to further reduce
harmonic images, noise, and spurs. The external ana­log filter can be either active or passive depending
upon performance and design requirements. For exam­ple filters, see Figures 11 and 12 and the

Applications

Information

section. Careful attention should be paid
when selecting capacitors for audio signal path appli­cations. NPO and C0G types are recommended as are
aluminum electrolytics and some tantalum varieties.
Use of generic ceramic types is not recommended and
may result in degraded THD performance. Always con­sult manufacturers’ data sheets and applications infor­mation.

Figure 11. Passive Component Analog Output Filter

OUTL

R = 560Ω

100kΩ

C = 1.5nF

MAX5556–MAX5559

OUTR

100kΩ

R = 560Ω

C = 1.5nF

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

14 _______________________________________________________________________________________

Figure 12. Active Component Analog Output Filter

24.3kΩ5.23kΩ

OUTR

33pF

56pF

+5V

MAX5556–MAX5559

OUTL

V

BIAS

5.23kΩ 24.3kΩ

33pF

V

BIAS

10kΩ 59kΩ

56pF

+5V

10kΩ 59kΩ

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

______________________________________________________________________________________

15

OUTPUTS HELD

Figure 13. Internal State Diagram

AT CURRENT LEVELS

NO POWER APPLIED

POWER-UP

OUTPUTS HELD

AT GROUND

VALID CLOCK

RATIO ESTABLISHED

VALID CLOCK

RATIO RE-ESTABLISHED

VALID CLOCK

RATIO RE-ESTABLISHED

OUTPUTS IMMEDIATELY

RETURNED TO DC

QUIESCENT LEVELS

LofC

LofC

LofC

LofC

OUTPUTS LINEARLY

RAMPED TO DC

QUIESCENT LEVELS (< 1 SECOND)

INTERNAL REGISTERS

INITIALIZED (MUTE)

LOSS-

OF-

POWER

EVENT

SOFT-START

VOLUME RAMPING

NORMAL OPERATION

(FULL VOLUME)

LofC = LOSS OF CLOCK EVENT

INVALID RATIO DETECTED
MCLK TIME OUT
SCLK INT/EXT MODE CHANGED
LRCLK LOSS

OUTPUTS IMMEDIATELY

RETURNED TO GROUND

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

16 _______________________________________________________________________________________

Pop and Click Suppression

The MAX5556–MAX5559 feature a pop and click
supression routine to reduce the unwanted audible
effects of system transients. This routine produces
glitch-free operation at the outputs during power-on,
loss of clock, or invalid clock conditions. See Figure 13
for a detailed state diagram during transient conditions.

Power-Up

Once the MAX5556–MAX5559 recognize a valid
MCLK/LRCLK ratio (256, 384, or 512), the analog outputs
(OUTR and OUTL) are enabled in stages using a glitch­less ramping routine. First, the outputs ramp up to the
quiescent output voltage at a rate of 5V/s typ (see Figure

14). After the outputs reach the quiescent voltage, the
converted data stream begins soft-start ramping, achiev­ing the full-scale operation over a 20ms period.

If invalid clock signals are detected while the outputs
are DC ramping to their quiescent state, the outputs
stop ramping and hold their preset values until valid
clock signals are restored (Figure 15).

Loss of Clock and Invalid Clock Conditions

The MAX5556–MAX5559 mute both outputs after
detecting one of four invalid clock conditions. All four
devices mute their outputs to prevent propagation of
pops, clicks, or corrupted data through the signal path.
The MAX5556–MAX5559 force the outputs to the quies­cent DC voltage (2.4V) to prevent clicks in capacitive­coupled systems. Invalid clock conditions include:

1. MCLK/LRCLK ratio changes between 256, 384,

and 512

2. Transition between internal and external serial-

clock mode

3. Invalid MCLK/LRCLK ratio

4. MCLK falls below the minimum operating

frequency 2kHz

When the MCLK/LRCLK ratio returns to 256, 384, or
512 and MCLK is equal or greater than its minimum
operating frequency, the MAX5556–MAX5559 outputs
return to their full-scale setting over a soft-start mute
time of 20ms (Figure 15).

Power-Down

When the positive supply is removed from the
MAX5556–MAX5559, the outputs discharge to ground.
When power is restored, the power-up ramp routine
engages once a valid clock ratio is established (see the

Power-Up

section).

Avoid violating absolute maximum conditions by sup­plying digital inputs to the part or forcing voltages on
the analog outputs during a loss-of-power event.

Applications Information

Low-Cost Line-Level Solution

Connect the MAX5556–MAX5559 outputs through a
passive output filter as detailed in Figure 11 for a
low-cost solution. This lowpass filter yields single-pole
(20dB/decade) roll-off at a corner frequency (fC)
determined by:

In the case of Figure 11, fCis approximately 190kHz.

High-Performance Line-Level Solution

For enhanced performance, connect the MAX5556–
MAX5559 outputs to an active filter by using an opera­tional amplifier as shown in Figure 12. The use of an
active filter allows for steeper roll-off, more efficient fil­tering, and also adds the capability of a programmable
output gain.

Power-Supply Sequencing

For correct power-up sequencing, apply VDDand then
connect the input digital signals. Do not apply digital sig­nals before V

DD

is applied.

Do not violate any of the absolute maximum ratings by
removing power with the digital inputs still connected.
To correctly power down the device, first disconnect
the digital input signals, and then remove V

DD

.

f

RC

C

=

1

2π

MAX5556–MAX5559

Low-Cost Stereo Audio DACs

______________________________________________________________________________________

17

OUTPUT

Figure 14. Power-Up Sequence

Figure 15. Invalid Clock Output Response

VOLTAGE

(OUTR OR OUTL)

VALID MCLK/LRCLK RATIO

DETECTED

SETTLES AT

V

OUT_

QUIESCENT VOLTAGE (2.4V)

RAMPS UP

V

OUT_

TO QUIESCENT

VOLTAGE AT 5V/s (TYP)

BEGINS TO

V

OUT_

FOLLOW THE DATA. THE

AMPLITUDE IS RAMPED

TO FULL SCALE (20ms TYP)

TIME

INVALID CLOCK

CONDITION

OUTPUT

VOLTAGE

(OUTR OR OUTL)

MUTE: V
FORCED TO DC QUIESCENT

VALID MCLK/LRCLK

RE-ESTABLISHED AND MCLK

EQUAL OR GREATER THAN

MINIMUM OPERATING FREQUENCY

TIME

IMMEDIATELY

OUT_

LEVEL (2.4V)

SOFT START

V

OUT_

RAMPING (20ms TYP)

MAX5556–MAX5559

Power-Supply Connections and Ground

Management

Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply
inputs and analog outputs to minimize losses due to
parasitic trace resistance. Large traces also aid in mov­ing heat away from the package. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any switching noise
from coupling into the audio signal. Route the analog
paths (GND, VDD, OUTL, and OUTR) away from the
digital signals. Connect a 0.1µF capacitor in parallel
with a 4.7µF capacitor as close to VDDas possible. Low
ESR-type capacitors are recommended for supply
decoupling applications. A small value C0G-type
bypass capacitor located as close to the device as
possible is recommended in parallel with larger values.

Chip Information

PROCESS: BiCMOS

Low-Cost Stereo Audio DACs

18 _______________________________________________________________________________________

MAX5556–MAX5559

Heslington

Low-Cost Stereo Audio DACs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________

19

© 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages

.)

N

1

TOP VIEW

D

e

FRONT VIEW

INCHES

DIM

MIN

0.053A

0.004

A1

0.014

B

0.007

C
e 0.050 BSC 1.27 BSC

0.150

HE

A

B

A1

C

L

E
H 0.2440.228 5.80 6.20

0.016L

VARIATIONS:

INCHES

MINDIM

D

0.189 0.197 AA5.004.80 8

0.337 0.344 AB8.758.55 14

D

0∞-8∞

SIDE VIEW

MAX

0.069

0.010

0.019

0.010

0.157

0.050

MAX

0.3940.386D

MILLIMETERS

MAX

MIN

1.35

1.75

0.10

0.25

0.35

0.49

0.19

0.25

3.80 4.00

0.40 1.27

MILLIMETERS

MAX

MIN

9.80 10.00

N MS012

16

AC

SOICN .EPS

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE, .150" SOIC

REV.DOCUMENT CONTROL NO.APPROVAL

21-0041

1

B

1