General Description
The MAX5550 dual, 10-bit, digital-to-analog converter
(DAC) features high-output-current capability. The
MAX5550 sources up to 30mA per DAC, making it ideal
for PIN diode biasing applications. Outputs can also be
paralleled for high-current applications (up to 60mA
typ). Operating from a single +2.7V to +5.25V supply,
the MAX5550 typically consumes 1.5mA per DAC in
normal operation and less than 1µA (max) in shutdown
mode. The MAX5550 also features low output leakage
current in shutdown mode (±1µA max) that is essential
to ensure that the external PIN diodes are off.
Additional features include an integrated +1.25V
bandgap reference, and a control amplifier to ensure
high accuracy and low-noise performance. A separate
reference input (REFIN) allows for the use of an external
reference source, such as the MAX6126, for improved
gain accuracy. A pin-selectable I
2
C*-/SPI™-compatible
serial interface provides optimum flexibility for the
MAX5550. The maximum programmable output current
value is set using software and an adjustment resistor.
The MAX5550 is available in a (3mm x 3mm) 16-pin thin
QFN package, and is specified over the extended
(-40°C to +85°C) temperature range.
Applications
PIN Diode Biasing
RF Attenuator Control
VCO Tuning
Features
♦ Pin-Selectable I2C- or SPI-Compatible Interface
♦ Guaranteed Low Output Leakage Current in
Shutdown (±1µA max)
♦ Guaranteed Monotonic over Extended
Temperature Range
♦ Dual Outputs for Balanced Systems
♦ Current Outputs Source Up to 30mA per DAC
♦ Parallelable Outputs for 60mA Applications
♦ Output Stable with RF Filters
♦ Internal or External Reference Capability
♦ Digital Output (DOUT) Available for Daisy
Chaining in SPI Mode
♦ +2.7V to +5.25V Single-Supply Operation
♦ 16-Pin (3mm x 3mm) Thin QFN Package
♦ Programmable Output Current Range Set by
Software and Adjustment Resistor
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3871; Rev 0; 10/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*Purchase of I2C components from Maxim Integrated Products,
Inc., or one of its sublicensed Associated Companies, conveys
a license under the Philips I
2
C Patent Rights to use these com-
ponents in an I
2
C system, provided that the system conforms
to the I
2
C Standard Specification as defined by Philips.
SPI is a trademark of Motorola, Inc.
+1.25V
REF
REFIN
BUFFER
10-BIT CURRENT-STEERING
DAC A
P
OUTA
V
DD
FSADJA
V
DD
OUTB
FSADJB
GND
DOUT/A1
CS/A0
DIN/SDASCLK/SCL
SPI/I2C
16-BIT INPUT REGISTER
DAC REGISTER A
DAC REGISTER B
10-BIT CURRENT-STEERING
DAC B
MAX5550
P
Functional Diagram
Pin Configuration appears at end of data sheet.
PART
MAX5550ETE
TEMP
RANGE
-40°C to
+85°C
PINPACKAGE
16 Thin QFN T1633F-3 ACZ
PKG
CODE
MARK
TOP
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND .............................................................-0.3V to +6V
OUTA, OUTB to GND.................................-0.3V to (V
DD
+ 0.3V)
REFIN, CS/AO, DOUT/AI, SPI/I2C, FSADJA,
FSADJB to GND ......................................-0.3V to (V
DD
+ 0.3V)
SCLK/SCL, DIN/SDA ................................................-0.3V to +6V
Continuous Power Dissipation (T
A
= +85°C)
16-Pin Thin QFN (derate 17.5mW/°C above +70°C) ..1398.6mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
ELECTRICAL CHARACTERISTICS
(VDD= +2.7V to +5.25V, GND = 0, V
REFIN
= +1.25V, internal reference, R
FSADJ_
= 20kΩ; compliance voltage = (VDD- 0.6V),
V
SCLK/SCL
= 0, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +3.0V and TA= +25°C.) (Note 1)
STATIC PERFORMANCE—ANALOG SECTION
Resolution 10 Bits
Integral Nonlinearity INL I
Differential Nonlinearity DNL Guaranteed monotonic ±1 LSB
Offset I
Zero-Scale Error I
Full-Scale Error
REFERENCE
Internal Reference Range 1.21 1.25 1.29 V
Internal Reference Tempco 30 ppm/°C
External Reference Range 0.5 1.5 V
External Reference Input Current 108 225 µA
DAC OUTPUTS
Full-Scale Current (Note 3) 1 30 mA
Output Current Leakage in
Shutdown
Output Capacitance 10 pF
Current Source Dropout Voltage
(V
Output Impedance at Full-Scale
Current
Capacitive Load to Ground C
Series Inductive Load L
Maximum FSADJ_ Capacitive
Load
DYNAMIC PERFORMANCE
Settling Time t
Digital Feedthrough 2 nVs
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
- V
OUT
_)
DD
_ = 1mA to 30mA (Note 2) ±2 LSB
OUT
OS
_ = 1mA to 30mA, code = 0x000 1 µA
OUT
I
_ = 1mA to 30mA, code = 0x3FF,
OUT
includes offset
I
_ = 30mA 1
OUT
I
_ = 20mA
OUT
LOAD
LOAD
C
FSADJ_
C
S
LOAD
= 24pF, L
-50 -16 LSB
-16 LSB
±1 µA
TA = +25°C 0.55
= -40°C to +85°C 0.6
T
A
100 kΩ
10 nF
100 nH
75 pF
= 27nH (Note 4) 30 µs
LOAD
V
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +2.7V to +5.25V, GND = 0, V
REFIN
= +1.25V, internal reference, R
FSADJ_
= 20kΩ; compliance voltage = (VDD- 0.6V),
V
SCLK/SCL
= 0, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +3.0V and TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Digital-to-Analog Glitch Impulse 40 nVs
DAC-to-DAC Current Matching 2%
Wake-Up Time
VDD = +3V 400
= +5V 10
V
DD
µs
POWER SUPPLIES
Supply Voltage V
Supply Current I
DD
DD
VDD = +5.25V, no load 3 6 mA
+2.70 +5.25 V
Shutdown Current 1.2 µA
LOGIC AND CONTROL INPUTS
0.7 x
V
DD
V
Input High Voltage (Note 5) V
+2.7V ≤ V
IH
DD
≤ +3.4V
+3.4V < VDD ≤ +5.25V 2.4
Input Low Voltage V
Input Hysteresis V
Input Capacitance C
Input Leakage Current I
Output Low Voltage V
Output High Voltage V
HYS
IN
OL
OH
(Note 5) 0.8 V
IL
0.1 x
V
DD
IN
I
= 3mA 0.6 V
SINK
V
I
SOURCE
= 2mA
DD
0.5
10 pF
-
V
±1 µA
V
I2C TIMING CHARACTERISTICS (Figure 2)
SCL Clock Frequency f
Setup Time for START Condition t
Hold Time for START Condition t
SCL Pulse-Width Low t
SCL Pulse-Width High t
Data Setup Time t
Data Hold Time t
SCL Rise Time t
SCL Fall Time t
SDA Rise Time t
SDA Fall Time t
SCL
SU:STA
HD:STA
LOW
HIGH
SU:DAT
HD:DAT
RCL
FCL
RDA
FDA
600 ns
600 ns
130 ns
600 ns
100 ns
070ns
20 + 0.1
x C
B
20 + 0.1
x C
B
20 + 0.1
x C
B
20 + 0.1
x C
B
400 kHz
300 ns
300 ns
300 ns
300 ns
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +2.7V to +5.25V, GND = 0, V
REFIN
= +1.25V, internal reference, R
FSADJ_
= 20kΩ; compliance voltage = (VDD- 0.6V),
V
SCLK/SCL
= 0, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +3.0V and TA= +25°C.) (Note 1)
Note 1: 100% production tested at TA= +25°C. Limits over temperature are guaranteed by design.
Note 2: INL linearity is guaranteed from code 60 to code 1024.
Note 3: Connect a resistor from FSADJ_ to GND to adjust the full-scale current. See the Reference Architecture and Operation section.
Note 4: Settling time is measured from (0.25 x full scale) to (0.75 x full scale).
Note 5: The device draws higher supply current when the digital inputs are driven with voltages between (V
DD
- 0.5V) and (GND +
0.5V). See the Supply Current vs. Digital Input Voltage graph in the Typical Operating Characteristics.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Bus Free Time Between a STOP
and START Condition
Setup Time for STOP Condition t
Maximum Capacitive Load for
Each Bus Line
SPI TIMING CHARACTERISTICS (Figure 6)
SCLK Clock Period t
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall to SCLK Rise Setup Time t
SCLK Rise to CS Rise Hold Time t
DIN Setup Time t
DIN Hold Time t
SCLK Fall to DOUT Transition t
CS Fall to DOUT Enable t
CS Rise to DOUT Disable t
SCLK Rise to CS Fall Delay t
CS Rise to SCLK Rise Hold Time t
CS Pulse-Width High t
SPI TIMING CHARACTERISTICS FOR DAISY CHAINING (Figure 6)
SCLK Clock Period t
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall to SCLK Rise Setup Time t
SCLK Rise to CS Rise Hold Time t
DIN Setup Time t
DIN Hold Time t
SCLK Fall to DOUT Transition t
CS Fall to DOUT Enable t
CS Rise to DOUT Disable t
SCLK Rise to CS Fall Delay t
CS Rise to SCLK Rise Hold Time t
CS Pulse-Width High t
t
BUF
SU:STO
C
B
CP
CH
CL
CSS
CSH
DS
DH
C
DO1
CSE
CSD
CS0
CS1
CSW
CP
CH
CL
CSS
CSH
DS
DH
DO1
CSE
CSD
CS0
CS1
CSW
= 30pF 40 ns
LOAD
C
= 30pF 40 ns
LOAD
= 30pF 40 ns
C
LOAD
C
= 30pF 40 ns
LOAD
C
= 30pF 40 ns
LOAD
= 30pF 40 ns
C
LOAD
1.3 µs
160 ns
400 pF
100 ns
40 ns
40 ns
25 ns
50 ns
40 ns
0ns
50 ns
40 ns
100 ns
200 ns
80 ns
80 ns
25 ns
50 ns
40 ns
0ns
50 ns
40 ns
100 ns
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(VDD= +3.0V, GND = 0, V
REFIN
= +1.25V, internal reference, R
FSADJ_
= 20kΩ, TA= +25°C. unless otherwise noted).
INL vs. CODE
2.0
1.5
1.0
0.5
0
INL (LSB)
-0.5
-1.0
-1.5
-2.0
0 128 384 640256 512 768 896 1024
CODE
DNL vs. TEMPERATURE
0.40
0.35
0.30
0.25
0.20
DNL (LSB)
0.15
0.10
0.05
0
-40 -15 10 35 60 85
TEMPERATURE (°C)
1.00
0.75
MAX5550 toc01
0.50
0.25
DNL (LSB)
-0.25
-0.50
-0.75
-1.00
MAX5550 toc04
INL (LSB)
DNL vs. CODE
0
0 128 384 640256 512 768 896 1024
CODE
MAXIMUM INL ERROR vs.
3.0
2.5
2.0
1.5
1.0
0.5
OUTPUT CURRENT RANGES
0
1–2
1.5–3 4.5–9
OUTPUT CURRENT RANGE (mA)
8–162–5
15–30
4.0
3.5
MAX5550 toc02
3.0
2.5
2.0
INL (LSB)
1.5
1.0
0.5
0
-40 -15 10 35 60 85
4.5
4.0
MAX5550 toc05
3.5
3.0
2.5
2.0
1.5
ZERO-SCALE CURRENT (nA)
1.0
0.5
0
-40 10-15 35 60 85
INL vs. TEMPERATURE
MAX5550 toc03
TEMPERATURE (°C)
ZERO-SCALE OUTPUT CURRENT
vs. TEMPERATURE
MAX5550 toc06
VDD = 5V
VDD = 3V
TEMPERATURE (°C)
FULL-SCALE CURRENT vs. TEMPERATURE
29.88
29.86
29.84
29.82
29.80
29.78
29.76
FULL-SCALE CURRENT (mA)
29.74
29.72
-40 -15 10 35 60 85
VDD = 3V
TEMPERATURE (°C)
VDD = 5V
MAX5550 toc07
SETTLING TIME
(FULL-SCALE POSITIVE STEP)
10µs/div
R
C
LOAD
LOAD
MAX5550 toc08
= 65Ω
= 24pF
CS
2V/div
V
OUT_
1V/div
SETTLING TIME
(FULL-SCALE NEGATIVE STEP)
10µs/div
R
C
LOAD
LOAD
MAX5550 toc09
= 65Ω
= 24pF
CS
2V/div
V
OUT_
1V/div
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD= +3.0V, GND = 0, V
REFIN
= +1.25V, internal reference, R
FSADJ_
= 20kΩ, TA= +25°C. unless otherwise noted).
GLITCH IMPULSE
MAX5548 toc10
V
OUT_
AC-COUPLED
40ns/div
CS
1V/div
10mV/div
R
LOAD
= 65Ω
C
LOAD
= 24pF
620
520
420
320
220
2.5 4.03.0 3.5 4.5 5.0 5.5
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX5550 toc11
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (nA)
NO LOAD, CODE = 0x00
620
520
420
320
220
-40 10-15 35 60 85
SHUTDOWN CURRENT vs. TEMPERATURE
MAX5550 toc12
TEMPERATURE (°C)
SHUTDOWN CURRENT (nA)
NO LOAD, CODE = 0x00
VDD = 5V
VDD = 3V
1.246
1.248
1.247
1.250
1.249
1.251
1.252
-40 10-15 35 60 85
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX5550 toc14
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE (V)
NO LOAD, CODE = 0x00
1.25100
1.25075
1.25050
1.25025
1.25000
2.5 4.03.0 3.5 4.5 5.0 5.5
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX5550 toc13
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE (V)
NO LOAD, CODE = 0x00
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(VDD= +3.0V, GND = 0, V
REFIN
= +1.25V, internal reference, R
FSADJ_
= 20kΩ, TA= +25°C. unless otherwise noted).
2.80
NO LOAD, CODE = 0x00
2.75
2.70
SUPPLY CURRENT (mA)
2.65
2.60
2.5 4.03.0 3.5 4.5 5.0 5.5
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE
EXTERNAL REFERENCE
SUPPLY VOLTAGE (V)
WAKE-UP TIME
R
C
LOAD
LOAD
MAX5550 toc17
= 65Ω
= 24pF
MAX5550 toc15
CS
2V/div
V
OUT_
1V/div
SUPPLY CURRENT
vs. TEMPERATURE
2.760
NO LOAD, CODE = 0x00
2.755
2.750
2.745
2.740
SUPPLY CURRENT (mA)
2.735
2.730
35
30
25
20
(mA)
OUT
15
I
10
5
VDD = 5V
-40 10-15 35 60 85
TEMPERATURE (°C)
I
vs. V
OUT
VDD = 3V
MAX5550 toc16
VDD = 3V
OUT
MAX5550 toc18
VDD = 5V
400µs/div
0
012345
V
(V)
OUT
SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE
10
NO LOAD, CODE = 0x00
VDD = 5V
SUPPLY CURRENT (mA)
1
012345
VDD = 3V
DIGITAL INPUT VOLTAGE (V)
MAX5550 toc19
DIGITAL FEEDTHROUGH
R
LOAD
C
LOAD
400µs/div
MAX5550 toc20
= 65Ω
= 24pF
SCLK
2V/div
V
OUT_
AC-COUPLED
10mV/div
MAX5550
Detailed Description
Architecture
The MAX5550 10-bit, dual current-steering DAC (see
the Functional Diagram) operates with DAC update
rates up to 10Msps in SPI mode and 400ksps in I2C
mode. The converter consists of a 16-bit shift register
and input DAC registers, followed by a current-steering
array. The current-steering array generates full-scale
currents up to 30mA per DAC. An integrated +1.25V
bandgap reference, control amplifier, and an external
resistor determine each data converter’s full-scale output range.
Reference Architecture and Operation
The MAX5550 provides an internal +1.25V bandgap reference or accepts an external reference voltage source
between +0.5V and +1.5V. REFIN serves as the input for
an external low-impedance reference source. Leave
REFIN unconnected in internal reference mode. Internal
or external reference mode is software selectable
through the SPI/I2C serial interface.
The MAX5550’s reference circuit (Figure 1) employs a
control amplifier to regulate the full-scale current (IFS)
for the current outputs of the DAC. This device has a
software-selectable full-scale current range (see the
command summary in Table 4). After selecting a current range, an external resistor (R
FSADJ
_) sets the fullscale current. See Table 1 for a matrix of IFSand
R
FSADJ
selections.
During startup, when the power is first applied, the
MAX5550 defaults to the external reference mode, and
to the 1mA–2mA full-scale current-range mode.
DAC Data
The 10-bit DAC data is decoded as offset binary, MSB
first, with 1 LSB = I
FS
/ 1024, and converted into the cor-
responding current as shown in Table 2.
Serial Interface
The MAX5550 features a pin-selectable SPI/I2C serial
interface. Connect SPI/I2C to GND to select I2C mode, or
connect SPI/I2C to VDDto select SPI mode. SDA and
SCL (I2C mode) and DIN, SCLK, and CS (SPI mode)
facilitate communication between the MAX5550 and the
master. The serial interface remains active in shutdown.
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
SCLK/SC
1
2 DIN/SDA Serial Data Input. Connect SDA to VDD through a 2.4kΩ resistor in I2C mode.
3 CS/A0
4 SPI/I2C
5 DOUT/A1
6, 13, 15 N.C. No Connection. Leave unconnected or connect to GND.
7 REFIN
8, 16 GND Ground
9 OUTB DACB Output. OUTB provides up to 30mA of output current.
10 FSADJB
11 FSADJA
12 OUTA DACA Output. OUTA provides up to 30mA of output current.
14 V
Serial Clock Input. Connect SCL to VDD through a 2.4kΩ resistor in I2C mode.
Chip-Select Input in SPI Mode/Address Select 0 in I
or GND to set the device address in I2C mode.
SPI/I2C Select Input. Connect SPI/I2C to V
mode.
Serial Data Output in SPI Mode/Address Select 1 in I
other devices or to read back in SPI mode. The digital data is clocked out on SCLK’s falling edge. Connect
A1 to V
Refer ence Inp ut. D r i ve RE FIN w i th an exter nal r efer ence sour ce b etw een + 0.5V and + 1.5V . Leave RE FIN
unconnected i n i nter nal r efer ence m od e. Byp ass w i th a 0.1µF cap aci tor to GN D as cl ose to the d evi ce as p ossi b l e.
D AC B Ful l - S cal e Ad j ust Inp ut. For m axi m um ful l - scal e outp ut cur r ent, connect a 20kΩ r esi stor b etw een FS AD JB
and GN D . For m i ni m um ful l - scal e cur r ent, connect a 40kΩ r esi stor b etw een FS AD JB an d GN D .
D AC A Ful l - S cal e Ad j ust Inp ut. For m axi m um ful l - scal e outp ut cur r ent, connect a 20kΩ r esi stor b etw een FS AD JA
and GN D . For m i ni m um ful l - scal e cur r ent, connect a 40kΩ r esi stor b etw een FS AD JA an d GN D .
Power Supply Input. Connect VDD to a +2.7 to +5.25V power supply. Bypass VDD to GND with a 0.1µF
DD
capacitor as close to the device as possible.
or GND to set the device address in I2C mode.
DD
DD
2
C Mode. CS is an active-low input. Connect A0 to V
to select SPI mode, or connect SPI/I2C to GND to select I2C
2
C Mode. Use DOUT to daisy chain the MAX5550 to
DD
I2C Compatibility (SPI/
I2C
= GND)
The MAX5550 is compatible with existing I2C systems
(Figure 2). SCL and SDA are high-impedance inputs;
SDA has an open-drain output that pulls the data line
low during the ninth clock pulse. SDA and SCL require
pullup resistors (2.4kΩ or greater) to VDD. Optional
resistors (24Ω) in series with SDA and SCL protect the
device inputs from high-voltage spikes on the bus lines.
Series resistors also minimize crosstalk and undershoot
of the bus signals. The communication protocol supports standard I2C 8-bit communications. The device’s
address is compatible with 7-bit I2C addressing protocol only. Ten-bit address formats are not supported.
Only write commands are accepted by the MAX5550.
Note: I2C readback is not supported.
Bit Transfer
One data bit transfers during each SCL rising edge.
The MAX5550 requires nine clock cycles to transfer
data into or out of the DAC register. The data on SDA
must remain stable during the high period of the SCL
clock pulse. Changes in SDA while SCL is high are
read as control signals (see the START and STOP
Conditions section). Both SDA and SCL idle high.
START and STOP Conditions
The master initiates a transmission with a START condition (S), (a high-to-low transition on SDA with SCL high).
The master terminates a transmission with a STOP condition (P), (a low-to-high transition on SDA while SCL is
high) (Figure 3). A START condition from the master
signals the beginning of a transmission to the
MAX5550. The master terminates transmission by issuing a STOP condition. The STOP condition frees the
bus. If a repeated START condition (S
r
) is generated
instead of a STOP condition, the bus remains active.
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
_______________________________________________________________________________________ 9
Figure 1. Reference Architecture and Output Current Adjustment
*Negative output current values = 0
Table 1. Full-Scale Output Current and R
FSADJ_
Selection Based on a +1.25V (typ)
Reference Voltage
*See the command summary in Table 4.
DAC CODE I
OUT
_
11 1111 1111
10 0000 0000
00 0000 0001*
00 0000 0000 0
Table 2. DAC Output Code Table
FULL-SCALE OUTPUT CURRENT (mA)* R
1mA–2mA 1.5mA–3mA 2.5mA–5mA 4.5mA–9mA 8mA–16mA 15mA–30mA Calculated 1% EIA Std
1.00 1.500 2.500 4.500 8.00 15.00 40 40.2
1.25 1.875 3.125 5.625 10.00 18.75 35 34.8
1.50 2.250 3.750 6.750 12.00 22.50 30 30.1
1.75 2.625 4.375 7.875 14.00 26.25 25 24.9
2.00 3.000 5.000 9.000 16.00 30.00 20 20.0
FSADJ
(kΩ)
+1.25V
REFERENCE
R
FSADJ_
FSADJ
I
FSADJ
V
DD
CURRENT-SOURCE
ARRAY DAC
GND
OUT_
1023
1023
1023
FS
×−II
1024
FS
×−II
1024
FS
×−II
1024
||
OS
||
OS
||
OS
MAX5550
Early STOP Conditions
The MAX5550 recognizes a STOP condition at any point
during transmission except if a STOP condition occurs in
the same high pulse as a START condition (Figure 4).
This condition is not allowed in the I2C format.
Repeated START Conditions
A repeated START (S
r
) condition is used when the bus
master is writing to several I
2
C devices and does not
want to relinquish control of the bus. The MAX5550’s
serial interface supports continuous write operations
with an S
r
condition separating them.
Acknowledge Bit (ACK)
Successful data transfers are acknowledged with an
acknowledge bit (ACK). Both the master and the
MAX5550 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull
SDA low before the rising edge of the acknowledgerelated clock pulse (ninth pulse) and keep it low during
the high period of the clock pulse (Figure 5).
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful data transfer, the master should reattempt communication at a later time.
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
10 ______________________________________________________________________________________
Figure 3. START and STOP Conditions
Figure 4. Early STOP Conditions
Figure 2. I2C Serial-Interface Timing Diagram
S
t
RDA
SDA
t
FDA
t
t
SU:STA
t
HD:STA
HD:DAT
t
SU:DAT
SCL
t
RCL
t
HIGH
t
FCL
t
LOW
t
FCL
t
LOW
t
HIGH
PSr
t
SU:STO
t
RCL
SPSr
SDA
SCL
SCL
SDA
STOP START
LEGAL STOP CONDITION
SCL
SDA
START
ILLEGAL EARLY STOP CONDITION
ILLEGAL
STOP
Slave Address
A master initiates communication with a slave device
by issuing a START condition followed by a slave
address (see Table 3). The slave address consists of 7
address bits and a read/write bit (R/W). When idle, the
device continuously waits for a START condition followed by its slave address. When the device recognizes its slave address, it acquires the data and
executes the command. The first 5 bits (MSBs) of the
slave address have been factory programmed and are
always 01100. Connect A1 and A0 to VDDor GND to
program the remaining 2 bits of the slave address. Set
the least significant bit (LSB) of the address byte (R/W)
to zero to write to the MAX5550. After receiving the
address, the MAX5550 (slave) issues an acknowledge
by pulling SDA low for one clock cycle. I2C read commands (R/W = 1) are not acknowledged by the
MAX5550.
Write Cycle
The write command requires 27 clock cycles. In write
mode (R/W = 0), the command/data byte that follows
the address byte controls the MAX5550 (Table 3). The
registers update on the rising edge of the 26th SCL
pulse. Prematurely aborting the write cycle does not
update the DAC. See Table 4 for a command summary.
SPI Compatibility (SPI/
I2C
= VDD)
The MAX5550 is compatible with the 3-wire SPI serial
interface (Figure 6). This interface mode requires three
inputs: chip-select (CS), data clock (SCLK), and data in
(DIN). Drive CS low to enable the serial interface and
clock data synchronously into the shift register on each
SCLK rising edge.
The MAX5550 requires 16 clock cycles to clock in 6
command bits (C5–C0) and 10 data bits (D9–D0)
(Figure 7). After loading data into the shift register,
drive CS high to latch the data into the appropriate
DAC register and disable the serial interface. Keep CS
low during the entire serial data stream to avoid corruption of the data. See Table 4 for a command summary.
Shutdown Mode
The MAX5550 has a software shutdown mode that
reduces the supply current to less than 1µA. Shutdown
mode disables the DAC outputs. The serial interface
remains active in shutdown. This provides the flexibilty to
update the registers while in shut down. Recycling the
power supply resets the device to the default settings.
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
______________________________________________________________________________________ 11
Figure 5. Acknowledge Condition
Table 3. Write Operation
*Read operation not supported.
SDA
SCL
S
T
A
R
T
Master
SDA
Slave
SDA
S01 100A1A00 C5C4C3C2C1C0D9 D8 D7D6D5D4D3D2D1D0 P
ADDRESS
BYTE
S
R/ W*
ACKNOWLEDGE
12 89
COMMAND/DATA BYTE DATA BYTE
A
C
K
A
C
K
S
T
O
P
A
C
K
MAX5550
Applications Information
Daisy Chaining (SPI/
I2C
= VDD)
In standard SPI-/QSPI™-/MICROWIRE™-compatible
systems, a microcontroller (µC) communicates with its
slave devices through a 3- or 4-wire serial interface.
The typical interface includes a chip-select signal (CS),
a serial clock (SCLK), a data input signal (DIN), and
sometimes a data signal output (DOUT). In this system,
the µC allots an independent slave-select signal (SS_)
to each slave device so that they can be addressed
individually. Only the slaves with their CS inputs asserted low acknowledge and respond to the activity on the
serial clock and data lines. This is simple to implement
when there are very few slave devices in the system.
An alternative method is daisy chaining. Daisy
chaining, in serial-interface applications, is the method
of propagating commands through devices connected
in series (see Figure 8).
Daisy chain devices by connecting the DOUT of one
device to the DIN of the next. Connect the SCLK of all
devices to a common clock and connect the CS of all
devices to a common slave-select line. Data shifts out of
DOUT 16.5 clock cycles after it is shifted into DIN on the
falling edge of SCLK. In this configuration, the µC only
needs three signals (SS, SCK, and MOSI) to control all of
the slaves in the network. The SPI-/QSPI-/MICROWIREcompatible serial interface normally works at up to
10MHz, but must be slowed to 5MHz if daisy chaining.
DOUT is high impedance when CS is high.
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
12 ______________________________________________________________________________________
Figure 7. SPI-Interface Format
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Figure 6. SPI-Interface Timing Diagram
CS
t
CSO
t
CSS
t
CP
t
CSH
t
CSW
t
CS1
SCLK
DIN
t
CSE
DOUT
CS
SCLK
1 2 3 4 5 6 7 8 9 10111213141516
DIN
t
DS
MSB
C5 C4
t
CH
t
DH
MSB
t
DO1
C1 C0
t
CL
D9 D8
LSB
D7 D6 D5 D4 D3 D2 D1 D0C3 C2
t
CSD
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
______________________________________________________________________________________ 13
Table 4. Command Summary
SERIAL DATA INPUT
C5 C4 C3 C2 C1 C0 D9–D0
000000 XXXXXXXXXX No operation.
000001 10-bit DAC data
000010 10-bit DAC data Load DAC register A and input register A from the shift register.
000011 10-bit DAC data Load DAC register B and input register B from the shift register.
000100 10-bit DAC data
000101 10-bit DAC data
000110 10-bit DAC data
000111 XXXXXXXXXX Update both DAC registers from their corresponding input registers.
001001 XXXXXXXXXX Update DAC register A from input register A.
001010 XXXXXXXXXX Update DAC register B from input register B.
001011 XXXXXXXXXX Internal reference mode.
001100 XXXXXXXXXX External reference mode (default mode at power-up).
001101 XXXXXXXXXX Shut down both DACs.
001110 XXXXXXXXXX Shut down DACA.
001111 XXXXXXXXXX Shut down DACB.
010000 XXXXXXXXXX
010001 XXXXXXXXXX DACA 1.5mA–3mA full-scale current range mode.
010010 XXXXXXXXXX DACA 2.5mA–5mA full-scale current range mode.
010011 XXXXXXXXXX DACA 4.5mA–9mA full-scale current range mode.
010100 XXXXXXXXXX DACA 8mA–16mA full-scale current range mode.
010101 XXXXXXXXXX DACA 15mA–30mA full-scale current range mode.
101101 XXXXXXXXXX Power up both DACs.
101110 XXXXXXXXXX Power up DACA.
101111 XXXXXXXXXX Power up DACB.
110000 XXXXXXXXXX
110001 XXXXXXXXXX DACB 1.5mA–3mA full-scale current range mode.
110010 XXXXXXXXXX DACB 2.5mA–5mA full-scale current range mode.
110011 XXXXXXXXXX DACB 4.5mA–9mA full-scale current range mode.
110100 XXXXXXXXXX DACB 8mA–16mA full-scale current range mode.
110101 XXXXXXXXXX DACB 15mA–30mA full-scale current range mode.
Load DAC data to both DAC registers and both input registers from the
shift register.
Load both channel input registers from the shift register, both DAC
registers are unchanged.
Load input register A from the shift register; DAC register A is
unchanged.
Load input register B from the shift register; DAC register B is
unchanged.
DACA 1mA–2mA full-scale current range mode (default mode at
power-up)
DACB 1mA–2mA full-scale current range mode (default mode at
power-up)
FUNCTIONS
MAX5550
Power Sequencing
Ensure that the voltage applied to REFIN does not
exceed VDDat any time. If proper power sequencing is
not possible, connect an external Schottky diode
between REFIN and VDDto ensure compliance with the
absolute maximum ratings.
Power-Supply Bypassing and Ground
Management
Digital or AC transient signals on GND create noise at
the analog output. Return GND to the highest quality
ground plane available. For extremely noisy environments, bypass REFIN and VDDto GND with 1µF and
0.1µF capacitors with the 0.1µF capacitor as close to
the device as possible. Careful PC board ground layout
minimizes crosstalk between the DAC outputs and
digital inputs.
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
14 ______________________________________________________________________________________
Figure 8. Daisy-Chain Configuration
15
16
14
13
5
6
7
CS/AO
SPI/I2C
8
SCLK/SCL
FSADJB
OUTB
OUTA
13
V
DD
4
12 10 9
N.C.
GND
GND
REFIN
N.C.
DOUT/A1
MAX5550
DIN/SDA FSADJA
2
11
N.C.
THIN QFN (3mm x 3mm)
TOP VIEW
Pin Configuration
Chip Information
PROCESS: BiCMOS
MAX5550
CONTROLLER
DEVICE
DIN(0)
SCLK
CS
DOUT(0)
MAX5550
DIN(1)
SCLK
DOUT(1)
CS
MAX5550
DIN(2)
SCLK
DOUT(2)
CS
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
Freed 7/13/05
MARKING
D/2
D
0.10 C 0.08 C
E/2
AAAA
E
(ND - 1) X e
C
L
C
L
C
L
A
A2
A1
L
e
(NE - 1) X e
D2/2
e
k
E2/2
L
E2
PACKAGE OUTLINE
12, 16L THIN QFN, 3x3x0.8mm
b
C
L
e
21-0136
D2
0.10 M C A B
L
12x16L QFN THIN.EPS
1
F
2
PKG
12L 3x3
REF. MIN.
NOM. MAX. NOM.
0.70
0.75
A
b
0.20
0.25
D
2.90
3.00
2.90
3.00
E
e
0.50 BSC.
0.45
0.55
L
N
12
NE
3
A1ND0
0.0230.05
0.20 REF
A2
-
0.25
k
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
10. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY
11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
MIN. MAX.
0.80
0.70
0.30
0.20
3.10
2.90
2.90
3.10
0.30
0.65
-
0.25
16L 3x3
3.00
0.50 BSC.
040.02
0.20 REF
0.75
0.80
0.25
0.30
3.10
3.00
3.10
0.40
0.50
16
4
0.05
-
-
PKG.
CODES
T1233-1
T1233-3 1.10 1.25 0.95 1.10
T1633-2 0.95
T1633F-3 0.65
T1633FH-3 0.65
T1633-4
EXPOSED PAD VARIATIONS
D2
MAX.
NOM.
1.10
1.10T1633-1 0.95
1.10
0.80
0.80
1.10
MIN.
1.25
0.95
1.25
0.95
0.95
0.65
0.95
1.25
0.95
MIN.
0.95
0.95
E2
PIN ID
NOM.
MAX.
1.10
1.25
0.35 x 45°
0.35 x 45°1.25 WEED-10.95
1.251.100.951.25
0.35 x 45° WEED-2
1.10
1.25
0.35 x 45°
0.80
0.95
0.225 x 45°
0.80 0.95
0.225 x 45°0.65
1.10
1.25
0.35 x 45°
PACKAGE OUTLINE
12, 16L THIN QFN, 3x3x0.8
JEDEC
WEED-1
WEED-2
WEED-2
WEED-2
WEED-2
21-0136
DOWN
BONDS
ALLOWED
NO
YES
YESWEED-11.251.100.95 0.35 x 45°1.251.100.95T1233-4
NO
YES
N/A
N/A
NO
2
F
2
Loading...