Rainbow Electronics MAX5531 User Manual

Page 1

General Description

The MAX5530/MAX5531 are single, 12-bit, ultra-lowpower, voltage-output, digital-to-analog converters (DACs) offering Rail-to-Rail®buffered voltage outputs. The DACs operate from a 1.8V to 5.5V supply and consume less than 6µA, making them desirable for lowpower and low-voltage applications. A shutdown mode reduces overall current, including the reference input current, to just 0.18µA. The MAX5530/MAX5531 use a 3-wire serial interface that is compatible with SPI™, QSPI™, and MICROWIRE™.

At power-up, the MAX5530/MAX5531 outputs are driven to zero scale, providing additional safety for applications that drive valves or for other transducers that must be off during power-up. The zero-scale outputs enable glitchfree power-up.

The MAX5530 accepts an external reference input. The MAX5531 contains an internal reference and provides an external reference output. Both devices have forcesense-configured output buffers.

The MAX5530/MAX5531 are available in a 4mm x 4mm x

0.8mm, 12-pin, thin QFN package and are guaranteed over the extended -40°C to +85°C temperature range.

For 10-bit compatible devices, refer to the MAX5520/ MAX5521 data sheet. For 8-bit compatible devices, refer to the MAX5510/MAX5511 data sheet.

Applications

Portable Battery-Powered Devices Instrumentation Automatic Trimming and Calibration in Factory

or Field Programmable Voltage and Current Sources Industrial Process Control and Remote

Industrial Devices Remote Data Conversion and Monitoring Chemical Sensor Cell Bias for Gas Monitors Programmable Liquid Crystal Display (LCD) Bias

Features

♦ Ultra-Low 6µA Supply Current ♦ Shutdown Mode Reduces Supply Current to

0.18µA (max)

♦ Single +1.8V to +5.5V Supply ♦ Small 4mm x 4mm x 0.8mm Thin QFN Package ♦ Flexible Force-Sense-Configured Rail-to-Rail

Output Buffers

♦ Internal Reference Sources 8mA of Current

(MAX5531)

♦ Fast 16MHz 3-Wire SPI-/QSPI-/MICROWIRE-

Compatible Serial Interface

♦ TTL- and CMOS-Compatible Digital Inputs with

Hysteresis

♦ Glitch-Free Outputs During Power-Up

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit,

Voltage-Output DACs

________________________________________________________________ Maxim Integrated Products 1

12FB11

N.C.10OUT

N.C.6N.C.

2SCLK

7DIN

GND

N.C.

MAX5530 MAX5531

REFIN (MAX5530)

REFOUT(MAX5531)

THIN QFN

TOP VIEW

Pin Configuration

Ordering Information

Selector Guide

19-3063; Rev 0; 1/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART REFERENCE TOP MARK

MAX5530ETC External AACS MAX5531ETC Internal AACT

Rail-to-Rail is a registered trademark of Nippon Motorola, Inc. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp

*EP = Exposed paddle (internally connected to GND).

PART TEMP RANGE PIN-PACKAGE

MAX5530ETC -40°C to +85°C 12 Thin QFN-EP* MAX5531ETC -40°C to +85°C 12 Thin QFN-EP*

Page 2

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit, Voltage-Output DACs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= +1.8V to +5.5V, OUT unloaded, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND..............................................................-0.3V to +6V

OUT to GND ...............................................-0.3V to (V

+ 0.3V)

FB to GND ..................................................-0.3V to (V

+ 0.3V)

SCLK, DIN,

CS to GND ..............................-0.3V to (V

+ 0.3V)

REFIN, REFOUT to GND ............................-0.3V to (V

+ 0.3V)

Continuous Power Dissipation (T

= +70°C)

Thin QFN (derate 16.9mW/°C above +70°C..............1349mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature..................................................... +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC ACCURACY (MAX5530 EXTERNAL REFERENCE)

Resolution N 12 Bits

VDD = 5V, V

REF

= 4.096V ±4 ±8

Integral Nonlinearity (Note 1) INL

= 1.8V, V

REF

= 1.024V ±4 ±8

LSB

Guaranteed monotonic, V

= 5V, V

REF

= 4.096V

±1

Differential Nonlinearity (Note 1) DNL

Guaranteed monotonic, V

= 1.8V, V

REF

= 1.024V

±1

LSB

VDD = 5V, V

REF

= 4.096V ±1

Offset Error (Note 2) V

VDD = 1.8V, V

REF

= 1.024V ±1

Offset-Error Temperature Drift ±2

µV/°C

VDD = 5V, V

REF

= 4.096V ±2 ±4

Gain Error (Note 3) GE

= 1.8V, V

REF

= 1.024V ±2 ±4

LSB

Gain-Error Temperature Coefficient

±4

ppm/°C

Power-Supply Rejection Ratio PSRR 1.8V ≤ VDD ≤ 5.5V 85 dB

STATIC ACCURACY (MAX5531 INTERNAL REFERENCE)

Resolution N 12 Bits

VDD = 5V, V

REF

= 3.9V ±4 ±8

Integral Nonlinearity (Note 1) INL

= 1.8V, V

REF

= 1.2V ±4 ±8

LSB

Guaranteed monotonic, V

= 5V, V

REF

= 3.9V

±1

Differential Nonlinearity (Note 1) DNL

Guaranteed monotonic, V

= 1.8V, V

REF

= 1.2V

±1

LSB

VDD = 5V, V

REF

= 3.9V ±1

Offset Error (Note 2) V

VDD = 1.8V, V

REF

= 1.2V ±1

Offset-Error Temperature Drift ±2

µV/°C

VDD = 5V, V

REF

= 3.9V ±2 ±4

Gain Error (Note 3) GE

= 1.8V, V

REF

= 1.2V ±2 ±4

LSB

Gain-Error Temperature Coefficient

±4

ppm/°C

±0.2

±20 ±20

Page 3

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit,

Voltage-Output DACs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +1.8V to +5.5V, OUT unloaded, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

Power-Supply Rejection Ratio PSRR 1.8V ≤ VDD ≤ 5.5V 85 dB

REFERENCE INPUT (MAX5530)

Reference-Input Voltage Range V

REFIN

Normal operation 4.1 MΩ

Reference-Input Impedance R

REFIN

In shutdown 2.5 GΩ

REFERENCE OUTPUT (MAX5531)

No external load, VDD = 1.8V No external load, VDD = 2.5V No external load, VDD = 3V

Initial Accuracy

No external load, VDD = 5V

Output-Voltage Temperature Coefficient

TA = -40°C to +85°C (Note 4) 12 30

ppm/°C

Line Regulation V

REFOUT

< VDD - 200mV (Note 5) 2 200 µV/V

0 ≤ I

REFOUT

≤ 1mA, sourcing, VDD = 1.8V,

REF

= 1.2V

0.3 2

0 ≤ I

REFOUT

≤ 8mA, sourcing, VDD = 5V,

REF

= 3.9V

0.3 2

Load Regulation

-150µA ≤ I

REFOUT

≤ 0, sinking 0.2

µV/µA

0.1Hz to 10Hz, V

REFOUT

= 3.9V

10Hz to 10kHz, V

REFOUT

= 3.9V

0.1Hz to 10Hz, V

REFOUT

= 1.2V 50

Output Noise Voltage

10Hz to 10kHz, V

REFOUT

= 1.2V

µV

P-P

VDD = 5V 30

Short-Circuit Current (Note 6)

= 1.8V 14

Capacitive Load Stability Range

(Note 7)

Thermal Hysteresis (Note 8)

ppm

REFOUT unloaded, VDD = 5V 5.4

Reference Power-Up Time (from Shutdown)

REFOUT unloaded, V

= 1.8V 4.4

Long-Term Stability

ppm/

1khrs

DAC OUTPUT (OUT)

Capacitive Driving Capability C

VDD = 5V, V

OUT

set to full scale, OUT

shorted to GND, source current

VDD = 5V, V

OUT

set to 0V, OUT shorted to

, sink current

VDD = 1.8V, V

OUT

set to full scale, OUT

shorted to GND, source current

Short-Circuit Current (Note 6)

= 1.8V, V

OUT

set to 0V, OUT shorted to

, sink current

SYMBOL

REFOUT

TEMPCO

MIN TYP MAX

1.197 1.214 1.231

1.913 1.940 1.967

2.391 2.425 2.459

3.828 3.885 3.941

150 600

450

0 to 10

200

1000

Page 4

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit, Voltage-Output DACs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +1.8V to +5.5V, OUT unloaded, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

= 5V 3

Coming out of shutdown (MAX5530)

3.8

DAC Power-Up Time

Coming out of standby (MAX5531)

= 1.8V

to 5.5V

0.4

Output Power-Up Glitch CL = 100pF 10 mV FB_ Input Current 10 pA

DIGITAL INPUTS (SCLK, DIN, CS)

4.5V ≤ VDD ≤ 5.5V 2.4

2.7V < VDD ≤ 3.6V 2.0Input High Voltage V

1.8V ≤ VDD ≤ 2.7V 0.7 x V

D D

4.5V ≤ VDD ≤ 5.5V 0.8

2.7V < VDD ≤ 3.6V 0.6Input Low Voltage V

1.8V ≤ VDD ≤ 2.7V

Input Leakage Current I

(Note 9)

µA

Input Capacitance C

10 pF

DYNAMIC PERFORMANCE

Voltage-Output Slew Rate SR Positive and negative (Note 10) 10

V/ms

Voltage-Output Settling Time

0.1 to 0.9 of full scale to within 0.5 LSB (Note 10)

µs

VDD = 5V 80

0.1Hz to 10Hz 55

VDD = 5V

Output Noise Voltage

10Hz to 10kHz

µV

P-P

POWER REQUIREMENTS

Supply Voltage Range V

1.8 5.5 V VDD = 5V 2.6 4 VDD = 3V 2.6 4MAX5530

3.6 5 VDD = 5V 5.3 7.0 VDD = 3V 4.8 7.0

Supply Current (Note 9) I

MAX5531

5.4 7.0

µA

VDD = 5V 3.3 4.5 VDD = 3V 2.8 4.0Standby Supply Current I

DDSD

(Note 9)

2.4 3.5

µA

Shutdown Supply Current I

DDPD

(Note 9)

µA

= 1.8V

VDD = 1.8V

VDD = 1.8V 476

VDD = 1.8V

0.3 x V

±0.05 ±0.5

660

620

0.05 0.25

Page 5

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit,

Voltage-Output DACs

_______________________________________________________________________________________ 5

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS (VDD = 4.5V TO 5.5V)

Serial Clock Frequency f

SCLK

MHz

DIN to SCLK Rise Setup Time t

15 ns

DIN to SCLK Rise Hold Time t

0ns

SCLK Pulse-Width High t

24 ns

SCLK Pulse-Width Low t

24 ns

CS Pulse-Width High t

CSW

100 ns

SCLK Rise to CS Rise Hold Time

CSH

0ns

CS Fall to SCLK Rise Setup Time

CSS

20 ns

SCLK Fall to CS Fall Setup t

CSO

0ns

CS Rise to SCK Rise Hold Time t

CS1

20 ns

TIMING CHARACTERISTICS

(VDD= +4.5V to +5.5V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

TIMING CHARACTERISTICS

(VDD= +1.8V to +5.5V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Note 1: Linearity is tested within codes 96 to 4080. Note 2: Offset is tested at code 96. Note 3: Gain is tested at code 4095. FB is connected to OUT. Note 4: Guaranteed by design. Not production tested. Note 5: V

must be a minimum of 1.8V.

Note 6: Outputs can be shorted to V

or GND indefinitely, provided that the package power dissipation is not exceeded.

Note 7: Optimal noise performance is at 2nF load capacitance. Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from T

MAX

to T

MIN

Note 9: All digital inputs at V

or GND.

Note 10: Load = 10kΩ in parallel with 100pF, V

= 5V, V

REF

= 4.096V (MAX5530) or V

REF

= 3.9V (MAX5531).

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS (VDD = 1.8V TO 5.5V)

Serial Clock Frequency f

SCLK

010

MHz

DIN to SCLK Rise Setup Time t

24 ns

DIN to SCLK Rise Hold Time t

0 ns

SCLK Pulse-Width High t

40 ns

SCLK Pulse-Width Low t

40 ns

CS Pulse-Width High t

CSW

SCLK Rise to CS Rise Hold Time

CSH

0 ns

CS Fall to SCLK Rise Setup Time

CSS

30 ns

SCLK Fall to CS Fall Setup t

CSO

0 ns

CS Rise to SCK Rise Hold Time t

CS1

30 ns

16.7

150

Page 6

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit, Voltage-Output DACs

6 _______________________________________________________________________________________

Typical Operating Characteristics

= 5.0V, V

REF

= 4.096V (MAX5530), V

REF

= 3.9V (MAX5531), TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

(MAX5531)

MAX5530 toc01

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

5.55.04.0 4.52.5 3.0 3.52.0

1.5 6.0

SUPPLY CURRENT vs. TEMPERATURE

(MAX5531)

MAX5530 toc02

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

603510-15

-40 85

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE (MAX5531)

MAX5530 toc03

TEMPERATURE (°C)

SHUTDOWN SUPPLY CURRENT (nA)

603510-15

100

1000

0.1

-40 85

STANDBY SUPPLY CURRENT

vs. TEMPERATURE (MAX5531)

MAX5530 toc04

TEMPERATURE (°C)

STANDBY SUPPLY CURRENT (µA)

603510-15

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-40 85

REF

= 3.9V

REF

= 2.4V

REF

= 1.9V

REF

= 1.2V

SUPPLY CURRENT

vs. CLOCK FREQUENCY

MAX5530 toc05

FREQUENCY (kHz)

SUPPLY CURRENT (µA)

1000010001001010.1

100

1000

0.01 100000

CS = LOGIC LOW CODE = 0

VDD = 5V

VDD = 1.8V

SUPPLY CURRENT

vs. LOGIC INPUT VOLTAGE

MAX5530 toc06

LOGIC INPUT VOLTAGE (V)

SUPPLY CURRENT (mA)

4.54.03.0 3.51.0 1.5 2.0 2.50.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 5.0

ALL DIGITAL INPUTS SHORTED TOGETHER

INL vs. INPUT CODE (V

= V

REF

= 1.8V)

MAX5530 toc07

DIGITAL INPUT CODE

INL (LSB)

4000350030002500200015001000500

-4

-3

-2

-1

-5 0 4500

INL vs. INPUT CODE

= V

REF

= 5V)

MAX5530 toc08

DIGITAL INPUT CODE

INL (LSB)

4000350030002500200015001000500

-4

-3

-2

-1

-5 04500

DNL vs. INPUT CODE

= V

REF

= 1.8V)

MAX5530 toc09

DIGITAL INPUT CODE

DNL (LSB)

4000350030002500200015001000500

-0.05

0.05

0.10

0.15

0.20

0.25

-0.10 04500

Page 7

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit,

Voltage-Output DACs

_______________________________________________________________________________________ 7

DNL vs. INPUT CODE

= V

REF

= 5V)

MAX5530 toc10

DIGITAL INPUT CODE

DNL (LSB)

4000350030002500200015001000500

-0.10

-0.05

0.05

0.10

0.15

0.20

-0.15

04500

OFFSET VOLTAGE

vs. TEMPERATURE

MAX5530 toc11

TEMPERATURE (°C)

OFFSET VOLTAGE (mV)

603510-15

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

-40 85

VDD = 5V V

REF

= 3.9V

GAIN-ERROR CHANGE

vs. TEMPERATURE

MAX5530 toc12

TEMPERATURE (°C)

GAIN-ERROR CHANGE (LSB)

603510-15

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

-40 85

VDD = 5V V

REF

= 3.9V

DIGITAL FEEDTHROUGH RESPONSE

MAX5530 toc13

20µs/div

CS 5V/div

SCLK 5V/div

DIN 5V/div

OUT 50mV/div

ZERO SCALE

DAC OUTPUT LOAD REGULATION

vs. OUTPUT CURRENT

MAX5530 toc14

DAC OUTPUT CURRENT (µA)

DAC OUTPUT VOLTAGE (V)

8006004002000-200-400-600-800

0.6042

0.6044

0.6046

0.6048

0.6050

0.6040

-1000 1000

VDD = 1.8V DAC CODE = MIDSCALE V

REF

= 1.2V

DAC OUTPUT VOLTAGE

vs. OUTPUT SOURCE CURRENT

MAX5530 toc16

OUTPUT SOURCE CURRENT (mA)

OUTPUT VOLTAGE (V)

1010.10.01

0.001 100

REF

= V

CODE = MIDSCALE

= 5V

= 3V

= 1.8V

DAC OUTPUT VOLTAGE

vs. OUTPUT SINK CURRENT

MAX5530 toc17

OUTPUT SINK CURRENT (mA)

DAC OUTPUT VOLTAGE (V)

1010.10.01

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0.001 100

REF

= V

CODE = MIDSCALE

VDD = 5V

VDD = 3V

VDD = 1.8V

OUTPUT LARGE-SIGNAL STEP RESPONSE

= 1.8V, V

REF

= 1.2V)

MAX5530 toc18

100µs/div

OUT

200mV/div

Typical Operating Characteristics (continued)

= 5.0V, V

REF

= 4.096V (MAX5530), V

REF

= 3.9V (MAX5531), TA = +25°C, unless otherwise noted.)

DAC OUTPUT LOAD REGULATION

vs. OUTPUT CURRENT

MAX5530 toc15

DAC OUTPUT CURRENT (mA)

DAC OUTPUT VOLTAGE (V)

86-8 -6 -4 0 2-2 4

1.9405

1.9410

1.9415

1.9420

1.9425

1.9430

1.9435

1.9440

1.9400

-10 10

VDD = 5.0V DAC CODE = MIDSCALE V

REF

= 3.9V

Page 8

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit, Voltage-Output DACs

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

= 5.0V, V

REF

= 4.096V (MAX5530), V

REF

= 3.9V (MAX5531), TA = +25°C, unless otherwise noted.)

OUTPUT LARGE-SIGNAL STEP RESPONSE

= 5V, V

REF

= 3.9V)

MAX5530 toc19

200µs/div

OUT

500mV/div

OUTPUT MINIMUM SERIES RESISTANCE

vs. LOAD CAPACITANCE

MAX5530 toc20

CAPACITANCE (µF)

MINIMUM SERIES RESISTANCE (Ω)

1010.10.010.001

100

200

300

400

500

600

0.0001 100

FOR NO OVERSHOOT

MAJOR CARRY OUTPUT VOLTAGE GLITCH

(CODE 7FFh TO 800h)

= 5V, V

REF

= 3.9V)

MAX5530 toc22

100µs/div

OUT

AC-COUPLED 5mV/div

REFERENCE OUTPUT VOLTAGE

vs. TEMPERATURE

MAX5530 toc23

TEMPERATURE (°C)

REFERENCE OUTPUT VOLTAGE (V)

6035-15 10

3.905

3.910

3.915

3.920

3.925

3.930

3.935

3.940

3.900

-40 85

VDD = 5V

REFERENCE OUTPUT VOLTAGE

vs. REFERENCE OUTPUT CURRENT

MAX5530 toc24

REFERENCE OUTPUT CURRENT (µA)

REFERENCE OUTPUT VOLTAGE (V)

7500550035001500

1.215

1.216

1.217

1.218

1.219

1.220

1.214

-500

VDD = 1.8V

REFERENCE OUTPUT VOLTAGE

vs. REFERENCE OUTPUT CURRENT

MAX5530 toc25

REFERENCE OUTPUT CURRENT (µA)

REFERENCE OUTPUT VOLTAGE (V)

14,50012,0009500700045002000

3.89

3.90

3.91

3.92

3.88

-500

VDD = 5V

REFERENCE OUTPUT VOLTAGE

vs. SUPPLY VOLTAGE

MAX5530 toc26

SUPPLY VOLTAGE (V)

REFERENCE OUTPUT VOLTAGE (V)

5.55.04.0 4.52.5 3.0 3.52.0

1.21732

1.21734

1.21736

1.21738

1.21740

1.21742

1.21744

1.21746

1.21748

1.21750

1.21730

1.5 6.0

NO LOAD

POWER-UP OUTPUT VOLTAGE GLITCH

MAX5530 toc21

20ms/div

OUT

10mV/div

2V/div

Page 9

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit,

Voltage-Output DACs

_______________________________________________________________________________________ 9

REFERENCE LINE-TRANSIENT RESPONSE

REF

= 3.9V)

MAX5530 toc28

100µs/div

5.5V

4.5V

REF

500mV/div

3.9V

REFERENCE LOAD TRANSIENT

= 1.8V)

MAX5530 toc29

200µs/div

REFOUT SOURCE CURRENT

0.5mA/div

REFOUT

500mV/div

REFERENCE LOAD TRANSIENT

= 5V)

MAX5530 toc30

200µs/div

REFOUT SOURCE CURRENT

0.5mA/div

REFOUT

500mV/div

3.9V

REFERENCE LOAD TRANSIENT

= 1.8V)

MAX5530 toc31

200µs/div

REFOUT SINK CURRENT 50µA/div

REFOUT

500mV/div

REFERENCE LOAD TRANSIENT

= 5V)

MAX5530 toc32

200µs/div

REFOUT SINK CURRENT 100µA/div

REFOUT

500mV/div

3.9V

Typical Operating Characteristics (continued)

= 5.0V, V

REF

= 4.096V (MAX5530), V

REF

= 3.9V (MAX5531), TA = +25°C, unless otherwise noted.)

REFERENCE LINE-TRANSIENT RESPONSE

REF

= 1.2V)

MAX5530 toc27

100µs/div

2.8V

1.8V

REF

500mV/div

Page 10

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit, Voltage-Output DACs

10 ______________________________________________________________________________________

REFERENCE PSRR

vs. FREQUENCY

MAX5530 toc33

FREQUENCY (kHz)

POWER-SUPPLY REJECTION RATIO (dB)

100100.1 1

0.01 1000

VDD = 1.8V

REFERENCE PSRR

vs. FREQUENCY

MAX5530 toc34

FREQUENCY (kHz)

POWER-SUPPLY REJECTION RATIO (dB)

100100.1 1

0.01 1000

VDD = 5V

REFERENCE OUTPUT NOISE

(0.1Hz TO 10Hz) (V

= 1.8V, V

REF

= 1.2V)

MAX5530 toc35

1s/div

100µV/div

REFERENCE OUTPUT NOISE

(0.1Hz TO 10Hz) (V

= 5V, V

REF

= 3.9V)

MAX5530 toc36

1s/div

100µV/div

Typical Operating Characteristics (continued)

= 5.0V, V

REF

= 4.096V (MAX5530), V

REF

= 3.9V (MAX5531), TA = +25°C, unless otherwise noted.)

Page 11

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit,

Voltage-Output DACs

______________________________________________________________________________________ 11

12-BIT DAC

DAC

OUT

REFIN

GND

MAX5530

INPUT

POWER-

DOWN

CONTROL

LOGIC

AND

SHIFT

SCLK

DIN

Pin Description

MAX5530 Functional Diagram

MAX5530

NAME FUNCTION

11CS Active-Low Digital-Input Chip Select 22SCLK Serial-Interface Clock 33DIN Serial-Interface Data Input 4—REFIN Reference Input

—4REFOUT Reference Output

5, 6, 7, 11

N.C. No Connection. Leave N.C. inputs unconnected (floating) or connected to GND.

88V

Power Input. Connect VDD to a 1.8V to 5.5V power supply. Bypass VDD to GND with a 0.1µF capacitor.

99GND Ground 10 10 OUT Analog Voltage Output 12 12 FB Feedback Input

EP EP

Exposed

Paddle

Exposed Paddle. Connect EP to GND.

MAX5531

5, 6, 7, 11

Page 12

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit, Voltage-Output DACs

12 ______________________________________________________________________________________

Detailed Description

The MAX5530/MAX5531 single, 12-bit, ultra-low-power, voltage-output DACs offer Rail-to-Rail buffered voltage outputs. The DACs operate from a 1.8V to 5.5V supply and require only 6µA (max) supply current. These devices feature a shutdown mode that reduces overall current, including the reference input current, to just

0.18µA. The MAX5531 includes an internal reference that saves additional board space and can source up to 8mA, making it functional as a system reference. The 16MHz, 3-wire serial interface is compatible with SPI, QSPI, and MICROWIRE protocols. When VDDis applied, all DAC outputs are driven to zero scale with virtually no output glitch. The MAX5530/MAX5531 output buffers are configured in force sense allowing users to externally set voltage gains on the output (an output amplifier inverting input is available). These devices come in a 4mm x 4mm thin QFN package.

Digital Interface

The MAX5530/MAX5531 use a 3-wire serial interface compatible with SPI, QSPI, and MICROWIRE protocols (Figures 1 and 2).

The MAX5530/MAX5531 include a single, 16-bit, input shift register. Data loads into the shift register through the serial interface. CS must remain low until all 16 bits are clocked in. Data loads MSB first, D11–D0. The 16 bits consist of 4 control bits (C3–C0) and 12 data bits (D11–D0) (see Table 1). The control bits C3–C0 control the MAX5530/MAX5531, as outlined in Table 2.

Each DAC channel includes two registers: an input register and a DAC register. The input register holds input data. The DAC register contains the data updated to the DAC output.

The double-buffered register configuration allows any of the following:

• Loading the input registers without updating the DAC registers

• Updating the DAC registers from the input registers

• Updating all the input and DAC registers simultaneously

12-BIT DAC

2-BIT

PROGRAMMABLE

REFERENCE

DAC

OUT

REF BUF

GND

MAX5531

REFOUT

INPUT

POWER-

DOWN

CONTROL

LOGIC

AND

SHIFT

SCLK

DIN

MAX5531 Functional Diagram

Page 13

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit,

Voltage-Output DACs

______________________________________________________________________________________ 13

CSW

CSS

CS0

CS1

CSH

SCLK

DIN

C1 D0

Figure 1. Timing Diagram

Figure 2. Register Loading Diagram

CONTROL DATA BITS

MSB

LSB

Table 1. Serial Write Data Format

C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1

16151413121110987654321SCLK

C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0DIN

CONTROL BITS DATA BITS

COMMAND EXECUTED

Page 14

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit, Voltage-Output DACs

14 ______________________________________________________________________________________

CONTROL BITS INPUT DATA

C3 C2 C1 C0 D11–D0

FUNCTION

0000

No operation; command is ignored.

000112-bit data

Load input register from shift register; DAC register unchanged;

DAC output unchanged. 0010 — Command reserved; do not use. 0011 — Command reserved; do not use.

0100 — Command reserved; do not use. 0101 — Command reserved; do not use. 0110 — Command reserved; do not use. 0111 — Command reserved; do not use.

100012-bit data

Load DAC register from input register; DAC output updated;

MAX5530 enters normal operation if in shutdown; MAX5531 enters

normal operation if in standby or shutdown.

100112-bit data

Load input register and DAC register from shift register; DAC output

updated; MAX5530 enters normal operation if in shutdown;

MAX5531 enters normal operation if in standby or shutdown. 1010 — Command reserved; do not use.

1011 — Command reserved; do not use.

1100

D11, D10,

XXXXXXXXXX

MAX5530 enters shutdown; MAX5531 enters standby*. For the

MAX5531, D11 and D10 configure the internal reference voltage

(Table 3).

1101

D11, D10,

XXXXXXXXXX

MAX5530/MAX5531 enter normal operation; DAC output reflects

existing contents of DAC register. For the MAX5531, D11 and D10

configure the internal reference voltage (Table 3).

1110

D11, D10,

XXXXXXXXXX

MAX5530/MAX5531 enter shutdown; DAC output set to high

impedance. For the MAX5531, D11 and D10 configure the internal

reference voltage (Table 3).

111112-bit data

Load input register and DAC register from shift register; DAC output

updated; MAX5530 enters normal operation if in shutdown;

MAX5531 enters normal operation if in standby or shutdown.

Table 2. Serial-Interface Programming Commands

X = Don’t care. *Standby mode can be entered from normal operation only. It is not possible to enter standby mode from shutdown.

XXXXXXXXXXXX

Page 15

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit,

Voltage-Output DACs

______________________________________________________________________________________ 15

Power Modes

The MAX5530/MAX5531 feature two power modes to conserve power during idle periods. In normal operation, the device is fully operational. In shutdown mode, the device is completely powered down, including the internal voltage reference in the MAX5531. The MAX5531 also offers a standby mode where all circuitry is powered down except the internal voltage reference. Standby mode keeps the reference powered up while the remaining circuitry is shut down, allowing it to be used as a system reference. Standby mode also helps reduce the wake-up delay by not requiring the reference to power up when returning to normal operation.

Shutdown Mode

The MAX5530/MAX5531 feature a software-programmable shutdown mode that reduces the typical supply current and the reference input current to 0.18µA (max). Writing an input control word with control bits C[3:0] = 1110 places the device in shutdown mode (Table 2). In shutdown, the MAX5530 reference input and DAC output buffers go high impedance. Placing the MAX5531 into shutdown turns off the internal reference, and the DAC output buffers go high impedance. The serial interface remains active for all devices.

Table 2 shows several commands that bring the MAX5530/MAX5531 back to normal operation. The power-up time from shutdown is required before the DAC outputs are valid.

Note: For the MAX5531, standby mode cannot be entered directly from shutdown mode. The device must be brought into normal operation before entering standby mode.

Standby Mode (MAX5531 Only)

The MAX5531 features a software-programmable standby mode that reduces the typical supply current to 6µA. Standby mode powers down all circuitry except the internal voltage reference. Place the device in standby mode by writing an input control word with control bits C[3:0] = 1100 (Table 2). The internal reference and serial interface remain active while the DAC output buffers go high impedance. If the MAX5531 is coming out of standby, the power-up time from standby is required before the DAC outputs are valid.

For the MAX5531, standby mode cannot be entered directly from shutdown mode. The device must be brought into normal operation before entering standby mode. To enter standby from shutdown, issue the command to return to normal operation, followed immediately by the command to go into standby.

Table 2 shows several commands that bring the MAX5531 back to normal operation. When transitioning from standby mode to normal operation, only the DAC power-up time is required before the DAC outputs are valid.

Reference Input

The MAX5530 accepts a reference with a voltage range extending from 0 to VDD. The output voltage (V

OUT

) is represented by a digitally programmable voltage source as:

OUT

= (V

REF

x N / 4096) x gain

where N is the numeric value of the DAC’s binary input code (0 to 4095), V

REF

is the reference voltage and gain is the externally set voltage gain for the MAX5530/ MAX5531.

In shutdown mode, the reference input enters a highimpedance state with an input impedance of 2.5GΩ (typ).

Reference Output

The MAX5531 internal voltage reference is software configurable to one of four voltages. Upon power-up, the default reference voltage is 1.214V. Configure the reference voltage using the D11 and D10 data bits (Table 3) when the control bits are as follows C[3:0] = 1100, 1101, or 1110 (Table 2). VDDmust be kept at a minimum of 200mV above V

REF

for proper operation.

D11 D10 REFERENCE VOLTAGE (V)

00 1.214 01 1.940 10 2.425 11 3.885

Table 3. Reference Output Voltage Programming

Page 16

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit, Voltage-Output DACs

16 ______________________________________________________________________________________

Applications Information

1-Cell and 2-Cell Circuit

See Figure 3 for an illustration of how to power the MAX5530/MAX5531 with either one lithium-ion battery or two alkaline batteries. The low current consumption of the devices makes the MAX5530/MAX5531 ideal for battery-powered applications.

Programmable Current Source

See the circuit in Figure 4 for an illustration of how to configure the MAX5530 as a programmable current source for driving an LED. The MAX5530 drives a standard NPN transistor to program the current source. The current source (I

LED

) is defined in the equation in

Figure 4.

Voltage Biasing a Current-Output

Transducer

See the circuit in Figure 5 for an illustration of how to configure the MAX5530 to bias a current output transducer. In Figure 5, the output voltage of the MAX5530 is a function of the voltage drop across the transducer added to the voltage drop across the feedback resistor R.

Self-Biased Two-Electrode

Potentiostat Application

See the circuit in Figure 6 for an illustration of how to use the MAX5531 to bias a two-electrode potentiostat on the input of an ADC.

Unipolar Output

Figure 7 shows the MAX5530 in a unipolar output configuration with unity gain. Table 4 lists the unipolar output codes.

Bipolar Output

The MAX5530 output can be configured for bipolar operation, as shown in Figure 8. The output voltage is given by the following equation:

OUT

= V

REF

x [(NA- 2048) / 2048]

where NArepresents the numeric value of the DAC’s binary input code. Table 5 shows digital codes (offset binary) and the corresponding output voltage for the circuit in Figure 4.

Configurable Output Gain

The MAX5530/MAX5531 have a force-sense output, which provides a connection directly to the inverting terminal of the output op amp, yielding the most flexibility. The advantage of the force-sense output is that specific gains can be set externally for a given application. The gain error for the MAX5530/MAX5531 is specified in a unity-gain configuration (op-amp output and inverting terminals connected), and additional gain error results from external resistor tolerances. Another advantage of the force-sense DAC is that it allows many useful circuits to be created with only a few simple external components.

An example of a custom fixed gain using the force-sense output of the MAX5530/MAX5531 is shown in Figure 9. In this example, R1 and R2 set the gain for V

OUT

=[(V

REFIN

x NA) / 4096] x [1 + (R2 / R1)]

where NArepresents the numeric value of the DAC input code.

REFIN

MAX5530

MAX6006

(1µA, 1.25V

SHUNT

REFERENCE)

GND

+1.25V

0.01µF

536kΩ

DAC

VOUT

DAC

IS THE NUMERIC VALUE

OF THE DAC INPUT CODE.

OUT

(0.30mV / LSB)

1.8V ≤ V

ALKALINE

≤ 3.3V

2.2V ≤ V

LITHIUM

≤ 3.3V

OUT

REFIN

× N

DAC

4096

0.1µF

Figure 3. Portable Application Using Two Alkaline Cells or One Lithium Coin Cell

Page 17

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit,

Voltage-Output DACs

______________________________________________________________________________________ 17

2N3904

DAC

IS THE NUMERIC VALUE OF THE DAC INPUT CODE.

LED

REFIN

LED

MAX5530

V+

DAC

VOUT

LED

REFIN

× N

DAC

4096 × R

Figure 4. Programmable Current Source Driving an LED

DAC

BAND

GAP

TO ADC

OUT

REFOUT

MAX5531

TO ADC

SENSOR

REF

Figure 6. Self-Biased Two-Electrode Potentiostat Application

DAC

IS THE NUMERIC VALUE

OF THE DAC INPUT CODE.

REFIN

MAX5530

VOUT

OUT

= V

BIAS

+ (IT × R)

OUT

BIAS

TRANSDUCER

BIAS

REFIN

× N

DAC

4096

DAC

Figure 5. Transimpedance Configuration for a Voltage-Biased Current-Output Transducer

NA IS THE DAC INPUT CODE (0 TO 4095 DECIMAL).

REFIN

MAX5530

OUT

REFIN

× N

4096

DAC

Figure 7. Unipolar Output Circuit

DAC CONTENTS

MSB

ANALOG OUTPUT

REF

(4095/4096)

REF

(2049/4096)

REF

(2048/4096) = +V

REF

/ 2

REF

(2047/4096)

REF

(1/4096) 0V

Table 4. Unipolar Code Table (Gain = +1)

DAC CONTENTS

MSB

ANALOG OUTPUT

REF

(2047/2048)

REF

(1/2048) 0V

-V

REF

(1/2048)

-V

REF

(2047/2048)

-V

REF

(2048/2048) = -V

REF

Table 5. Bipolar Code Table (Gain = +1)

LSB

1111 1111 1100 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0001 0001 0000 0000 0000

LSB

1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000

Page 18

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit, Voltage-Output DACs

18 ______________________________________________________________________________________

Power Supply and Bypassing

Considerations

Bypass the power supply with a 0.1µF capacitor to GND. Minimize lengths to reduce lead inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. For the thin QFN package, connect the exposed paddle to ground.

Layout Considerations

Digital and AC transient signals coupling to GND can create noise at the output. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use printed circuit (PC) boards. Good PC board ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines.

Figure 8. Bipolar Output Circuit

Figure 9. Separate Force-Sense Outputs Create Unity and Greater-than-Unity DAC Gains Using the Same Reference

REFIN

MAX5530

OUT

V+

10kΩ 10kΩ

V-

DAC

Figure 10. Software-Configurable Output Gain

DAC

IS THE NUMERIC VALUE OF THE DAC INPUT CODE.

POT

IS THE NUMERIC VALUE OF THE POT INPUT CODE.

REFIN

MAX5530

MAX5401

SOT-POT

100kΩ

VOUT

5PPM/°C

RATIOMETRIC

TEMPCO

1.8V ≤ V

≤ 5.5V

OUT

REFIN

× N

DAC

4096

(

1 +

255 - N

POT

)

255

SCLK

DIN

CS2

CS1

DAC

Chip Information

TRANSISTOR COUNT: 10,688 PROCESS: BiCMOS

MAX5530

REFIN

DAC

OUT

Page 19

MAX5530/MAX5531

Ultra-Low-Power, 12-Bit,

Voltage-Output DACs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages

24L QFN THIN.EPS

PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm

21-0139

PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm

21-0139