The MAX5481–MAX5484 10-bit (1024-tap) nonvolatile,
linear-taper, programmable voltage-dividers and variable resistors perform the function of a mechanical
potentiometer, but replace the mechanics with a pinconfigurable 3-wire serial SPI™-compatible interface or
up/down digital interface. The MAX5481/MAX5482 are
3-terminal voltage-dividers and the MAX5483/MAX5484
are 2-terminal variable resistors.
The MAX5481–MAX5484 feature an internal, nonvolatile, electrically erasable programmable read-only
memory (EEPROM) that stores the wiper position for initialization during power-up. The 3-wire SPI-compatible
serial interface allows communication at data rates up
to 7MHz. A pin-selectable up/down digital interface is
also available.
The MAX5481–MAX5484 are ideal for applications
requiring digitally controlled potentiometers. Two end-toend resistance values are available (10kΩ and 50kΩ) in a
voltage-divider or a variable-resistor configuration (see
the Selector Guide). The nominal resistor temperature
coefficient is 35ppm/°C end-to-end, and only 5ppm/°C
ratiometric, making these devices ideal for applications
requiring low-temperature-coefficient voltage-dividers,
such as low-drift, programmable gain-amplifiers.
The MAX5481–MAX5484 operate with either a +2.7V to
+5.25V single power supply or ±2.5V dual power supplies. These devices consume 400µA (max) of supply
current when writing data to the nonvolatile memory
and 1.0µA (max) of standby supply current. The
MAX5481–MAX5484 are available in a space-saving
(3mm x 3mm), 16-pin TQFN, or a 14-pin TSSOP package and are specified over the extended (-40°C to
+85°C) temperature range.
Applications
Features
♦ 1024 Tap Positions
♦ Power-On Recall of Wiper Position from
Nonvolatile Memory
♦ 16-Pin (3mm x 3mm x 0.8mm) TQFN or 14-Pin
TSSOP Package
♦ 35ppm/°C End-to-End Resistance Temperature
Coefficient
♦ 5ppm/°C Ratiometric Temperature Coefficient
♦ 10kΩ and 50kΩ End-to-End Resistor Values
♦ Pin-Selectable SPI-Compatible Serial Interface or
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND...........................................................-0.3V to +6.0V
V
SS
to GND............................................................-6.0V to +0.3V
V
DD
to VSS.............................................................-0.3V to +6.0V
H, L, W to V
SS
..................................(VSS- 0.3V) to (VDD+ 0.3V)
CS, SCLK(INC), DIN(U/D), SPI/UD to GND..-0.3V to (V
Note 1: 100% production tested at TA= +25°C and TA= +85°C. Guaranteed by design to TA= -40°C.
Note 2: The DNL and INL are measured with the device configured as a voltage-divider with H = V
DD
and L = VSS. The wiper termi-
nal (W) is unloaded and measured with a high-input-impedance voltmeter.
Note 3: The DNL_R and INL_R are measured with D.N.C. unconnected and L = V
SS
= 0. For VDD= 5V, the wiper terminal is driven
with a source current of I
W
= 80µA for the 50kΩ device and 400µA for the 10kΩ device. For VDD= 3V, the wiper terminal is
driven with a source current of 40µA for the 50kΩ device and 200µA for the 10kΩ device.
Note 4: The wiper resistance is measured using the source currents given in Note 3.
Note 5: The device draws higher supply current when the digital inputs are driven with voltages between (V
DD
- 0.5V) and (GND +
0.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics.
Note 6: Wiper settling test condition uses the voltage-divider configuration with a 10pF load on W. Transition code from 00000 00000
to 01111 01111 and measure the time from CS going high to the wiper voltage settling to within 0.5% of its final value.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ANALOG SECTION
Wiper Settling Time (Note 6)t
SPI-COMPATIBLE SERIAL INTERFACE (Figure 3)
SCLK Frequencyf
SCLK Clock Periodt
SCLK Pulse-Width Hight
SCLK Pulse-Width Lowt
CS Fall to SCLK Rise Setupt
SCLK Rise to CS Rise Holdt
DIN to SCLK Setupt
DIN Hold after SCLKt
SCLK Rise to CS Fall Delayt
CS Rise to SCLK Rise Holdt
CS Pulse-Width Hight
Write NV Register Busy Timet
UP/DOWN DIGITAL INTERFACE (Figure 8)
CS to INC Setupt
INC High to U/D ChangetU/D to INC Setupt
INC Low Periodt
INC High Periodt
INC Inactive to CS Inactivet
CS Deselect Time (Store)t
INC Cycle Timet
INC Active to CS Inactivet
4–7, 157, 8, 9, 13N.C.No Connection. Not internally connected.
8, 1614V
96SPI/UD
105DIN(U/D)
114SCLK(INC)
123CSActive-Low Digital Input Chip Select
132GNDGround
141V
EP—EPExposed Pad. Externally connect EP to VSS or leave unconnected.
NAMEFUNCTION
Negative Power-Supply Input. For single-supply operation, connect VSS to GND. For dual-
SS
DD
supply operation, -2.5V ≤ V
with a 0.1µF ceramic capacitor as close to the device as possible.
Interface-Mode Select. Select serial SPI interface when SPI/UD = 1. Select serial up/down
interface when SPI/UD = 0.
Serial SPI Interface Data Input (SPI/UD = 1)
Up/Down Control Input (SPI/UD = 0). With DIN(U/D) low, a high-to-low SCLK(INC) transition
decrements the wiper position. With DIN(U/D) high, a high-to-low SCLK(INC) transition
increments the wiper position.
Serial SPI Interface Clock Input (SPI/UD = 1)
Wiper-Increment Control Input (SPI/UD = 0). With CS low, the wiper position moves in the
direction determined by the state of DIN(U/D) on a high-to-low transition.
Positive Power-Supply Input (+2.7V ≤ VDD ≤ +5.25V). Bypass VDD to GND with a 0.1µF
ceramic capacitor as close to the device as possible.
≤ -0.2V as long as (V
SS
DD
- VSS) ≤ +5.25V. Bypass V
SS
to GND
MAX5481–MAX5484
10-Bit, Nonvolatile, Linear-Taper Digital
Potentiometers
4–7, 157, 8, 9, 13N.C.No Connection. Not internally connected.
112D.N.C.Do Not Connect. Leave unconnected for proper operation.
211WWiper Terminal
310LLow Terminal
8, 1614V
NAMEFUNCTION
Negative Power-Supply Input. For single-supply operation, connect VSS to GND. For dual-
SS
supply operation, -2.5V ≤ V
with a 0.1µF ceramic capacitor as close to the device as possible.
≤ -0.2V as long as (V
SS
- VSS) ≤ 5.25V. Bypass V
DD
SS
to GND
96SPI/UD
105DIN(U/D)
114SCLK(INC)
123CSActive-Low Digital Input Chip Select
132GNDGround
141V
EP—EPExposed Pad. Externally connect EP to VSS or leave unconnected.
DD
Interface-Mode Select. Select serial SPI interface when SPI/UD = 1. Select serial up/down
interface when SPI/UD = 0.
Serial SPI Interface Data Input (SPI/UD = 1)
Up/Down Control Input (SPI/UD = 0). With DIN(U/D) low, a high-to-low SCLK(INC) transition
decrements the wiper position. With DIN(U/D) high, a high-to-low SCLK(INC) transition
increments the wiper position.
Serial SPI Interface Clock Input (SPI/UD = 1)
Wiper Increment Control Input (SPI/UD = 0). With CS low, the wiper position moves in the
direction determined by the state of DIN(U/D) on a high-to-low transition.
Positive Power-Supply Input (+2.7V ≤ VDD ≤ +5.25V). Bypass VDD to GND with a 0.1µF
ceramic capacitor as close to the device as possible.
The MAX5481/MAX5482 linear programmable voltagedividers and the MAX5483/MAX5484 variable resistors
feature 1024 tap points (10-bit resolution) (see the
Functional Diagrams). These devices consist of multiple strings of equal resistor segments with a wiper contact that moves among the 1024 points through a
pin-selectable 3-wire SPI-compatible serial interface or
up/down interface. The MAX5481/MAX5483 provide a
total end-to-end resistance of 10kΩ, and the
MAX5482/MAX5484 have an end-to-end resistance of
50kΩ. The MAX5481/MAX5482 allow access to the
high, low, and wiper terminals for a standard voltagedivider configuration.
MAX5481/MAX5482 Programmable
Voltage-Dividers
The MAX5481/MAX5482 programmable voltagedividers provide a weighted average of the voltage
between the H and L inputs at the W output. Both
devices feature 10-bit resolution and provide up to
1024 tap points between the H and L voltages. Ideally,
the V
L
voltage occurs at the wiper terminal (W) when all
data bits are zero and the VHvoltage occurs at the
wiper terminal when all data bits are one. The step size
(1 LSB) voltage is equal to the voltage applied across
terminals H and L divided by 210. Calculate the wiper
voltage VWas follows:
where D is the decimal equivalent of the 10 data bits written (0 to 1023), VHLis the voltage difference between the
H and L terminals:
The MAX5481 includes a total end-to-end resistance
value of 10kΩ while the MAX5482 features an end-toend resistance value of 50kΩ. These devices are notintended to be used as a variable resistor. Wiper current creates a nonlinear voltage drop in series with the
wiper. To ensure temperature drift remains within specifications, do not pull current through the voltage-divider
wiper. Connect the wiper to a high-impedance node.
Figures 1 and 2 show the behavior of the MAX5481’s
resistance from W to H and from W to L. This does not
apply to the variable-resistor devices
MAX5483/MAX5484 Variable Resistors
The MAX5483/MAX5484 provide a programmable
resistance between W and L. The MAX5483 features a
total end-to-end resistance value of 10kΩ, while the
MAX5484 provides an end-to-end resistance value of
50kΩ. The programmable resolution of this resistance is
equal to the nominal end-to-end resistance divided by
1024 (10-bit resolution). For example, each nominal
segment resistance is 9.8Ω and 48.8Ω for the MAX5483
and the MAX5484, respectively.
The 10-bit data in the 10-bit latch register selects a
wiper position from the 1024 possible positions, resulting in 1024 values for the resistance from W to L.
Calculate the resistance from W to L (RWL) by using the
following formula:
where D is decimal equivalent of the 10 data bits written, R
W-L
is the nominal end-to-end resistance, and R
Z
is the zero-scale error. Table 1 shows the values of R
WL
at selected codes for the MAX5483/MAX5484.
Digital Interface
Configure the MAX5481–MAX5484 by a pin-selectable,
3-wire, SPI-compatible serial data interface or an
up/down interface. Drive SPI/UD high to select the 3wire SPI-compatible interface. Pull SPI/UD low to select
the up/down interface.
Table 1. R
WL
at Selected Codes
Figure 1. Resistance from W to H vs. Code (10kΩ Voltage-Divider)
Figure 2. Resistance from W to L vs. Code (10kΩ Voltage-Divider)
18
16
14
12
10
(kΩ)
W-H
8
R
6
4
2
0
01024
CODE (DECIMAL)
50kΩ DEVICE SCALES BY A FACTOR OF FIVE
896768512 640256 384128
V
⎡
⎤
VFSE
=
FSE
VZSE
=
ZSE
⎢
1024
⎣
V
⎡
⎢
1024
⎣
HL
HL
⎥
⎦
⎤
⎥
⎦
and
,
18
16
14
12
10
(kΩ)
W-L
8
R
6
4
2
0
01024
50kΩ DEVICE SCALES BY A FACTOR OF FIVE
CODE
(DECIMAL)
070110
180160
512507025,110
102310,07050,110
(10kΩ DEVICE)
CODE (DECIMAL)
MAX5483
(Ω)R
R
WL
896768512 640256 384128
MAX5484
(50kΩ DEVICE)
(Ω)
WL
RD
WLW LZ
D
1023
RR
−
()=×+
MAX5481–MAX5484
10-Bit, Nonvolatile, Linear-Taper Digital
Potentiometers
Drive SPI/UD high to enable the 3-wire SPI-compatible
serial interface (see Figure 3). This write-only interface
contains three inputs: chip select (CS), data in
(DIN(U/D)), and data clock (SCLK(INC)). Drive CS low
to load the data at DIN(U/D) synchronously into the shift
register on each SCLK(INC) rising edge.
The WRITE command (C1, C0 = 00) requires 24 clock
cycles to transfer the command and data (Figure 4a).
The COPY commands (C1, C0 = 10 or 11) use either
eight clock cycles to transfer the command bits (Figure
4b) or 24 clock cycles with the last 16 data bits disregarded by the device.
After loading the data into the shift register, drive CS
high to latch the data into the appropriate control register. Keep CS low during the entire serial data stream to
avoid corruption of the data. Table 2 shows the command decoding.
Write Wiper Register
Data written to this register (C1, C0 = 00) controls the
wiper position. The 10 data bits (D9–D0) indicate the
position of the wiper. For example, if DIN(U/D) = 00 0000
0000, the wiper moves to the position closest to L. If
DIN(U/D) = 11 1111 1111, the wiper moves closest to H.
This command writes data to the volatile random
access memory (RAM), leaving the NV register
unchanged. When the device powers up, the data
stored in the NV register transfers to the wiper register,
moving the wiper to the stored position. Figure 5 shows
how to write data to the wiper register.
The copy wiper register to NV register command (C1,
C0 = 10) stores the current position of the wiper to the
NV register for use at power-up. Figure 6 shows how to
copy data from wiper register to NV register. The operation takes up to 12ms (max) after CS goes high to
complete and no other operation should be performed
until completion.
Copy NV Register to Wiper Register
The copy NV register to wiper register (C1, C0 = 11)
restores the wiper position to the current value stored in
the NV register. Figure 7 shows how to copy data from
the NV register to the wiper register.
Digital Up/Down Interface
Figure 8 illustrates an up/down serial-interface timing
diagram. In digital up/down interface mode (SPI/UD =
0), the logic inputs CS, DIN(U/D), and SCLK(INC) control the wiper position and store it in nonvolatile memory
(see Table 3). The chip-select (CS) input enables the
serial interface when low and disables the interface
when high. The position of the wiper is stored in the
nonvolatile register when CS transitions from low to
high while SCLK(INC) is high.
When the serial interface is active (CS low), a high-tolow (falling edge) transition on SCLK(INC) increments
or decrements the internal 10-bit counter depending on
the state of DIN(U/D). If DIN(U/D) is high, the wiper
increments. If DIN(U/D) is low, the wiper decrements.
The device stores the value of the wiper position in the
nonvolatile memory when CS transitions from low to high
while SCLK(INC) is high. The host system can disable
the serial interface and deselect the device without storing the latest wiper position in the nonvolatile memory by
keeping SCLK(INC) low while taking CS high.
Upon power-up, the MAX5481–MAX5484 load the
value of nonvolatile memory into the wiper register, and
set the wiper position to the value last stored.
Figure 6. Copy Wiper Register to NV Register Operation
The MAX5481–MAX5484 feature a low-power standby
mode. When the device is not being programmed, it
enters into standby mode and supply current drops to
0.5µA (typ).
Nonvolatile Memory
The internal EEPROM consists of a nonvolatile register
that retains the last value stored prior to power-down.
The nonvolatile register is programmed to midscale at
the factory. The nonvolatile memory is guaranteed for
50 years of wiper data retention and up to 200,000
wiper write cycles.
Power-Up
Upon power-up, the MAX5481–MAX5484 load the data
stored in the nonvolatile wiper register into the volatile
wiper register, updating the wiper position with the data
stored in the nonvolatile wiper register.
Applications Information
The MAX5481–MAX5484 are ideal for circuits requiring
digitally controlled adjustable resistance, such as LCD
contrast control (where voltage biasing adjusts the display contrast), or programmable filters with adjustable
gain and/or cutoff frequency.
Positive LCD Bias Control
Figures 9 and 10 show an application where a voltagedivider or a variable resistor is used to make an
adjustable, positive LCD-bias voltage. The op amp provides buffering and gain to the voltage-divider network
made by the programmable voltage-divider (Figure 9) or
to a fixed resistor and a variable resistor (see Figure 10).
Programmable Gain and Offset Adjustment
Figure 11 shows an application where a voltage-divider
and a variable resistor are used to make a programmable gain and offset adjustment.
Figure 12 shows the configuration for a 1st-order programmable filter using two variable resistors. Adjust R2
for the gain and adjust R3 for the cutoff frequency. Use
the following equations to estimate the gain (G) and the
3dB cutoff frequency (fC):
Figure 10. Positive LCD Bias Control Using a Variable Resistor
Figure 12. Programmable Filter
Figure 11. Programmable Gain/Offset Adjustment
Figure 9. Positive LCD Bias Control Using a Voltage-Divider
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
D2
b
0.10 M
D
D/2
D2/2
C A B
C
L
C
L
0.10 C0.08 C
PKG
12L 3x3
REF. MIN.
NOM. MAX.NOM.
0.70
0.75
A
b
0.20
0.25
D
2.90
3.00
3.00
2.90
E
e
0.50 BSC.
0.55
0.45
L
N
12
ND
NE
3
0.0230.05
A1
0
A2
0.20 REF
-
k
0.25
MIN.MAX.
0.80
0.70
0.30
0.20
3.10
2.90
2.90
3.10
0.30
0.65
-
0.25
A
A2
A1
16L 3x3
0.75
0.25
3.00
3.00
0.50 BSC.
0.40
16
0.02
0
0.20 REF
E/2
E
0.80
0.30
3.10
3.10
0.50
4
4
0.05
-
-
PKG.
CODES
T1233-1
T1233-3
T1633-10.95
T1633-2
T1633F-3 0.65
T1633-4
(NE - 1) X e
C
L
L
e
EXPOSED PAD VARIATIONS
D2
MIN.
NOM.
1.10
0.95
1.10
0.95
1.10
0.95
1.10
0.80
0.95
1.10
MAX.
1.25
1.25
1.25
1.25
0.95
1.25
e
PACKAGE OUTLINE
12, 16L, THIN QFN, 3x3x0.8mm
E2
NOM.
MIN.
MAX.
1.10
0.95
0.95 1.10
1.10
0.95
1.10
0.95
0.80
0.65
1.10
0.95
1.25
1.25
1.25
0.95
1.25
E2/2
k
(ND - 1) X e
C
L
e
21-0136
PIN ID
JEDEC
0.35 x 45∞
WEED-1
0.35 x 45∞1.25WEED-1
0.35 x 45∞ WEED-2
0.35 x 45∞
WEED-2
0.225 x 45∞
WEED-2
0.35 x 45∞
WEED-2
E2
L
L
DOWN
BONDS
ALLOWED
NO
YES
NO
YES
N/A
NO
12x16L QFN THIN.EPS
1
E
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PACKAGE OUTLINE
12, 16L, THIN QFN, 3x3x0.8mm
21-0136
2
E
2
MAX5481–MAX5484
10-Bit, Nonvolatile, Linear-Taper Digital
Potentiometers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
TSSOP4.40mm.EPS
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