Rainbow Electronics MAX539 User Manual

19-0172; Rev 6; 2/97

+5V, Low-Power, Voltage-Output,

Serial 12-Bit DACs

_______________General Description

The MAX531/MAX538/MAX539 are low-power, voltage­output, 12-bit digital-to-analog converters (DACs) speci­fied for single +5V power-supply operation. The MAX531
can also be operated with ±5V supplies. The
MAX538/MAX539 draw only 140µA, and the MAX531
(with internal reference) draws only 260µA. The
MAX538/MAX539 come in 8-pin DIP and SO packages,
while the MAX531 comes in 14-pin DIP and SO pack­ages. All parts have been trimmed for offset voltage,
gain, and linearity, so no further adjustment is necessary.

The MAX538’s buffer is fixed at a gain of +1 and the
MAX539’s buffer at a gain of +2. The MAX531’s internal
op amp may be configured for a gain of +1 or +2, as
well as for unipolar or bipolar output voltages. The
MAX531 can also be used as a four-quadrant multiplier
without external resistors or op amps.

For parallel data inputs, see the MAX530 data sheet.

_______________________Applications

Battery-Powered Test Instruments
Digital Offset and Gain Adjustment
Battery-Operated/Remote Industrial Controls
Machine and Motion Control Devices
Cellular Telephones

________________Functional Diagram

(MAX531 ONLY)

REFOUT

REFIN

(MAX531 ONLY)

BIPOFF

___________________________Features

♦ Operate from Single +5V Supply
♦ Buffered Voltage Output
♦ Internal 2.048V Reference (MAX531)
♦ 140µA Supply Current (MAX538/MAX539)
♦ INL = ±1/2LSB (max)
♦ Guaranteed Monotonic over Temperature
♦ Flexible Output Ranges:

0V to VDD(MAX531/MAX539)
VSSto VDD(MAX531)
0V to 2.6V (MAX531/MAX538)

♦ 8-Pin SO/DIP (MAX538/MAX539)
♦ Power-On Reset
♦ Serial Data Output for Daisy-Chaining

______________Ordering Information

PART TEMP. RANGE PIN-PACKAGE

MAX531ACPD

MAX531BCPD 0°C to +70°C 14 Plastic DIP
MAX531ACSD 0°C to +70°C 14 SO
MAX531BCSD 0°C to +70°C 14 SO
MAX531BC/D 0°C to +70°C Dice* ±1

Ordering Information continued at end of data sheet.

*Dice are specified at T

0°C to +70°C 14 Plastic DIP

= +25°C only.

A

ERROR

(LSB)

±1/2
±1
±1/2
±1

_________________Pin Configurations

MAX531/MAX538/MAX539

AGND

CLR

(MAX531

ONLY)

SCLK

DIN

CS

DAC REGISTER

SHIFT REGISTER

(LSB)

MAX531
MAX538
MAX539

DAC

(12 BITS)

(12 BITS)

(MSB)

2.048V

REFERENCE

(MAX531 ONLY)

POWER-UP

RESET

CONTROL

LOGIC

________________________________________________________________

BITS

RFB
(MAX531
ONLY)

VOUT

V

DD

DGND
(MAX531
ONLY)



V

SS

(MAX531
ONLY)

4

DOUT

TOP VIEW

DIN

1

SCLK

2

CS

DOUT

Pin Configurations continued at end of data sheet.

MAX538

3

MAX539

4

DIP/SO

Maxim Integrated Products

V

8

DD

VOUT

7

REFIN

6
5

AGND

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone]

+5V, Low-Power, Voltage-Output
Serial 12-Bit DACs

ABSOLUTE MAXIMUM RATINGS

VDDto DGND and VDDto AGND................................-0.3V, +6V

to DGND and VSSto AGND .................................-6V, +0.3V

V

SS

to VSS.................................................................-0.3V, +12V

V

DD

AGND to DGND........................................................-0.3V, +0.3V

Digital Input Voltage to DGND ......................-0.3V, (V

REFIN..................................................(V

REFOUT to AGND.........................................-0.3V, (V

RFB .....................................................(V

BIPOFF................................................(V

(Note 1) ................................................................VSS, V

V

OUT

Continuous Current, Any Pin................................-20mA, +20mA

Note 1: The output may be shorted to VDD, V

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

- 0.3V), (V

SS

- 0.3V), (V

SS

- 0.3V), (V

SS

SS

+ 0.3V)

DD

+ 0.3V)

DD

+ 0.3V)

DD

+ 0.3V)

DD

+ 0.3V)

DD

DD

or AGND if the package power dissipation limit is not exceeded.

,

ELECTRICAL CHARACTERISTICS—Single +5V Supply

(VDD= +5V ±10%, VSS= 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX531), C
(MAX531), R

= 10kΩ, CL= 100pF, TA= T

L

MIN

to T

, unless otherwise noted.)

MAX

Continuous Power Dissipation (T

8-Pin Plastic DIP (derate 9.09mW/°C above +70°C)....727mW

8-Pin SO (derate 5.88mW/°C above +70°C)................471mW

14-Pin Plastic DIP (derate 10.00mW/°C above +70°C)...800mW

14-Pin SO (derate 8.33mW/°C above +70°C)..............667mW

Operating Temperature Ranges

MAX53_ _C_ _ .....................................................0°C to +70°C

MAX53_ _E_ _ ..................................................-40°C to +85°C

Storage Temperature Range.............................-65°C to +165°C

Lead Temperature (soldering, 10sec).............................+300°C

= +70°C)

A

REFOUT

= 33µF

PARAMETER SYMBOL MIN TYP MAX UNITS

STATIC PERFORMANCE

Resolution N 12 Bits

MAX531/MAX538/MAX539

Relative Accuracy (Note 2) INL LSB

Differential Nonlinearity DNL ±1 LSB
Unipolar Offset Error V
Unipolar Offset Tempco TCV
Gain Error (Note 2) GE ±1 LSB
Gain-Error Tempco 1 ppm/°C

Power-Supply Rejection Ratio
(Note 3)

VOLTAGE OUTPUT (VOUT)

Output Voltage Range
Output Load Regulation 1 LSB

Short-Circuit Current I

REFERENCE INPUT (REFIN)

Voltage Range 0V
Input Resistance 40 kΩ
Input Capacitance 10 50 pF
AC Feedthrough -80 dB

PSRR 0.4 1 LSB/V

SC

MAX53_AC/E
MAX53_BC/E
Guaranteed monotonic

MAX53_ _C/E

OS

OS

MAX53_ _C/E

4.5V ≤ VDD≤ 5.5V

MAX531 (G = +1), MAX538
MAX531 (G = +2), MAX539
VOUT = 2V, RL= 2kΩ

Code dependent, minimum at code 555 hex
Code dependent (Note 4)
REFIN = 1kHz, 2Vp-p

CONDITIONS

±0.5

±1

08LSB

3 ppm/°C

0V
0V

12 mA

DD

DD

- 0.4

DD

- 2

- 2 V

V

2 _______________________________________________________________________________________

+5V, Low-Power, Voltage-Output,

Serial 12-Bit DACs

ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)

(VDD= +5V ±10%, VSS= 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX531), C
(MAX531), R

PARAMETER

= 10kΩ, CL= 100pF, TA= T

L

SYMBOL MIN TYP MAX

MIN

to T

, unless otherwise noted.)

MAX

CONDITIONS

REFERENCE OUTPUT (REFOUT—MAX531 only)

TA= +25°C

Reference Output Voltage V

VDD= 5.0V

MAX531BC

MAX531BE
Temperature Coefficient TC
Resistance R

Power-Supply Rejection Ratio

REFOUT

REFOUT

PSRR 300 µV/V
Noise Voltage e
Minimum Required External

Capacitor

C

n

MIN

MAX531AC/AE/AM/BM
MAX531BC/BE
(Note 5)

4.5V ≤ VDD≤ 5.5V

0.1Hz to 10kHz

2.024 2.048 2.072

2.017 2.079

2.013 2.083
30 50
30

0.5 2

400

3.3 µF

DIGITAL INPUTS (DIN, SCLK, CS, CLR)

Input High
Input Low
Input Current
Input Capacitance C

V

IH

V

IL

I

IN

IN

VIN= 0V or V

DD

2.4

8

DIGITAL OUTPUT (DOUT)

Output High
Output Low V

V

OH
OL

I

SOURCE

I

SINK

= 2mA

= 2mA

V

- 1

DD

DYNAMIC PERFORMANCE

Voltage-Output Slew Rate SR 0.15 0.25 V/µs
Voltage-Output Settling Time 25 µs
Digital Feedthrough

Signal-to-Noise plus Distortion SINAD 68 dB

TA= +25°C
To ±1/2LSB, VOUT = 2V
CS = VDD, DIN = 100kHz
REFIN = 1kHz, 2Vp-p (G = +1 or +2),

code = FFF hex

5 nV-s

POWER SUPPLY

Positive Supply Voltage V
Power-Supply Current I

DD

DD

All inputs = 0V or VDD,
output = no load

MAX531
MAX538, MAX539

4.5 5.5 V
260 400
140 300

SWITCHING CHARACTERISTICS

CS Setup Time
SCLK Fall to CS Fall Hold Time
SCLK Fall to CS Rise Hold Time
SCLK High Width t
SCLK Low Width t
DIN Setup Time t
DIN Hold Time t
DOUT Valid Propagation Delay t

CS High Pulse Width
CLR Pulse Width
CS Rise to SCLK Rise Setup Time

t

CSS

t

CSH0

t

CSH1

CH
CL
DS
DH

DO

t

CSW

t

CLR

t

CS1

CL= 50pF 80 ns

20 ns
15 ns

0 ns
35 ns
35 ns
45 ns

0 ns

20 ns
25 ns
50 ns

= 33µF

REFOUT

UNITS

ppm/°C

µVp-p

0.8 V
±1

0.4 V

MAX531/MAX538/MAX539

Ω

V

µA
pF

V

µA

_______________________________________________________________________________________ 3

+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs

ELECTRICAL CHARACTERISTICS—Dual Supplies (MAX531 Only)

(VDD= +5V ±10%, VSS= -5V ±10%, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, C

= 10kΩ, CL= 100pF, TA= T

R

L

MIN

to T

, unless otherwise noted.)

MAX

REFOUT

= 33µF,

PARAMETER SYMBOL MIN TYP MAX UNITS

Resolution
Relative Accuracy INL
Differential Nonlinearity

Bipolar Offset Error V
Bipolar Offset Tempco TCV
Gain Error (Unipolar or Bipolar) GEU
Gain-Error Tempco

Power-Supply Rejection Ratio
(Note 3)

REFERENCE INPUT (REFIN)

Voltage Range
Input Resistance
Input Capacitance
AC Feedthrough -80 dB

REFERENCE OUTPUT (REFOUT—MAX531 only)

MAX531/MAX538/MAX539

Temperature Coefficient TC
Resistance R

Power-Supply Rejection Ratio PSRR 4.5V ≤ VDD≤ 5.5V 300 µV/V

Minimum Required External
Capacitor

DIGITAL INPUTS (DIN, SCLK, CS)

Input High V
Input Low V
Input Current I
Input Capacitance C

DIGITAL OUTPUT (DOUT)

Output High V
Output Low V

N 12

Tested at VDD= 5V,
VSS= -5V

DNL ±1 LSB

PSRR 0.4 1 LSB/V

REFOUT

REFOUT

e

C

MIN

Guaranteed monotonic
BIPOFF = REFIN, MAX531_C/E

OS

BIPOFF = REFIN

OS

MAX531_C/E

4.5V ≤ VDD≤ 5.5V, -5.5V ≤ VSS≤ -4.5V

Code dependent, minimum at code 555 hex
Code dependent (Note 4)
REFIN = 1kHz, 2.0Vp-p

VDD= 5.0V

MAX531AC/AE/AM/BM 30 50
MAX531BC/BE 30
(Note 5) 0.5 2 Ω

0.1Hz to 10kHz 400 µVp-pNoise Voltage

n

IH

IL

VIN= 0V or V

IN

IN

I

OH
OL

SOURCE

I

= 2mA 0.4 V

SINK

CONDITIONS

MAX531AC/E
MAX531BC/E

VSS+ 2 VDD- 2

40 kΩ
10 50 pF

TA= +25°C
MAX531BC
MAX531BE

DD

= 2mA VDD- 1 V

2.024 2.048 2.072

2.017 2.079

2.013 2.083

3.3 µF

2.4 V

±0.5

3 ppm/°C

1 ppm/°C

0.8 V

8 pF

Bits

±1

±8

±1

±1 µA

LSB

LSB

LSB

ppm/°C

V

VReference Output Voltage

4 _______________________________________________________________________________________

+5V, Low-Power, Voltage-Output,

Serial 12-Bit DACs

ELECTRICAL CHARACTERISTICS—Dual Supplies (MAX531 Only) (continued)

(VDD= +5V ±10%, VSS= -5V ±10%, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, C

= 10kΩ, CL= 100pF, TA= T

R

L

PARAMETER

VOLTAGE OUTPUT (VOUT)

Output Voltage Range
Output Load Regulation

Short-Circuit Current

DYNAMIC PERFORMANCE

Voltage-Output Slew Rate SR
Voltage-Output Settling Time 25 µs
Digital Feedthrough

Signal-to-Noise plus Distortion

POWER SUPPLY

Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current I
Negative Supply Current I

SWITCHING CHARACTERISTICS

CS Setup Time
SCLK Fall to CS Fall Hold Time
SCLK Fall to CS Rise Hold Time
SCLK High Width t
SCLK Low Width t
DIN Setup Time t
DIN Hold Time t
DOUT Valid Propagation Delay t

CS High Pulse Width
CLR Pulse Width
CS Rise to SCLK Rise Setup Time

Note 2: In single-supply operation, INL and GE calculated from code 11 to code 4095. Tested at VDD= +5V.
Note 3: This specification applies to both gain-error power-supply rejection ratio and offset-error power-supply rejection ratio.
Note 4: Guaranteed by design.
Note 5: Tested at I

= 100µA. The reference can typically source up to 5mA (see

OUT

to T

MIN

, unless otherwise noted.)

MAX

SYMBOL MIN TYP MAX UNITS

MAX531 (G = +1)
MAX531 (G = +2)
VOUT = 2V, RL= 2kΩ

I

SC

To ±1/2LSB, VOUT = 2V
Step 000 hex to FFF hex

SINAD

V

V

DD

SS

t

CSS

t

CSH0

t

CSH1

CH

CL

DS
DH
DO

t

CSW

t

CLR

t

CS1

REFIN = 1kHz, 2Vp-p, (G = +1)
REFIN = 1kHz, 2Vp-p, (G = +2)

DD
SS

CL= 50pF 80 ns

CONDITIONS

V

+ 2 V

SS

V

+ 0.4 V

SS

0.15 0.25

4.5 5.5

-5.5 0 V

20 ns
15 ns

0 ns
35 ns
35 ns
45 ns

0 ns

20 ns
25 ns
50 ns

Typical Operating Characteristics

REFOUT

12

5 nV-s
68
68

260 400 µAAll inputs = 0V or VDD, no load

-120 -200 µAAll inputs = 0V or VDD, no load

= 33µF,

- 2

DD

- 0.4

DD

1 LSB

).

MAX531/MAX538/MAX539

V

mA

V/µs

dB

V

_______________________________________________________________________________________

5

+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs

__________________________________________Typical Operating Characteristics

(VDD= +5V, V

= 2.048V, TA= +25°C, unless otherwise noted.)

REFIN

INTEGRAL NONLINEARITY vs. DIGITAL

INPUT CODE (FIRST 12 CODES)

0.25
DUAL SUPPLIES

0

-0.25

-0.50

-0.75

INTEGRAL NONLINEARITY (LSB)

-1.00

-1.25

SINGLE SUPPLY

012

2610

4

DIGITAL INPUT CODE (DECIMAL)

8

MAX531-1

OUTPUT SOURCE CAPABILITY vs.

OUTPUT PULL-UP VOLTAGE

0

MAX531/MAX538/MAX539

1
2
3
4
5
6

OUTPUT SOURCE CAPABILITY (mA)

7

8

V

V

-5 VDD-1

DD

-4 VDD-3

DD

OUTPUT PULL-UP VOLTAGE (V)

VDD-2

MAX531-4

VDD-0

SUPPLY CURRENT vs.

TEMPERATURE

300
280
260

MAX531

240
220
200
180

SUPPLY CURRENT (µA)

160
140
120

-60

-40 0 40 100

MAX538/MAX539

-20 20 80
TEMPERATURE (°C)

60

MAX531-7

INTEGRAL NONLINEARITY vs. DIGITAL

INPUT CODE (ALL CODES)

0.25

0

INTEGRAL NONLINEARITY (LSB)

-0.25
0 512 1024 1536 2048 2560 3072 3584 4095

DIGITAL INPUT CODE (DECIMAL)

ANALOG FEEDTHROUGH vs.

FREQUENCY

-110

-100

CODE = 000 hex

-90

-80

-70

-60

-50

-40

-30

ANALOG FEEDTHROUGH (dB)

-20

-10
0

1 10 1k 100k

100 10k 1M

FREQUENCY (Hz)

MAX531

GAIN vs. FREQUENCY

4

REFIN = 4Vp-p

2
0

-2

-4

-6

GAIN (dB)

-8

-10

-12

-14
1 100 100k

FREQUENCY (Hz)

1k 10k

OUTPUT SINK CAPABILITY vs.

OUTPUT PULL-DOWN VOLTAGE

16
14
12
10

8
6
4

OUTPUT SINK CAPABILITY (mA)

2
0

0 0.8

0.2 0.4

OUTPUT PULL-DOWN VOLTAGE (V)

2.055

MAX531-5

2.050

REFERENCE VOLTAGE (V)

2.045

-60

-40

AMPLIFIER SIGNAL-TO-NOISE RATIO

80

MAX531-8

SIGNAL-TO-NOISE RATIO (dB)

REFIN = 4Vp-p

70
60
50
40
30
20
10

0

10 1k 100k

0.6

MAX531

REFERENCE VOLTAGE vs.

TEMPERATURE

-20 20 80
TEMPERATURE (°C)

60

MAX531 

10k100

FREQUENCY (Hz)

MAX531-3

1.0

MAX531-6

100400

MAX531-9

6 _______________________________________________________________________________________

+5V, Low-Power, Voltage-Output,

Serial 12-Bit DACs

____________________________Typical Operating Characteristics (continued)

(VDD= +5V, V

= 2.048V, TA= +25°C, unless otherwise noted.)

REFIN

MAX531

GAIN AND PHASE vs. FREQUENCY

20

10

0

GAIN (dB)

-10

-20

-30

RFB CONNECTED TO AGND (G=2)
RFB CONNECTED TO VOUT (G=1)

1

10 100

FREQUENCY (kHz)

GAIN

PHASE

800

180

MAX531-10

0

PHASE (degrees)

-180

DIGITAL FEEDTHROUGH

MAX531 REFERENCE OUTPUT VOLTAGE

vs. REFERENCE LOAD CURRENT

2.0520

2.0515

2.0510

2.0505

2.0500

REFERENCE OUTPUT (V)

2.0495

2.0490
0 5.0

1.0 2.0 4.0

0.5 1.5 2.5 3.5 4.5
REFERENCE LOAD CURRENT (mA)

A

3.0

MAX531-14

MAX531/MAX538/MAX539

NEGATIVE SETTLING TIME (MAX531)


V

= ±5V, V

DD

A: CS RISING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div


REFIN

5µs/div

= 2V, BIPOLAR CONFIGURATION

_______________________________________________________________________________________ 7

2µs/div

CS = HIGH
A: DIN = 4Vp-p, 100kHz
B: VOUT, 10mV/div


A

B

B

POSITIVE SETTLING TIME (MAX531)


V

= ±5V, V

DD

A: CS RISING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div


REFIN

5µs/div

= 2V, BIPOLAR CONFIGURATION

A

B

+5V, Low-Power, Voltage-Output
Serial 12-Bit DACs

____________________Pin Description

PIN

MAX531

1

2 DIN Serial Data Input

3

4 SCLK Serial Clock Input
5

6 DOUT

7 DGND Digital Ground
8 AGND Analog Ground
9 REFIN Reference Input

MAX531/MAX538/MAX539

10

11 — V
12 7 VOUT DAC Output

MAX538
MAX539

—

1

—

2
3

4

—

5
6

— REFOUT

NAME

BIPOFF

CLR

CS

SS

FUNCTION

Bipolar Offset/Gain
Resistor

Clear. Asynchronously sets
DAC register to 000 hex.

Chip Select, active low
Serial Data Output for

daisy-chaining

Reference Output,

2.048V
Negative Power Supply

_______________Detailed Description

General DAC Discussion

The MAX531/MAX538/MAX539 use an “inverted” R-2R
ladder network with a single-supply CMOS op amp to con­vert 12-bit digital data to analog voltage levels (see

Functional Diagram)

ladder network because the REFIN pin in current-output
DACs is the summing junction, or virtual ground, of an op
amp. However, such use would result in the output voltage
being the inverse of the reference voltage. The
MAX531/MAX538/MAX539’s topology makes the output
the same polarity as the reference input.

An internal reset circuit forces the DAC register to reset to
000 hex on power-up. Additionally, a clear CLR pin, when
held low, sets the DAC register to 000 hex. CLR operates
asynchronously and independently from the chip-select
(CS) pin.

The output buffer is a unity-gain stable, rail-to-rail output,
BiCMOS op amp. Input offset voltage and CMRR are
trimmed to achieve better than 12-bit performance.
Settling time is 25µs to 0.01% of final value. The settling
time is considerably longer when the DAC code is initially
set to 000 hex, because at this code the op amp is com­pletely debiased. Start from code 001 hex if necessary.
The output is short-circuit protected and can drive a 2kΩ
load with more than 100pF load capacitance.

. The term “inverted” describes the

Buffer Amplifier

13 8 V
14 — RFB Feedback Resistor

CS

t

CSH0

SCLK

DIN

DOUT

Figure 1. Timing Diagram

8 _______________________________________________________________________________________

DD

t

DS

Positive Power Supply

CSS

t

CH

t

DH

t

t

CL

t

DO

t

CSH1

t

CS1

t

CSW

+5V, Low-Power, Voltage-Output,

Serial 12-Bit DACs

R

REFOUT

C

REFOUT

300

SINGLE-POLE ROLLOFF

250

)

RMS

200

150

100

REFERENCE NOISE (µV

50

0

0.1

Figure 2. Reference Noise vs. Frequency

S

C

S

TEK 7A22

C

REFOUT

1 10 100

FREQUENCY (kHz)

= 3.3µF

C

REFOUT

TOTAL
REFERENCE
NOISE

= 47µF

1000

1.8

1.6

MAX531-FIG02

1.4

1.2

1.0

0.8

0.6

0.4

REFERENCE NOISE (mVp-p)

0.2
0

Internal Reference (MAX531 only)

The on-chip reference is lesser trimmed to generate 2.048V
at REFOUT. The output stage can source and sink current,
so REFOUT can settle to the correct voltage quickly in
response to code-dependent loading changes. Typically,
source current is 5mA and sink current is 100µA.

REFOUT connects the internal reference to the R-2R DAC
ladder at REFIN. The R-2R ladder draws 50µA maximum
load current. If any other connection is made to REFOUT,
ensure that the total load current is less than 100µA to
avoid gain errors.

For applications requiring very low-noise performance,
connect a 33µF capacitor from REFOUT to AGND. If noise
is not a concern, a lower value capacitor (3.3µF min) may
be used. To reduce noise further, insert a buffered RC filter
between REFOUT and REFIN (Figure 2). The reference
bypass capacitor, C

REFOUT

, is still required for reference
stability. In applications not requiring the reference, con­nect REFOUT to VDDor use the MAX538 or MAX539 (no
internal reference).

External Reference

An external reference in the range (VSS+ 2V) to (VDD- 2V)
may be used with the MAX531 in dual-supply operation.
With the MAX538/MAX539 or the MAX531 in single-supply
use, the reference must be positive and may not exceed
VDD- 2V. The reference voltage determines the DAC’s full­scale output. The DAC input resistance is code dependent
and is minimum (40kΩ) at code 555 hex and virtually infi-

nite at code 000 hex. REFIN’s input capacitance is also
code dependent and has a 50pF maximum value at sever­al codes. Because of the code-dependent nature of refer­ence input impedances, a high-quality, low-output-imped­ance amplifier (such as the MAX480 low-power, precision
op amp) should be used.

If an upgrade to the internal reference is required, the 2.5V
MAX873A is suitable: ±15mV initial accuracy, TCV

OUT

7ppm/°C (max).

Logic Interface

The MAX531/MAX538/MAX539 logic inputs are designed to
be compatible with TTL or CMOS logic levels. However, to
achieve the lowest power dissipation, drive the digital inputs
with rail-to-rail CMOS logic. With TTL logic levels, the power
requirement increases by a factor of approximately 2.

Serial Clock and Update Rate

Figure 1 shows the MAX531/MAX538/MAX539 timing. The
maximum serial clock rate is given by 1 / (t

CH

+ tCL),
approximately 14MHz. The digital update rate is limited by
the chip-select period, which is 16 x (tCH+ tCL) + t

CSW

This equals a 1.14µs, or 877kHz, update rate. However, the
DAC settling time to 12 bits is 25µs, which may limit the
update rate to 40kHz for full-scale step transitions.

____________Applications Information

Refer to Figures 3a and 3b for typical operating connec­tions.

Serial Interface

The MAX531/MAX538/MAX539 use a three-wire serial
interface that is compatible with SPI™, QSPI™
(CPOL = CPHA = 0), and Microwire™ standards as shown
in Figures 4 and 5. The DAC is programmed by writing two
8-bit words (see Figure 1 and the
Sixteen bits of serial data are clocked into the DAC MSB
first with the MSB preceded by four fill (dummy) bits. The
four dummy bits are not normally needed. They are
required only when DACs are daisy-chained. Data is
clocked in on SCLK’s rising edge while CS is low. The seri­al input data is held in a 16-bit serial shift register. On CS
rising edge, the 12 least significant bits are transferred to
the DAC register and update the DAC. With CS
cannot be clocked into the MAX531/MAX538/MAX539.

The MAX531/MAX538/MAX539 input data in 16-bit blocks.
The SPI and Microwire interfaces output data in 8-bit
blocks, thereby requiring two write cycles to input data to
the DAC. The QSPI interface allows variable data input
from eight to 16 bits, and can be loaded into the DAC in
one write cycle.

SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corp.

Functional Diagram

high, data

MAX531/MAX538/MAX539

=

.

).

’s

_______________________________________________________________________________________ 9

+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs

DIN DOUT SCLK CS CLR

REFIN

INVERTED
R-2R DAC

REFOUT

2.048V

AGND DGND

33µF

Figure 3a. MAX531 Typical Operating Circuit

MAX531

V

0.1µF

0.1µF

V

DD

SS

2R

2R

+5V
0V TO -5V

VOUT

RFB

BIPOFF

CONNECT BIPOFF
TO VOUT FOR G = 1,
TO AGND FOR G = 2,
OR TO REFIN FOR
BIPOLAR GAIN

Daisy-Chaining Devices

The serial output, DOUT, allows cascading of two or
more DACs. The data at DIN appears at DOUT,

MAX531/MAX538/MAX539

delayed by 16 clock cycles plus one clock width. For
low power, DOUT is a CMOS output that does not
require an external pull-up resistor. DOUT does not go
into a high-impedance state when CS is high. DOUT
changes on SCLK’s falling edge when CS is low. When
CS is high, DOUT remains in the state of the last data
bit.

Any number of MAX531/MAX538/MAX539 DACs can
be daisy-chained by connecting the DOUT of one
device to the DIN of the next device in the chain. For
proper timing, ensure that tCL(CS low to SCLK high) is
greater than tDO+ tDS.

Unipolar Configuration

The MAX531 is configured for a gain of +1 (0V to V
unipolar output) by connecting BIPOFF and RFB to
VOUT (Figure 6). The converter operates from either sin­gle or dual supplies in this configuration. See Table 1 for
the DAC-latch contents (input) vs. the analog VOUT
(output). In this range, 1LSB = V

REFIN

MAX538 is internally configured for unipolar gain = +1
operation.

A gain of +2 (0V to 2V

unipolar output) is set up

REFIN

by connecting BIPOFF to AGND and RFB to VOUT
(Figure 7). Table 2 shows the DAC-latch contents vs.
VOUT. The MAX531 operates from either single or dual

(2

-12

REFIN

). The

DIN DOUTSCLK CS

REFIN

INVERTED
R-2R DAC

2R

MAX538
MAX539

AGND

0.1µF

Figure 3b. MAX538/MAX539 Typical Operating Circuit

2R

MAX539

V

DD

ONLY

+5V

supplies in this mode. In this range, 1LSB = (2)(V
(2

-12

) = (V

REFIN

-11

)(2

). The MAX539 is internally config-

VOUT

REFIN

ured for unipolar gain = +2 operation.

Bipolar Configuration

A bipolar range is set up by connecting BIPOFF to
REFIN and RFB to VOUT, and operating from dual
(±5V) supplies (Figure 8). Table 3 shows the DAC-latch
contents (input) vs. VOUT (output). In this range,
1LSB = V

REFIN

(2

-11

).

Four-Quadrant Multiplication

The MAX531 can be used as a four-quadrant multiplier
by connecting BIPOFF to REFIN and RFB to VOUT,
using (1) an offset binary digital code, (2) bipolar power
supplies, using dual power supplies, and (3) a bipolar
analog input at REFIN within the range VSS+ 2V to V

- 2V, as shown in Figure 9.
In general, a 12-bit DAC’s output is (D) (V

REFIN)

where “G” is the gain (+1 or +2) and “D” is the binary
representation of the digital input divided by 212or

4096. This formula is precise for unipolar operation.
However, for bipolar, offset binary operation, the MSB is
really a polarity bit. No resolution is lost, as there are
the same number of steps. The output voltage, howev­er, has been shifted from a range of, for example, 0V to

4.096V (G = +2) to a range of -2.048V to +2.048V.
Keep in mind that when using the DAC as a four-quad-

rant multiplier, the scale is skewed. Negative full scale
is -V

, while positive full scale is +V

REFIN

REFIN

- 1LSB.

DD

(G),

)

10 ______________________________________________________________________________________

+5V, Low-Power, Voltage-Output,

Serial 12-Bit DACs

MAX531/MAX538/MAX539

SCLK

MAX531

DIN

MAX538
MAX539

THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
DEVICE, BUT MAY BE USED FOR VERIFYING DATA TRANSFER .

CS

DOUT

SK

MICROWIRE

SO

I/O

SI

PORT

MAX531
MAX538
MAX539

THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
DEVICE, BUT MAY BE USED FOR VERIFYING DATA TRANSFER .

SCLK

DIN

CS

DOUT

Figure 4. Microwire Connection Figure 5. SPI/QSPI Connection

+5V

33µF



REFIN
REFOUT

AGND
DGND

V

DD

MAX531

V

SS

BIPOFF

RFB

VOUT

G = +1

REFIN
REFOUT

33µF

MAX531

BIPOFF

AGND

V

OUT

DGND

V

+5V

V

SCK

SPI

MOSI

PORT

I/O

MISO
CPOL = 0, CPHA = 0

DD

RFB

VOUT

SS

G = +2

V

OUT

0V TO -5V

Figure 6. Unipolar Configuration (0V to +2.048V Output)

Table 1. Unipolar Binary Code Table
(0V to V

1111 1111

1000 0000

1000 0000

0111 1111

0000 0000

0000 0000

REFIN

Output), Gain = +1

INPUT OUTPUT

4095

(V

(V

REFIN

(V

(V

REFIN

REFIN

2048

)

4096

REFIN

REFIN

)

2049

)

4096

= +V

2047

)

4096

)

4096

OV

4096

1

REFIN

/ 2



1111

0001

0000

(V

1111

0001

0000

______________________________________________________________________________________ 11

0V TO -5V

Figure 7. Unipolar Configuration (0V to +4.096V Output)

Table 2. Unipolar Binary Code Table
(0V to 2V

1111 1111

1000 0000

1000 0000

0111 1111

0000 0000

0000 0000

REFIN

INPUT OUTPUT

Output), Gain = +2

1111

0001

0000

1111

0001

0000

+2 (V

+2 (V

+2 (V

+2 (V

+2 (V

REFIN

REFIN

REFIN

REFIN

REFIN

OV

)

)

)

)

)

4095
4096

2049
4096

2048
4096

2047
4096

4096

= +V

REFIN

1

+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs

Table 3. Bipolar (Offset Binary) Code

+5V

Table (-V

REFIN

to +V

REFIN

Output)

REFIN
REFOUT

33µF

Figure 8. Bipolar Configuration (-2.048V to +2.048V Output)

MAX531

AGND
DGND

-5V

BIPOFF

RFB

VOUT

V

OUT

Single-Supply Linearity

As with any amplifier, the MAX531/MAX538/MAX539’s
output buffer can be positive or negative. When the off-

MAX531/MAX538/MAX539

set is positive, it is easily accounted for (Figure 10).
However, when the offset is negative, the buffer output
cannot follow linearly when there is no negative supply.
In that case, the amplifier output (VOUT) remains at
ground until the DAC voltage is sufficient to overcome
the offset and the output becomes positive.

Normally, linearity is measured after accounting for
zero error and gain error. Since, in single-supply opera­tion, the actual value of a negative offset is unknown, it
cannot be accounted for during test. Additionally, the
output buffer amplifier exhibits a nonlinearity near-zero
output when operating with a single supply. To account
for this nonlinearity in the MAX531/MAX538/MAX539,
linearity and gain error are measured from code 11 to
code 4095. The output buffer’s offset and nonlinear
behavior do not affect monotonicity, and these DACs
are guaranteed monotonic starting with code zero. In
dual-supply operation, linearity and gain error are mea­sured from code 0 to 4095.

Power-Supply Bypassing and

Ground Management

Best system performance is obtained with printed cir­cuit boards that use separate analog and digital
ground planes. Wire-wrap boards are not recommend­ed. The two ground planes should be connected
together at the low-impedance power-supply source.

INPUT

1111 1111

1000 0000

1000 0000
0111 1111

0000 0000

0000 0000

1111

0001

0000
1111

0001

0000

OUTPUT

(+V

REFIN

(+V

REFIN

(-V

REFIN

(-V

REFIN

(-V

REFIN

)

0V

)

2047

)

2048

2048

2048

2047

)

2048
2048

)

2048

1

1



= -V

REFIN

DGND and AGND should be connected together at the
chip. For the MAX531 in single-supply applications,
connect VSSto AGND at the chip. The best ground
connection may be achieved by connecting the DAC’s
DGND and AGND pins together and connecting that
point to the system analog ground plane. If the DAC’s
DGND is connected to the system digital ground, digi­tal noise may get through to the DAC’s analog portion.

Bypass VDD(and VSSin dual-supply mode) with a

0.1µF ceramic capacitor, connected between VDDand
AGND (and between VSSand AGND). Mount with short
leads close to the device. Ferrite beads may also be
used to further isolate the analog and digital power
supplies.

Figures 11a and 11b illustrate the grounding and
bypassing scheme described.

Saving Power

When the DAC is not being used by the system, mini­mize power consumption by setting the appropriate
code to minimize load current. For example, in bipolar
mode, with a resistive load to ground, set the DAC
code to mid-scale (Table 3). If there is no output load,
minimize internal loading on the reference by setting
the DAC to all 0s (on the MAX531, use CLR). Under this
condition, REFIN is high impedance and the op amp
operates at its minimum quiescent current. Due to
these low current levels, the output settling time for an
input code close to 0 typically increases to 60µs (no
more than 100µs).

12 ______________________________________________________________________________________

+5V, Low-Power, Voltage-Output,

Serial 12-Bit DACs

MAX531/MAX538/MAX539

CS

CLR

DIN DOUT

2.048V

REFOUT

VDDV

SS

POSITIVE OFFSET

SIGNAL

REFIN

IN

INVERTED
R-2R DAC

MAX531

VOUT

2R

2R

RFB

BIPOFF

Figure 9. MAX531 Connected as Four-Quadrant Multiplier. The
unused REFOUT is connected to V

DD

.

AC Considerations

Digital Feedthrough

High-speed serial data at any of the digital input or output
pins may couple through the DAC package and cause
internal stray capacitance to appear at the DAC output as
noise, even though CS is held high (see

Characteristics

). This digital feedthrough is tested by hold-

Typical Operating

ing CS high, transmitting 555 hex from DIN to DOUT.

Analog Feedthrough

Because of internal stray capacitance, higher frequency
analog input signals may couple to the output as shown in
the Analog Feedthrough vs. Frequency graph in the

Typical Operating Characteristics

. It is tested by holding
CS high, setting the DAC code to all 0s, and sweeping
REFIN.

4

OUTPUT (LSB)

3
2
1
0

123 45678

DAC CODE (LSB)

Figure 10. Single-Supply Offset

ANALOG GROUND PLANE

1
2
3
4
5
6
7

(a) MAX531 BYPASSING

NEGATIVE OFFSET

0.1µF

14
13
12
11
10

9

0.1µF

8

1
2
3
4

(b) MAX538/MAX539 BYPASSING

8
7
6

0.1µF

5

Figure 11. Power-Supply Bypassing

______________________________________________________________________________________ 13

+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs

__Ordering Information (continued)

PIN-PACKAGETEMP. RANGEPART

14 Plastic DIP-40°C to +85°CMAX531AEPD

14 Plastic DIP-40°C to +85°CMAX531BEPD

14 SO-40°C to +85°CMAX531AESD

MAX538ACPA

Dice*0°C to +70°CMAX538BC/D

MAX539ACPA

MAX531/MAX538/MAX539

*Dice are specified at TA= +25°C only.

ERROR

(LSB)

±1/2
±1
±1/2
±114 SO-40°C to +85°CMAX531BESD
±1/28 Plastic DIP0°C to +70°C
±18 Plastic DIP0°C to +70°CMAX538BCPA
±1/28 SO0°C to +70°CMAX538ACSA
±18 SO0°C to +70°CMAX538BCSA
±1
±1/28 Plastic DIP-40°C to +85°CMAX538AEPA
±18 Plastic DIP-40°C to +85°CMAX538BEPA
±1/28 SO-40°C to +85°CMAX538AESA
±18 SO-40°C to +85°CMAX538BESA
±1/28 Plastic DIP0°C to +70°C
±18 Plastic DIP0°C to +70°CMAX539BCPA
±1/28 SO0°C to +70°CMAX539ACSA
±18 SO0°C to +70°CMAX539BCSA
±1Dice*0°C to +70°CMAX539BC/D
±1/28 Plastic DIP-40°C to +85°CMAX539AEPA
±18 Plastic DIP-40°C to +85°CMAX539BEPA
±1/28 SO-40°C to +85°CMAX539AESA
±18 SO-40°C to +85°CMAX539BESA

____Pin Configurations (continued)

TOP VIEW

BIPOFF

DIN

CLR

SCLK

DOUT

DGND

1
2

MAX531

3
4

CS

5
6
7

RFB

14

V

13

DD

VOUT

12
11

V

SS

REFOUT

10

REFIN

9

AGND

8

DIP/SO

___________________Chip Topography

(CLR)

SCLK

DOUT

DIN (BIPOFF)(RFB) V

CS

(DGND)

(2.032mm)

AGND

0.080"

DD

VOUT

(VSS)

(REFOUT)

REFIN

0.120"

(3.048mm)

( ) ARE FOR MAX531 ONLY.

TRANSISTOR COUNT: 922
SUBSTRATE CONNECTED TO V

DD

14 ______________________________________________________________________________________

+5V, Low-Power, Voltage-Output,

Serial 12-Bit DACs

________________________________________________________Package Information

PDIPN.EPS

MAX531/MAX538/MAX539

______________________________________________________________________________________ 15

+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs

__________________________________________Package Information (continued)

SOICN.EPS

MAX531/MAX538/MAX539

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

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