Rainbow Electronics MAX530 User Manual

19-0168; Rev 3; 7/95

+5V, Low-Power, Parallel-Input,

Voltage-Output, 12-Bit DAC

_______________General Description

The MAX530 is a low-power, 12-bit, voltage-output digi­tal-to-analog converter (DAC) that uses single +5V or
dual ±5V supplies. This device has an on-chip voltage
reference plus an output buffer amplifier. Operating cur­rent is only 250µA from a single +5V supply, making it
ideal for portable and battery-powered applications. In
addition, the SSOP (Shrink-Small-Outline-Package) mea­sures only 0.1 square inches, using less board area than
an 8-pin DIP. 12-bit resolution is achieved through laser
trimming of the DAC, op amp, and reference. No further
adjustments are necessary.

Internal gain-setting resistors can be used to define a
DAC output voltage range of 0V to +2.048V, 0V to
+4.096V, or ±2.048V. Four-quadrant multiplication is pos­sible without the use of external resistors or op amps. The
parallel logic inputs are double buffered and are compati­ble with 4-bit, 8-bit, and 16-bit microprocessors. For DACs
with similar features but with a serial data interface, refer
to the MAX531/MAX538/MAX539 data sheet.

________________________Applications

Battery-Powered Data-Conversion Products
Minimum Component-Count Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Arbitrary Function Generators
Automatic Test Equipment
Microprocessor-Controlled Calibration

________________Functional Diagram

REFOUT REFIN ROFS

REFGND

AGND

CLR

LDAC

18 13 22

2.048V

REFERENCE

17

24 1
D0/D8

D1/D9

DAC LATCH

12-BIT DAC LATCH

NBM

NBL
INPUT
LATCH

D2/D10

INPUT
LATCH

234567

D4

D5

D3/D11

MAX530

D6

D7

14

POWER-ON

RESET

15

8

A0

9

A1

CONTROL

11

LOGIC

CS

10

WR

16

NBH
INPUT
LATCH

21

RFB

20

VOUT

23

V

DD

12

DGND

19

V

SS

____________________________Features

♦ Buffered Voltage Output
♦ Internal 2.048V Voltage Reference
♦ Operates from Single +5V or Dual ±5V Supplies
♦ Low Power Consumption:

250µA Operating Current
40µA Shutdown-Mode Current

♦ SSOP Package Saves Space

1

♦ Relative Accuracy: ±

Temperature

/

LSB Max Over

2

♦ Guaranteed Monotonic Over Temperature
♦ 4-Quadrant Multiplication with No External

Components

♦ Power-On Reset
♦ Double-Buffered Parallel Logic Inputs

______________Ordering Information

PART TEMP. RANGE PIN-PACKAGE

MAX530ACNG 0°C to +70°C 24 Narrow Plastic DIP
MAX530BCNG 0°C to +70°C 24 Narrow Plastic DIP
MAX530ACWG 0°C to +70°C 24 Wide SO
MAX530BCWG 0°C to +70°C 24 Wide SO
MAX530ACAG 0°C to +70°C 24 SSOP
MAX530BCAG 0°C to +70°C 24 SSOP
MAX530BC/D 0°C to +70°C Dice* ±1

Ordering Information continued on last page.

* Dice are tested at T

= +25°C, DC parameters only.

A

ERROR

(LSB)

1

/

±

2

±1

1

/

±

2

±1

1

/

±

2

±1

__________________Pin Configuration

TOP VIEW

D1/D9
D2/D10
D3/D11

WR

DGND

1
2
3

D4

4

D5

5

D6

6

D7

7

A0

8

A1

9

10

CS

11
12

DIP/SO/SSOP

MAX530

24
23

22
21
20

19
18
17
16
15
14
13

D0/D8
V

DD

ROFS
RFB
VOUT
V

SS

REFOUT
REFGND
LDAC
CLR
AGND
REFIN

MAX530

________________________________________________________________

Maxim Integrated Products

Call toll free 1-800-998-8800 for free samples or literature.

1

+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC

ABSOLUTE MAXIMUM RATINGS

VDDto DGND and VDDto AGND................................-0.3V, +6V

to DGND and VSSto AGND .................................-6V, +0.3V

V

SS

to VSS............................................................... -0.3V, +12V

V

DD

AGND to DGND........................................................-0.3V, +0.3V

REFGND to AGND........................................-0.3V, (V

Digital Input Voltage to DGND ................... -0.3V, (V

REFIN.................................................(V

MAX530

REFOUT.............................................(V

REFOUT to REFGND................................... -0.3V, (V

RFB ...................................................(V

ROFS .................................................(V

Note 1: The output may be shorted to VDD, VSS, DGND, or AGND if the continuous package power dissipation and current ratings

are not exceeded. Typical short-circuit currents are 20mA.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

- 0.3V), (VDD+ 0.3V)

SS

- 0.3V), (VDD+ 0.3V)

SS

- 0.3V), (VDD+ 0.3V)

SS

- 0.3V), (VDD+ 0.3V)

SS

DD
DD

DD

+ 0.3V)
+ 0.3V)

+ 0.3V)

VOUT to AGND (Note 1) .............................................. V

Continuous Current, Any Input ........................................±20mA

Continuous Power Dissipation (T

Narrow Plastic DIP (derate 13.33mW/°C above +70°C)......1067mW

Wide SO (derate 11.76mW/°C above +70°C) .......... 941mW

SSOP (derate 8.00mW/°C above +70°C) ..................640mW

Operating Temperature Ranges:

MAX530_C_ _ ...................................................0°C to +70°C

MAX530_E_ _ ................................................-40°C to +85°C

Storage Temperature Range.............................-65°C to +165°C

Lead Temperature (soldering, 10sec ) .......................... +300°C

= +70°C)

A

SS,VDD

ELECTRICAL CHARACTERISTICS—Single +5V Supply

(VDD= 5V ±10%, VSS= 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, C
RL= 10kΩ, CL= 100pF, TA= T

STATIC PERFORMANCE

Unipolar Offset Error
Unipolar Offset

Temperature Coefficient
Unipolar Offset-Error

Power-Supply Rejection

Gain Error (Note 2)

DAC VOLTAGE OUTPUT (VOUT)

Output Voltage Range

Short-Circuit Current

REFERENCE INPUT (REFIN)

MIN

to T

, unless otherwise noted.)

MAX

VDD= 5V (Note 2)

INLRelative Accuracy

Guaranteed monotonic LSB±1DNLDifferential Nonlinearity
VDD= 5V

OS

OS

4.5V ≤ VDD≤ 5.5V (Note 3)

DAC latch = all 1s,
VOUT < VDD- 0.4V
(Note 2)

4.5V ≤ VDD≤ 5.5V (Note 3)

VOUT = 2V, load regulation ≤ ±1LSB kΩ2Resistive Load

SC

Code dependent, minimum at code 555hex kΩ40Reference Input Resistance
Code dependent (Note 4) pF10 50Reference Input Capacitance
(Note 5) dB-80AC Feedthrough

CONDITIONS

MAX530AC/AE
MAX530BC/BE

MAX530_C/E

MAX530_C/E

REFOUT

±0.5

±1

- 0.4

DD

- 2Reference Input Range

DD

= 33µF,

UNITSMIN TYP MAXSYMBOLPARAMETER

ppm/°C3TCV

LSB/V0.4 1PSRR

ppm/°C1Gain-Error Temperature Coefficient

LSB/V0.4 1PSRRGain-Error Power-Supply Rejection

Bits12NResolution
LSB

LSB018V

LSB±1GE

V0V

Ω0.2DC Output Impedance

mA20I

V0V

2 _______________________________________________________________________________________

+5V, Low-Power, Parallel-Input,

LDAC, CLR, CS, WR

Voltage-Output, 12-Bit DAC

ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)

(VDD= 5V ±10%, VSS= 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, C

= 10kΩ, CL= 100pF, TA= T

R

L

PARAMETER

REFERENCE OUTPUT (REFOUT)

Reference Tolerance V

Reference Output Resistance R
Power-Supply Rejection Ratio PSRR 300 µV/V
Noise Voltage e

Temperature Coefficient
Minimum Required External

Capacitor

DYNAMIC PERFORMANCE

Voltage Output Slew Rate
Voltage Output Settling Time
Digital Feedthrough 5 nV-s

Signal-to-Noise Plus
Distortion Ratio

DIGITAL INPUTS (D0-D7,

Logic High Input V
Logic Low Input V
Digital Leakage Current ±1 µA
Digital Input Capacitance 8 pF

POWER SUPPLIES

Positive Supply-Voltage Range V
Positive Supply Current I

SWITCHING CHARACTERISTICS

Address to WR Setup t
Address to WR Hold t
CS to WR Setup t
CS to WR Hold t
Data to WR Setup
Data to WR Hold
WR Pulse Width t
LDAC Pulse Width t
CLR Pulse Width t

Internal Power-On Reset
Pulse Width

to T

MIN

, unless otherwise noted.)

MAX

SYMBOL MIN TYP MAX30UNITS

REFOUT

REFOUT

C

MIN

SINAD

VDD= 5.0V

(Note 8)

4.5V ≤ VDD≤ 5.5V

0.1Hz to 10kHz

n

MAX530AC/AE
MAX530BC/BE

TA= +25°C
To ±0.5LSB, VOUT = 2V
WR = VDD, digital inputs all 1s to all 0s
Unity gain (Note 5)
Gain = 2 (Note 5)

, A0, A1)

IH

IL

VIN= 0V or V

(Note 6) 4.5 5.5 V

DD

Outputs unloaded, all digital inputs = 0V or V

DD

AWS
AWH
CWS
CWH

t

DS

t

DH

WR

LDAC

CLR

t

(Note 4) 1.3 10 µs

POR

CONDITIONS

DD

MAX530BC
MAX530BE

2.024 2.048 2.072TA= +25°C

2.013 2.083

400

30 50

3.3 µF

0.15 0.25 V/µs
25

68
68

2.4 V

DD

250 400 µA

5 ns
5 ns
0 ns
0 ns

45 ns

0 ns
45 ns
45 ns
45 ns

REFOUT

2 Ω

0.8 V

= 33µF,

µVp-p

ppm/°C

MAX530

V2.017 2.079

µs

dB

_______________________________________________________________________________________ 3

+5V, Low-Power, Parallel-Input,

LDAC, CLR, CS, WR

Voltage-Output, 12-Bit DAC

ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies

(VDD= 5V ±10%, VSS= -5V ±10%, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT,
C

= 33µF, RL= 10kΩ, CL= 100pF, TA= T

REFOUT

MIN

to T

, unless otherwise noted.)

MAX

CONDITIONS

STATIC PERFORMANCE

MAX530

VDD= 5V, VSS= -5V

INLRelative Accuracy

Guaranteed monotonic LSB±1DNLDifferential Nonlinearity
Bipolar Offset Error
Bipolar Offset

Temperature Coefficient
Bipolar Offset-Error

Power-Supply Rejection
Gain Error

DAC VOLTAGE OUTPUT (VOUT)

Output Voltage Range

Short-Circuit Current

REFERENCE INPUT (REFIN)

REFERENCE OUTPUT (REFOUT)—Specifications are identical to those under Single +5V Supply
DYNAMIC PERFORMANCE—Specifications are identical to those under Single +5V Supply
DIGITAL INPUTS (D0-D7,
POWER SUPPLIES

Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
SWITCHING CHARACTERISTICS—Specifications are identical to those under Single +5V Supply

VDD= 5V, VSS= -5V

OS

OS

4.5V ≤ VDD≤ 5.5V

-5.5V ≤ VSS≤ -4.5V (Note 3)

MAX530_C/E

4.5V ≤ VDD≤ 5.5V, -5.5V ≤ VSS≤ -4.5V (Note 3)

VOUT = 2V, load regulation ≤ ±1LSB kΩ2Resistive Load

SC

Code dependent, minimum at code 555hex kΩ40Reference Input Resistance

Code dependent (Note 4) pF10 50Reference Input Capacitance

(Note 5) dB-80AC Feedthrough

, A0, A1)—Specifications are identical to those under Single +5V Supply

(Note 6) V4.5 5.5V

DD

(Note 7) V-5.5 -4.5V

SS

Outputs unloaded, all digital inputs = 0V or V

DD

Outputs unloaded, all digital inputs = 0V or V

SS

MAX530AC/AE ±0.5
MAX530BC/BE

MAX530_C/E

DD
DD

UNITSMIN TYP MAXSYMBOLPARAMETER

Bits12NResolution

LSB

±1.5

LSB0±8V

3TCV

0.4 1PSRRGain-Error Power-Supply Rejection

ppm/°C

LSB/V0.4 1PSRR

LSB±1

ppm/°C1TCGain-Error Temperature Coefficient

LSB/V

VVSS+ 0.4 VDD- 0.4

Ω0.2DC Output Impedance

mA20I

VVSS+ 2 VDD- 2Reference Input Range

µA250 400I
µA150 200I

4 _______________________________________________________________________________________

+5V, Low-Power, Parallel-Input,

Voltage-Output, 12-Bit DAC

ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (continued)

(VDD= 5V ±10%, VSS= -5V ±10%, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT,
C

Note 2: In single supply, INL and GE are calculated from code 11 to code 4095.
Note 3: Zero Code, Bipolar and Gain Error PSRR are input referred specifications. In Unity Gain, the specification is 500µV.

Note 4: Guaranteed by design.
Note 5: REFIN = 1kHz, 2.0Vp-p.
Note 6: For specified performance, V
Note 7: For specified performance, V
Note 8: Tested at I

= 33µF, RL= 10kΩ, CL= 100pF, TA= T

REFOUT

In Gain = 2 and Bipolar modes, the specification is 1mV.

= 5V ±10% is guaranteed by PSRR tests.

DD

= -5V ±10% is guaranteed by PSRR tests.

= 100µA. The reference can typically source up to 5mA (see

OUT

SS

MIN

to T

, unless otherwise noted.)

MAX

Typical Operating Characteristics

).

__________________________________________Typical Operating Characteristics

(TA = +25°C, single supply (+5V), unity gain, code = all 1s, unless otherwise noted).

INTEGRAL NONLINEARITY vs.

0.25

-0.50

INTEGRAL NONLINEARITY (LSB)

-1.00

-1.25

DIGITAL INPUT CODE (0–11)

DUAL
SUPPLIES

0

SINGLE
SUPPLY

012

2610

4

DIGITAL INPUT CODE (DECIMAL)

8

0.25

MAX530-1

-0.25

INTEGRAL NONLINEARITY vs.

DIGITAL INPUT CODE (11–4095)

0

INTEGRAL NONLINEARITY (LSB)

11 512 10241536 2048 2560 3072 3584 4095

DIGITAL INPUT CODE (DECIMAL)

OUTPUT SINK CAPABILITY (mA)

OUTPUT SINK CAPABILITY vs.

OUTPUT PULL-DOWN VOLTAGE

16
14
12
10

8
6
4
2

0

0 0.8

0.2 0.4

OUTPUT PULL-DOWN VOLTAGE (V)

0.6

MAX530

MAX531-3

1.0

OUTPUT SOURCE CAPABILITY vs.

OUTPUT PULL-UP VOLTAGE

8
7
6
5
4
3
2

OUTPUT SOURCE CAPABILITY (mA)

1
0

12

04

OUTPUT PULL-UP VOLTAGE (V)

3

MAX531-4

5

_______________________________________________________________________________________

ANALOG FEEDTHROUGH vs.

-110

-100

-90

-80

-70

-60

-50

-40

-30

ANALOG FEEDTHROUGH (dB)

-20

-10
0

1 10 1k 100k

FREQUENCY

REFIN = 2V

p-p

CODE = ALL 0s,
DUAL SUPPLIES (±5V)

100 10k 1M

FREQUENCY (Hz)

REFERENCE VOLTAGE vs.

2.055

MAX531-5

2.050

REFERENCE VOLTAGE (V)

2.045

-60 120

TEMPERATURE

-20 20 80
TEMPERATURE (°C)

MAX531-6

60

100400-40

140

5

+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC

____________________________Typical Operating Characteristics (continued)

(TA = +25°C, single supply (+5V), unity gain, code = all 1s, unless otherwise noted).

SUPPLY CURRENT vs. TEMPERATURE

300

290

MAX530

280

270

260

250

SUPPLY CURRENT (µA)

240

230

-60 -20

-40 0 40 80

GAIN AND PHASE vs.

-200

-100

0

GAIN (dB)

-100

-200

-300
1

FREQUENCY

(G = 2)

(G = 1)

10 100

FREQUENCY (kHz)

20

TEMPERATURE (°C)

GAIN

PHASE

4

GAIN vs. FREQUENCY

MAX530-7

GAIN (dB)

60

100

180

MAX530-10

0

PHASE SHIFT (Degrees)

SUPPLY CURRENT (µA)

-180

800

REFIN = 4Vp-p

2
0

-2

-4

-6

-8

-10

-12

-14
1 100 100k

250

200

150

100

50

0

DUAL SUPPLIES (±5V)

1k 10k

FREQUENCY (Hz)



SUPPLY CURRENT vs. REFIN

REFGND = AGND

REFGND = V

DD

REFIN = EXTERNAL

0 500

100 200 400

50 150 250 350 450

300

REFIN (mV)

MAX531-8

MAX530-14

AMPLIFIER SIGNAL-TO-NOISE RATIO

80

REFIN = 4Vp-p

70
60
50
40
30
20

SIGNAL-TO-NOISE RATIO (dB)

10

0

2.0480

2.0475

2.0470

2.0465

2.0460

REFERENCE OUTPUT (V)

2.0455

2.0450

DUAL SUPPLIES (±5V)

10 1k 100k

0 5.0

FREQUENCY (Hz)



REFERENCE OUTPUT VOLTAGE

vs. REFERENCE LOAD CURRENT

1.0 2.0 4.0

0.5 1.5 2.5 3.5 4.5
REFERENCE LOAD CURRENT (mA)

3.0

MAX531-9

10k100

MAX530-15

DIGITAL FEEDTHROUGH

A

SETTLING TIME (RISING)

SETTLING TIME (FALLING)

A

B

B

A: D0...D7 = 100kHz, 4Vp-p

2µs/div

B: VOUT, 10mV/div
LDAC = CS = HIGH 

5µs/div

A: DIGITAL INPUTS RISING EDGE,

NO LOAD, 1V/div

B: VOUT

,

DUAL SUPPLY (±5V)
LDAC = LOW
BIPOLAR CONFIGURATION

= 2V

V

REFIN



A: DIGITAL INPUTS FALLING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div
DUAL SUPPLY (±5V)
LDAC = LOW
BIPOLAR CONFIGURATION

= 2V

V

REFIN

5µs/div

6 _______________________________________________________________________________________

A

B

+5V, Low-Power, Parallel-Input,

Voltage-Output, 12-Bit DAC

______________________________________________________________Pin Description

NAME

D1/D9
D2/D10
D3/D11

D4

A08

A19

REFIN13

LDAC16

REFGND17

19

23

* This applies to 4 + 4 + 4 input loading mode. See Table 2 for 8 + 4 input loading mode.

SS

DD

D0/D824

D1 Input Dta, when A0 = 0 and A1 = 1, or D9 Input when A0 = A1 = 1*1
D2 Input Dta, when A0 = 0 and A1 = 1, or D10 Input when A0 = A1 = 1*2
D3 Input Dta, when A0 = 0 and A1 = 1, or D11 (MSB) Input when A0 = A1 =1*3
D4 Input Dta, or tie to D0 and multiplex when A0 = 1 and A1 = 0*4
D5 Input Dta, or tie to D1 and multiplex when A0 = 1 and A1 = 0*D55
D6 Input Dta, or tie to D2 and multiplex when A0 = 1 and A1 = 0*D66
D7 Input Dta, or tie to D3 and multiplex when A0 = 1 and A1 = 0*D77
Address Line A0. With A1, used to multiplex 4 of 12 data lines to load low (NBL), middle (NBM),

and high (NBH) 4-bit nibbles. (12 bits can also be loaded as 8+4.)
Address Line A1. Set A0 = A1 = 0 for NBL and NBM, A0 = 0 and A1 = 1 for NBL, A0 = 1 and

A1 = 0 for NBM, or A0 = A1 = 1 for NBH. See Table 2 for complete input latch addressing.
Write Input (active low). Used with CS to load data into the input latch selected by A0 and A1.WR10
Chip Select (active low). Enables addressing and writing to this chip from common bus lines.CS11
Digital GroundDGND12
Reference Input. Input for the R-2R DAC. Connect an external reference to this pin or a jumper to

REFOUT (pin 18) to use the internal 2.048V reference.
Analog GroundAGND14
Clear (active low). A low on CLR resets the DAC latches to all 0s.CLR15
Load DAC Input (active low). Driving this asynchronous input low transfers the contents of the input

latch to the DAC latch and updates VOUT.
Reference Ground must be connected to AGND when using the internal reference. Connect to V

to disable the internal reference and save power.
Reference Output. Output of the internal 2.048V reference. Tie to REFIN to drive the R-2R DAC.REFOUT18
Negative Power Supply. Usually ground for single-supply or -5V for dual-supply operation.V
Voltage Output. Op-amp buffered DAC output.VOUT20
Feedback Pin. Op-amp feedback resistor. Always connect to VOUT.RFB21
Offset Resistor Pin. Connect to VOUT for G = 1, to AGND for G = 2, or to REFIN for bipolar output.ROFS22
Positive Power Supply (+5V)V
D0 (LSB) Input Dta when A0 = 0 and A1 = 1, or D8 Input when A0 = A1= 1*

FUNCTIONPIN

DD

MAX530

_______________________________________________________________________________________ 7

+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC

________________Detailed Description

The MAX530 consists of a parallel-input logic interface, a
12-bit R-2R ladder, a reference, and an op amp. The

Functional Diagram

flow through the input data latch to the DAC latch, as well
as the 2.048V reference and output op amp. Total supply
current is typically 250µA with a single +5V supply. This

MAX530

circuit is ideal for battery-powered, microprocessor-con­trolled applications where high accuracy, no adjustments,
and minimum component count are key requirements.

The MAX530 uses an “inverted” R-2R ladder network with
a BiCMOS op amp to convert 12-bit digital data to analog
voltage levels. Figure 1 shows a simplified diagram of the
R-2R DAC and op amp. Unlike a standard DAC, the
MAX530 uses an “inverted” ladder network. Normally, the
REFIN pin is the current output of a standard DAC and
would be connected to the summing junction, or virtual
ground, of an op amp. In this standard DAC configura-

LSB

*

REFIN
AGND

REFOUT

2.048V

REFGND

Figure 1. Simplified MAX530 DAC Circuit

D0/D8

INPUT
LATCH

D1/D9

LSB

NBL

shows the control lines and signal

R-2R Ladder

MAX530



RRR

2R2R 2R 2R 2R

MSB

MSB

NBH

INPUT

LATCH

*SHOWN FOR ALL 1s

D2/D10

D3/D11

DAC LATCH

NBM
INPUT
LATCH

D4

D6

D5

D7

2R
2R

OUTPUT
BUFFER

R = 80kΩ

CLR

ROFS
RFB

VOUT

tion, however, the output voltage would be the inverse of
the reference voltage. The MAX530’s topology makes the
ladder output voltage the same polarity as the reference
input, which makes the device suitable for single-supply
operation. The BiCMOS op amp is then used to buffer,
invert, or amplify the ladder signal.

Ladder resistors are nominally 80kΩ to conserve power
and are laser trimmed for gain and linearity. The input
impedance at REFIN is code dependent. When the DAC
register is all 0s, all rungs of the ladder are grounded
and REFIN is open or no load. Maximum loading (mini­mum REFIN impedance) occurs at code 010101... or
555hex. Minimum reference input impedance at this
code is guaranteed to be not less than 40kΩ.

The REFIN and REFOUT pins allow the user to choose
between driving the R-2R ladder with the on-chip refer­ence or an external reference. REFIN may be below ana­log ground when using dual supplies. See the

Reference

and

Four-Quadrant Multiplication

External

sections for

more information.

Internal Reference

The on-chip reference is laser trimmed to generate

2.048V at REFOUT. The output stage can source and
sink current so REFOUT can settle to the correct volt­age quickly in response to code-dependent loading
changes. Typically source current is 5mA and sink cur­rent is 100µA.

REFOUT connects the internal reference to the R-2R
DAC ladder at REFIN. The R-2R ladder draws 50µA
maximum load current. If any other connection is made
to REFOUT, ensure that the total load current is less
than 100µA to avoid gain errors.

A separate REFGND pin is provided to isolate refer­ence currents from other analog and digital ground
currents. To achieve specified noise performance, con­nect a 33µF capacitor from REFOUT to REFGND (see
Figure 2). Using smaller capacitance values increases
noise, and values less than 3.3µF may compromise the
reference’s stability. For applications requiring the low­est noise, insert a buffered RC filter between REFOUT
and REFIN. When using the internal reference,
REFGND must be connected to AGND. In applications
not requiring the internal reference, connect REFGND
to V

, which shuts down the reference and saves typ-

DD

ically 100µA of V

supply current.

DD

8 _______________________________________________________________________________________

+5V, Low-Power, Parallel-Input,

Voltage-Output, 12-Bit DAC

R

REFOUT

C

REFOUT

300

SINGLE POLE ROLLOFF

250

)

RMS

200

150

100

REFERENCE NOISE (µV

50

0

0.1

Figure 2. Reference Noise vs. Frequency

S

C

S

TEK 7A22

C

REFOUT

1 10 100

FREQUENCY (kHz)

= 3.3µF

C

REFOUT

TOTAL
REFERERNCE
NOISE

= 47µF

1000

1.8

1.6

MAX531-FIG02

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

REFERENCE NOISE (mVp-p)

Output Buffer

The output amplifier uses a folded cascode input stage
and a type AB output stage. Large output devices with
low series resistance allow the output to swing to
ground in single-supply operation. The output buffer is
unity-gain stable. Input offset voltage and supply cur­rent are laser trimmed. Settling time is 25µs to 0.01% of
final value. The output is short-circuit protected and
can drive a 2kΩ load with more than 100pF of load
capacitance. The op amp may be placed in unity-gain
(G = 1), in a gain of two (G = 2), or in a bipolar-output
mode by using the ROFS and RFB pins. These pins are
used to define a DAC output voltage range of 0V to
+2.048V, 0V to +4.096V or ±2.048V, by connecting
ROFS to VOUT, GND, or REFIN. RFB is always con­nected to VOUT. Table 1 summarizes ROFS usage.

Table 1. ROFS Usage

ROFS

CONNECTED TO:

VOUT 0V to 2.048V G = 1
AGND 0V to 4.096V G = 2
REFIN -2.048V to +2.048V Bipolar

Note: Assumes RFB = VOUT and REFIN = REFOUT = 2.048V

DAC OUTPUT

RANGE

OP-AMP

GAIN

An external reference in the range (VSS+ 2V) to

External Reference

(VDD- 2V) may be used with the MAX530 in dual-sup­ply, unity-gain operation. In single-supply, unity-gain
operation, the reference must be positive and may not
exceed (VDD- 2V). The reference voltage determines
the DAC’s full-scale output. Because of the code­dependent nature of reference input impedances, a
high-quality, low-output-impedance amplifier (such as
the MAX480 low-power, precision op amp) should be
used to drive REFIN.

If an upgrade to the internal reference is required, the

2.5V MAX873A is ideal: ±15mV initial accuracy,
7ppm/°C (max) temperature coefficient.

Power-On Reset

An internal power-on reset (POR) circuit forces the
DAC register to reset to all 0s when VDDis first applied.
The POR pulse is typically 1.3µs; however, it may take
2ms for the internal reference to charge its large filter
capacitor and settle to its trimmed value.

In addition to POR , a clear (CLR) pin, when held low,
sets the DAC register to all 0s. CLR operates asynchro­nously and independently from chip select (CS). With
the DAC input at all 0s, the op-amp output is at zero for
unity-gain and G = 2 configurations, but it is at -V

REF

for the bipolar configuration.

Shutdown Mode

The MAX530 is designed for low power consumption.
Understanding the circuit allows power consumption
management for maximum efficiency. In single-supply
mode (VDD= +5V, VSS= GND) the initial supply cur­rent is typically only 160µA, including the reference, op
amp, and DAC. This low current occurs when the
power-on reset circuit clears the DAC to all 0s and
forces the op-amp output to zero (unipolar mode only).
See the Supply Current vs. REFIN graph in the

Operating Characteristics

. Under this condition, there

Typical

is no internal load on the reference (DAC = 000hex,
REFIN is open circuit) and the op amp operates at its
minimum quiescent current. The CLR signal resets the
MAX530 to these same conditions and can be used to
control a power-saving mode when the DAC is not
being used by the system.

MAX530

_______________________________________________________________________________________ 9

+5V, Low-Power, Parallel-Input,

CLR CS WR LDAC

Voltage-Output, 12-Bit DAC

REFOUT REFIN ROFS

33µF

MAX530

MAX530

2N7002

CLR

REFGND

LDAC

WR

AGND

DGND

A0
A1
CS

POWER-ON

RESET

CONTROL

LOGIC

Figure 3. Low-Current Shutdown Mode

An additional 110µA of supply current can be saved
when the internal reference is not used by connecting
REFGND to VDD. A low on resistance N-channel FET,
such as the 2N7002, can be used to turn off the internal
reference to create a shutdown mode with minimum
current drain (Figure 3). When CLR is high, the transis­tor pulls REFGND to AGND and the reference and DAC
operate normally. When CLR goes low, REFGND is
pulled up to VDDand the reference is shut down. At the
same time, CLR resets the DAC register to all 0s, and
the op-amp output goes to 0V for unity-gain and G = 2

Table 2. Input Latch Addressing

L X X X X X Reset DAC Latches
H H X H X X No Operation
H X H H X X No Operation
H L L H H H NBH (D8-D11)
H L L H H L NBM (D4-D7)
H L L H L H NBL (D0-D3)
H H H L X X Update DAC Only
H L L X L L DAC NOT UPDATED
H L L L H H NBH and Update DAC

A0 A1 DATA UPDATED

2.048V

REFERENCE

D0/D8

MAX530



NBL
INPUT
LATCH

D1/D9

RFB

V

OUT

DAC

V

DD

+5V

V

SS

D2/D10

12-BIT DAC LATCH

D3/D11

NBM
INPUT
LATCH

D4

D6

D5

NBH

INPUT

LATCH

D7

modes. This reduces the total single-supply operating
current from 250µA (400µA max) to typically 40µA in
shutdown mode.

A small error voltage is added to the reference output
by the reference current flowing through the N-channel
pull-down transistor. The switch’s on resistance should
be less than 5Ω. A typical reference current of 100µA
would add 0.5mV to REFOUT. Since the reference cur­rent and on resistance increase with temperature, the
overall temperature coefficient will degrade slightly.

As data is loaded into the DAC and the output moves
above GND, the op-amp quiescent current increases to
its nominal value and the total operating current aver­ages 250µA. Using dual supplies (±5V), the op amp is
fully biased continuously, and the VDDsupply current is
more constant at 250µA. The V

current is typically

SS

150µA.
The MAX530 logic inputs are compatible with TTL and

CMOS logic levels. However, to achieve the lowest
power dissipation, drive the digital inputs with rail-to-rail
CMOS logic. With TTL logic levels, the power require­ment increases by a factor of approximately 2.

10 ______________________________________________________________________________________

A0-A1

+5V, Low-Power, Parallel-Input,

Voltage-Output, 12-Bit DAC

MAX530

ADDRESS BUS VALID

V

IH

V

IL

t

CS

t

WR

CWS

t

t

AWS

WR

AWH

t

CWH

DATA BITS

(8-BIT BYTE OR

4-BIT NIBBLE)

Figure 4. MAX530 Write-Cycle Timing Diagram



CLR

LDAC

NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS

t

CLR

V

IH + VIL

2

Parallel Logic Interface

Designed to interface with 4-bit, 8-bit, and 16-bit micro­processors (µPs), the MAX530 uses 8 data pins and
double-buffered logic inputs to load data as 4 + 4 + 4
or 8 + 4. The 12-bit DAC latch is updated simultane­ously through the control signal LDAC. Signals A0, A1,
WR, and CS select which input latches to update. The
12-bit data is broken down into nibbles (NB); NBL is
the enable signal for the lowest 4 bits, NBM is the
enable for the middle 4 bits, and NBH is the enable for
the highest and most significant 4 bits. Table 2 lists the
address decoding scheme.

Refer to Figure 4 for the MAX530 write-cycle timing
diagram.

Figure 5 shows the circuit configuration for a 4-bit µP
application. Figure 6 shows the corresponding timing
sequence. The 4 low bits (D0-D3) are connected in paral­lel to the other 4 bits (D4-D7) and then to the µP bus.
Address lines A0 and A1 enable the input data latches

V
V

t

IH

IL

DS

DATA BUS

VALID

t

DH

t

LDAC

for the high, middle, or low data nibbles. The µP sends
chip select (CS

) and write (WR) signals to latch in each of

three nibbles in three cycles when the data is valid.
Figure 7 shows a typical interface to an 8-bit or a 16-bit

µP. Connect 8 data bits from the data bus to pins D0-D7
on the MAX530. With LDAC

held high, the user can load
NBH or NBL +NBM in any order. Figure 8a shows the
corresponding timing sequence. For fastest throughput,
use Figure 8b’s sequence. Address lines A0 and A1 are
tied together and the DAC is loaded in 2 cycles as 8 + 4.
In this scheme, with LDAC

held low, the DAC latch is
transparent. Always load NBL and NBM first, followed by
NBH.

is asynchronous with respect to WR. If LDAC is

LDAC
brought low before or at the same time WR

must remain low for at least 50ns to ensure the cor-

LDAC

goes high,

rect data is latched. Data is latched into DAC registers on

’s rising edge.

LDAC

______________________________________________________________________________________ 11

+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC

DATA BUS

D0-D3 D0-D3

FROM

SYSTEM

RESET

MAX530

MC6800

R/W

A0-A15



02

ADDRESS BUS A0, A1

Figure 5. 4-Bit µP Interface

NBH

NBM

NBL

CS

WR

LDAC

Figure 6. 4-Bit µP Timing Sequence

D0-D3

D0-D3
CLR

A0, A1

WR CS

EN

DECODER

A13-A15

A0 = 1, A1 = 1

D4-D7

MAX530

LDAC

A0 = 1, A1 = 0

DATA BUS

D0-D7

FROM

MC6809

R/W

A0-A15

E

ADDRESS BUS

SYSTEM

RESET

CLR

A0-A1

EN

A0

Figure 7. 8-Bit and 16-Bit µP Interface

A0 = 0, A1 = 1

DAC UPDATE

WR

D0-D7

D0-D7

MAX530

CS LDAC

DECODER

A13-A15

NBH

NBL & NBM

CS

WR

LDAC

A0 = A1 = 1

A0 = A1 = 0

DAC UPDATE

Figure 8a. 8-Bit and 16-Bit µP Timing Sequence Using LDAC

12 ______________________________________________________________________________________

+5V, Low-Power, Parallel-Input,

Voltage-Output, 12-Bit DAC

MAX530

NBL & NBM

NBH

CS

WR

LDAC = 0 (DAC LATCH IS TRANSPARENT)

A0 = A1 = 0

Figure 8b. 8-Bit and 16-Bit µP Timing Sequence with LDAC = 0

Unipolar Configuration

The MAX530 is configured for a 0V to +2.048V unipolar
output range by connecting ROFS and RFB to VOUT
(Figure 9). The converter operates from either single or
dual supplies in this configuration. See Table 3 for the
DAC-latch contents (input) vs. the analog VOUT (output).
In this range, 1LSB = REFIN (2



REFIN
REFOUT

33µF

AGND
DGND

REFGND

+5V

V

DD

MAX530

V

SS

0V TO -5V

-12

).

ROFS

RFB

VOUT

G = 1

V

OUT

A0 = A1 = 1

DAC UPDATE

A 0V to 4.096V unipolar output range is set up by con­necting ROFS to AGND and RFB to VOUT (Figure 10).
Table 4 shows the DAC-latch contents vs. VOUT. The
MAX530 operates from either single or dual supplies in
this mode. In this range, 1LSB = (2)(REFIN)(2
(REFIN)(2

-11

).

33µF

REFIN
REFOUT

ROFS
AGND
DGND

REFGND

+5V

V

DD

MAX530

V

SS

0V TO -5V

RFB

VOUT

G = 2

-12

) =

V

OUT

Figure 9. Unipolar Configuration (0V to +2.048V Output) Figure 10. Unipolar Configuration (0V to +4.096V Output)

______________________________________________________________________________________ 13

+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC

Table 3. Unipolar Binary Code Table
(0V to V

MAX530

1111 1111

1000 0000

1000 0000

0111 1111

0000 0000

0000 0000

A -V

REFIN

necting ROFS to REFIN and RFB to VOUT, and operat­ing from dual (±5V) supplies (Figure 11). Table 5
shows the DAC-latch contents (input) vs. VOUT (out­put). In this range, 1 LSB = REFIN (2

The MAX530 can be used as a four-quadrant multiplier
by connecting ROFS to REFIN and RFB to VOUT and,
using (1) an offset binary digital code, (2) bipolar
power supplies, and (3) a bipolar analog input at
REFIN within the range VSS+ 2V to VDD- 2V, as shown
in Figure 12.

In general, a 12-bit DAC’s output is (D)(V
where “G” is the gain (1 or 2) and “D” is the binary rep­resentation of the digital input divided by 212or 4,096.
This formula is precise for unipolar operation. However,
for bipolar, offset binary operation, the MSB is really a
polarity bit. No resolution is lost, because there is the
same number of steps. The output voltage, however,
has been shifted from a range of, for example, 0V to

4.096V (G = 2) to a range of -2.048V to +2.048V.
Keep in mind that when using the DAC as a four-quad-

rant multiplier, the scale is skewed. The negative full
scale is -V

- 1LSB.

Output), Gain = 1

REFIN

(V

(V

(V

REFIN

(V

(V

OUTPUT

REFIN

REFIN

)

REFIN

REFIN

INPUT

1111

0001

0000

1111

0001

0000

Bipolar Configuration

to +V

bipolar range is set up by con-

REFIN

Four-Quadrant Multiplication

, while the positive full scale is +V

REFIN

2048
4096

-11

)

)

)

OV

)

4095
4096

2049
4096

= +V

2047
4096

4096

).

REFIN

1

REFIN



/2

)(G),

REFIN

Table 4. Unipolar Binary Code Table
(0V to 2V

1111 1111

1000 0000

1000 0000

0111 1111

0000 0000

0000 0000

Output), Gain = 2

REFIN

INPUT

1111

0001

0000

1111

0001

0000

+2 (V

+2 (V

+2 (V

+2 (V

+2 (V

OUTPUT

4095

)

REFIN

4096

2049

)

REFIN

4096

2048

)

REFIN

4096

2047

)

REFIN

4096

)

REFIN

4096

OV

= +V

REFIN

1

Table 5. Bipolar (Offset Binary) Code Table
(-V

REFIN

1111 1111

1000 0000

1000 0000

0111 1111

0000 0000

0000 0000

to +V

INPUT

REFIN

1111

0001

0000

1111

0001

0000

Output)

(-V

OUTPUT

(+V

REFIN

(+V

REFIN

REFIN

(-V

REFIN

(-V

REFIN

2047

)

2048

1

)

2048

0V

1

)

2048



2047

)

2048

2048

)

= -V

REFIN

2048

14 ______________________________________________________________________________________

+5V, Low-Power, Parallel-Input,

Voltage-Output, 12-Bit DAC

+5V

REFIN
REFOUT

33µF

Figure 11. Bipolar Configuration (-2.048V to +2.048V Output)

MAX530

AGND
DGND

REFGND

ROFS

RFB

V

VOUT

-5V

OUT

__________Applications Information

As with any amplifier, the MAX530’s output op amp offset
can be positive or negative. When the offset is positive, it
is easily accounted for. However, when the offset is nega­tive, the output cannot follow linearly when there is no
negative supply. In that case, the amplifier output (VOUT)
remains at ground until the DAC voltage is sufficient to
overcome the offset and the output becomes positive.
The resulting transfer function is shown in Figure 13.

Normally, linearity is measured after allowing for zero
error and gain error. Since, in single-supply operation,
the actual value of a negative offset is unknown, it can­not be accounted for during test. In the MAX530, linear­ity and gain error are measured from code 11 to code
4095 (see Note 2 under
output amplifier offset does not affect monotonicity, and
these DACs are guaranteed monotonic starting with
code zero. In dual-supply operation, linearity and gain
error are measured from code 0 to 4095.

Best system performance is obtained with printed cir­cuit boards that use separate analog and digital ground
planes. Wire-wrap boards are not recommended. The
two ground planes should be connected together at the
low-impedance power-supply source.

AGND and REFGND should be connected together,
and then to DGND at the chip. For single-supply appli-

Single-Supply Linearity

Electrical Characteristics

). The

Power-Supply Bypassing

and Ground Management

+5V

V

DD

REFIN

REFGND

MAX530

AGND

DGND

Figure 12. Four-Quadrant Multiplying Circuit

cations, connect V

to AGND at the chip. The best

SS

ROFS

RFB

VOUT

V

SS

-5V

REFIN

V

OUT

ground connection may be achieved by connecting
the AGND, REFGND, and DGND pins together and
connecting that point to the system analog ground
plane. If DGND is connected to the system digital
ground, digital noise may get through to the DAC’s ana­log portion.

Bypass VDD(and VSSin dual-supply mode) with a

0.1µF ceramic capacitor connected between VDDand
AGND (and between VSSand AGND). Mount the
capacitors with short leads close to the device.

AC Considerations

Digital Feedthrough

High-speed data at any of the digital input pins may
couple through the DAC package and cause internal
stray capacitance to appear as noise at the DAC out­put, even though LDAC and CS are held high (see

Typical Operating Characteristics

). This digital
feedthrough is tested by holding LDAC and CS high
and toggling the data inputs from all 1s to all 0s.

Analog Feedthrough

Because of internal stray capacitance, higher-frequen­cy analog input signals at REFIN may couple to the
output, even when the input digital code is all 0s, as
shown in the

Typical Operating Characteristics

graph
Analog Feedthrough vs. Frequency. It is tested by set­ting CLR to low (which sets the DAC latches to all 0s)
and sweeping REFIN.

MAX530

______________________________________________________________________________________ 15

+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC

___________________Chip Topography

POSITIVE OFFSET

D3/D11

D4

D2/D10

D1/D9

D0/D8

V

DD

RFB

ROFS

MAX530

4

OUTPUT (LSBs)

3
2
1
0

12345678

NEGATIVE OFFSET

DAC CODE (LSBs)

Figure 13. Single-Supply DAC Transfer Function

_Ordering Information (continued)

PIN-PACKAGETEMP. RANGEPART

24 Narrow Plastic DIP-40°C to +85°CMAX530AENG
24 Narrow Plastic DIP-40°C to +85°CMAX530BENG
24 Wide SO-40°C to +85°CMAX530AEWG
24 Wide SO-40°C to +85°CMAX530BEWG
24 SSOP-40°C to +85°CMAX530AEAG

ERROR

(LSB)

1

/

±

2

±1

1

/

±

2

±1

1

/

±

2

±124 SSOP-40°C to +85°CMAX530BEAG

D5
D6

D7
A0

A1

WR

DGND

CS

(2.210mm)

REFIN

0.087"

AGND

TRANSISTOR COUNT: 913;
SUBSTRATE CONNECTED TO V

CLR

DD

VOUT

0.133"

(3.378mm)

V

SS

REFOUT

REFGND
LDAC

.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

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© 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.