Rainbow Electronics MAX5295 User Manual
General Description
The MAX5290–MAX5295 dual, 12-/10-/8-bit, voltageoutput digital-to-analog converters (DACs) offer
buffered outputs and a 3µs maximum settling time at
the 12-bit level. The DACs operate from a 2.7V to 3.6V
analog supply and a separate 1.8V to 3.6V digital supply. The 20MHz 3-wire serial interface is compatible
with SPI™, QSPI™, MICROWIRE™, and digital signal
processor (DSP) protocol applications. Multiple devices
can share a common serial interface in direct access or
daisy-chained configuration. The MAX5290–MAX5295
provide two multifunctional, user-programmable, digital
I/O ports. The externally selectable power-up states of
the DAC outputs are either zero scale, midscale, or full
scale. Software-selectable FAST and SLOW settling
modes decrease settling time in FAST mode, or reduce
supply current in SLOW mode.
The MAX5290/MAX5291 are 12-bit DACs, the MAX5292/
MAX5293 are 10-bit DACs, and the MAX5294/MAX5295
are 8-bit DACs. The MAX5290/ MAX5292/MAX5294 provide unity-gain-configured output buffers, while the
MAX5291/MAX5293/MAX5295 provide force-sense-configured output buffers. The MAX5290– MAX5295 are
specified over the extended -40°C to +85°C temperature
range, and are available in space-saving 4mm x 4mm,
16-pin thin QFN and 6.5mm x 5mm, 14-pin and 16-pin
TSSOP packages.
Applications
Portable Instrumentation
Automatic Test Equipment (ATE)
Digital Offset and Gain Adjustment
Automatic Tuning
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Controls
Motion Control
Microprocessor (µP)-Controlled Systems
Power Amplifier Control
Fast Parallel-DAC to Serial-DAC Upgrades
Features
♦ Dual, 12-/10-/8-Bit Serial DACs in 4mm x 4mm
Thin QFN and TSSOP Packages
♦ 3µs (max) 12-Bit Settling Time to 1/2 LSB
♦ Integral Nonlinearity
1 LSB (max) MAX5290/MAX5291 A-Grade (12-Bit)
1 LSB (max) MAX5292/MAX5293 (10-Bit)
1/2 LSB (max) MAX5294/MAX5295 (8-Bit)
♦ Guaranteed Monotonic, ±1 LSB (max) DNL
♦ Two User-Programmable Digital I/O Ports
♦ Single +2.7V to +3.6V Analog Supply
♦ +1.8V to AV
DD
Digital Supply
♦ 20MHz 3-Wire SPI-/QSPI-/MICROWIRE- and
DSP-Compatible Serial Interface
♦ Glitch-Free Outputs Power Up to Zero Scale,
Midscale or Full Scale
♦ Unity-Gain- or Force-Sense-Configured Output
Buffers
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3005; Rev 0; 11/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*Future product—contact factory for availability. Specifications
are preliminary.
**EP = Exposed paddle.
Selector Guide and Pin Configurations appear at end of data
sheet.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PART TEMP RANGE PIN-PACKAGE
MAX5290AEUD* -40°C to +85°C 14 TSSOP
MAX5290BEUD -40°C to +85°C 14 TSSOP
MAX5290AETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5290BETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5291AEUE* -40°C to +85°C 16 TSSOP
MAX5291BEUE -40°C to +85°C 16 TSSOP
MAX5291AETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5291BETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5292EUD -40°C to +85°C 14 TSSOP
MAX5292ETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5293EUE -40°C to +85°C 16 TSSOP
MAX5293ETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5294EUD -40°C to +85°C 14 TSSOP
MAX5294ETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5295EUE -40°C to +85°C 16 TSSOP
MAX5295ETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= 2.7V to 3.6V, DVDD= 1.8V to AVDD, AGND = 0, DGND = 0, V
REF
= 2.5V, RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto DVDD........................................................................±6V
AGND to DGND ..................................................................±0.3V
AV
DD
to AGND, DGND.............................................-0.3V to +6V
DV
DD
to AGND, DGND ............................................-0.3V to +6V
FB_, OUT_,
REF to AGND........-0.3V to the lower of (AV
DD
+ 0.3V) or +6V
SCLK, DIN, CS, PU,
DSP to DGND .......-0.3V to the lower of (DV
DD
+ 0.3V) or +6V
UPIO1, UPIO2
to DGND ...............-0.3V to the lower of (DV
DD
+ 0.3V) or +6V
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
14-Pin TSSOP (derate 9.1mW/°C above +70°C) .........727mW
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
16-Pin Thin QFN (derate 16.9mW/°C above +70°C) .1349mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY
Integral Nonlinearity INL
Differential Nonlinearity DNL Guaranteed monotonic (Note 2) ±1 LSB
Offset Error V
Offset-Error Drift 5
Gain Error GE Full-scale output
Gain-Error Drift 1
OS
MAX5290/MAX5291 12
MAX5292/MAX5293 10Resolution N
MAX5294/MAX5295 8
MAX5290A/MAX5291A (12-bit) ±1
V
= 2.5V at
REF
= 2.7V
AV
DD
(Note 2)
MAX5290A/MAX5291A (12-bit), decimal code = 40 ±5
MAX5290B/MAX5291B (12-bit), decimal code = 82 ±5 ±25
MAX5292/MAX5293 (10-bit), decimal code = 21 ±5 ±25
MAX5294/MAX5295 (8-bit), decimal code = 5 ±5 ±25
MAX5290B/MAX5291B (12-bit) ±2 ±4
MAX5292/MAX5293 (10-bit) ±0.5 ±1
MAX5294/MAX5295 (8-bit) ±0.125 ±0.5
MAX5290A/MAX5291A (12-bit) ±4
MAX5290B/MAX5291B (12-bit) ±10 ±20
MAX5292/MAX5293 (10-bit) ±3 ±5
MAX5294/MAX5295 (8-bit) ±0.5 ±2
Bits
LSB
mV
ppm of
FS/°C
LSB
ppm of
FS/°C
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= 2.7V to 3.6V, DVDD= 1.8V to AVDD, AGND = 0, DGND = 0, V
REF
= 2.5V, RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-Supply Rejection
Ratio
REFERENCE INPUT
Reference Input Range V
Reference Input
Resistance
Reference Leakage
Current
DAC OUTPUT CHARACTERISTICS
Output Voltage Noise
Output Voltage Range
(Note 4)
DC Output Impedance 38 Ω
Short-Circuit Current AVDD = 3V, OUT_ to AGND, full scale, FAST mode 45 mA
Power-Up Time From DVDD applied, interface is functional 30 60 µs
Wake-Up Time Coming out of shutdown, outputs settled 40 µs
Output OUT_ and FB_
Open-Circuit Leakage
Current
DIGITAL OUTPUTS (UPIO_)
Output High Voltage V
Output Low Voltage V
DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
Input Capacitance C
PSRR Full-scale output, AV
REF
R
REF
I
REF
OH
OL
IH
IL
IN
IN
= 2.7V to 3.6V 200 µV/V
DD
Normal operation (no code dependence) 145 200 kΩ
Shutdown mode 0.5 1 µA
SLOW mode,
full scale
FAST mode,
full scale
Unity-gain output 0 AV
Force-sense output 0 AV
Programmed in shutdown mode, force-sense
outputs only
I
I
2.7V ≤ DVDD ≤ 3.6V 2.4
DVDD < 2.7V
2.7V ≤ DVDD ≤ 3.6V 0.6
DVDD < 2.7V 0.2
= 2mA
SOURCE
= 2mA 0.4 V
SINK
Unity gain 85
Force sense 67
Unity gain 140
Force sense 110
0.25 AV
-
DV
DD
0.5
0.7 x
DV
DD
DD
DD
/ 2
µV
DD
0.01 µA
±0.1 ±1 µA
10 pF
V
RMS
V
V
V
V
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= 2.7V to 3.6V, DVDD= 1.8V to AVDD, AGND = 0, DGND = 0, V
REF
= 2.5V, RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PU INPUT
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
DYNAMIC PERFORMANCE
Voltage-Output Slew
Rate
IH-PU
IL-PU
IN-PU
SR
Voltage-Output Settling
Time (Note 5)
FB_ Input Voltage 0V
FB_ Input Current 0.1 µA
Reference -3dB
Bandwidth (Note 6)
Digital Feedthrough
Digital-to-Analog Glitch
Impulse
DAC-to-DAC Crosstalk (Note 3) 15 nV-s
PU still considered floating when connected to a
tri-state bus
Fast mode 3.6
Slow mode 1.6
M AX 5290/M AX 5291 fr om cod e 322 to
cod e 4095 to 1/2 LS B
FAST mode
SLOW mode
Unity gain 200
Force sense 150
CS = DV
from 0 to DV
Major carry transition 2 nV-s
M AX 5292/M AX 5293 fr om cod e 82 to
cod e 1023 to 1/2 LS B
MAX5294/MAX5295 from code 21 to
code 255 to 1/2 LSB
M AX 5290/M AX 5291 fr om cod e 322 to
cod e 4095 to 1/2 LS B
MAX5292/MAX5293 from code 82 to
code 1023 to 1/2 LSB
MAX5294/MAX5295 from code 21 to
code 255 to 1/2 LSB
, code = zero scale, any digital input
DD
and DVDD to 0, f = 100kHz
DD
DVDD 200mV
200 mV
±200 nA
23
1.5 3
12
36
2.5 6
24
REF
0.1 nV-s
V/µs
/ 2 V
kHz
V
µs
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= 2.7V to 3.6V, DVDD= 1.8V to AVDD, AGND = 0, DGND = 0, V
REF
= 2.5V, RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage
Range
AV
DD
2.7 3.6 V
Digital Supply Voltage
Range
DV
DD
1.8
V
Unity gain
0.8 µA
SLOW mode, all digital inputs
at DGND or DV
DD
, no load,
V
REF
= 2.5V
Force sense 0.9 1.2 mA
Unity gain
2
Operating Supply
Current
I
AVDD
+
I
DVDD
FAST mode, all digital inputs
at DGND or DV
DD
, no load,
V
REF
= 2.5V
Force sense 1.2 2
mA
Shutdown Supply
Current
I
AV D D ( S H D N )
+
No clocks, all digital inputs at DGND or DVDD, all
DACs in shutdown mode
2.5 µA
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V Logic) (Figure 1)
(DVDD= 2.7V to 3.6V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
I
D V D D ( S H D N )
0.55
0.85
AV
DD
SCLK Frequency f
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall to SCLK Rise Setup Time t
SCLK Rise to CS Rise Hold Time t
SCLK Rise to CS Fall Setup Time t
DIN to SCLK Rise Setup Time t
DIN to SCLK Rise Hold Time t
SCLK Rise to DOUTDC1 Valid
Propagation Delay
SCLK Fall to DOUT_ Valid
Propagation Delay
CS Rise to SCLK Rise Hold Time t
CS Pulse-Width High t
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK
CH
CL
CSS
CSH
CS0
DS
DH
t
DO1
t
DO2
CS1
CSW
2.7V < DVDD < 3.6V 20 MHz
(Note 7) 20 ns
(Note 7) 20 ns
10 ns
5ns
10 ns
12 ns
CL = 20pF, UPIO_ = DOUTDC1 mode 30 ns
CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode
MICROWIRE and SPI modes 0 and 3 10 ns
5ns
30 ns
45 ns
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V Logic) (Figure 1) (continued)
(DVDD= 2.7V to 3.6V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)
(DVDD= 1.8V to 3.6V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
UPIO TIMING CHARACTERISTICS
DOUT Tri-State Time when Exiting
DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
t
DOZ
CL = 20pF, from end of write cycle to UPIO_
in high impedance
100 ns
DOUTRB Tri-State Time from CS
Rise
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
LDAC Pulse-Width Low t
LDAC Effective Delay t
CLR, MID, SET Pulse-Width Low t
GPO Output Settling Time t
GPO Output High-Impedance
Time
t
DRBZ
t
ZEN
LDL
LDS
CMS
GP
t
GPZ
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
CL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state
Figure 5 20 ns
Figure 6 100 ns
Figure 5 20 ns
Figure 6 100 ns
SCLK Frequency f
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall to SCLK Rise Setup Time t
SCLK Rise to CS Rise Hold Time t
SCLK Rise to CS Fall Setup Time t
DIN to SCLK Rise Setup Time t
DIN to SCLK Rise Hold Time t
SCLK Rise to DOUTDC1 Valid
Propagation Delay
SCLK Fall to DOUT_ Valid
Propagation Delay
CS Rise to SCLK Rise Hold Time t
CS Pulse-Width High t
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK
CH
CL
CSS
CSH
CS0
DS
DH
t
DO1
t
DO2
CS1
CSW
1.8V < DVDD < 3.6V 10 MHz
(Note 7) 40 ns
(Note 7) 40 ns
20 ns
0ns
10 ns
20 ns
5ns
CL = 20pF, UPIO_ = DOUTDC1 mode 60 ns
CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode
MICROWIRE and SPI modes 0 and 3 20 ns
90 ns
20 ns
20 ns
100 ns
60 ns
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 7
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1) (continued)
(DVDD= 1.8V to 3.6V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V Logic) (Figure 2)
(DVDD= 2.7V to 3.6V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
DOUTRB Tri-State Time from CS
Rise
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
LDAC Pulse-Width Low t
LDAC Effective Delay t
CLR, MID, SET Pulse-Width Low t
GPO Output Settling Time t
GPO Output High-Impedance
Time
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
t
DOZ
t
DRBZ
t
ZEN
LDL
LDS
CMS
GP
t
GPZ
CL = 20pF, from end of write cycle to UPIO_
in high impedance
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
CL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state
Figure 5 40 ns
Figure 6 200 ns
Figure 5 40 ns
Figure 6 200 ns
200 ns
40 ns
40 ns
200 ns
SCLK Frequency f
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall to SCLK Fall Setup Time t
DSP Fall to SCLK Fall Setup Time t
SCLK Fall to CS Rise Hold Time t
SCLK Fall to CS Fall Delay t
SCLK Fall to DSP Fall Delay t
DIN to SCLK Fall Setup Time t
DIN to SCLK Fall Hold Time t
SCLK Rise to DOUT_ Valid
Propagation Delay
SCLK Fall to DOUTDC0 Valid
Propagation Delay
CS Rise to SCLK Fall Hold Time t
CS Pulse-Width High t
DSP Pulse-Width High t
DSP Pulse-Width Low t
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK
CH
CL
CSS
DSS
CSH
CS0
DS0
DS
DH
t
DO1
t
DO2
CS1
CSW
DSW
DSPWL
2.7V < DVDD < 3.6V 20 MHz
(Note 7) 20 ns
(Note 7) 20 ns
10 ns
10 ns
5ns
10 ns
10 ns
12 ns
5ns
CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode
CL = 20pF, UPIO_ = DOUTDC0 mode 30 ns
MICROWIRE and SPI modes 0 and 3 10 ns
45 ns
20 ns
(Note 8) 20 ns
30 ns
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
8 _______________________________________________________________________________________
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V Logic) (Figure 2) (continued)
(DVDD= 2.7V to 3.6V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)
(DVDD= 1.8V to 3.6V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
t
DOZ
CL = 20pF, from end of write cycle to UPIO_
in high impedance
100 ns
DOUTRB Tri-State Time from CS
Rise
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
LDAC Pulse-Width Low t
LDAC Effective Delay t
CLR, MID, SET Pulse-Width Low t
GPO Output Settling Time t
GPO Output High-Impedance
Time
t
DRBZ
t
ZEN
LDL
LDS
CMS
GP
t
GPZ
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
CL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state
Figure 5 20 ns
Figure 6 100 ns
Figure 5 20 ns
Figure 6 100 ns
SCLK Frequency f
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall to SCLK Fall Setup Time t
DSP Fall to SCLK Fall Setup Time t
SCLK Fall to CS Rise Hold Time t
SCLK Fall to CS Fall Delay t
SCLK Fall to DSP Fall Delay t
DIN to SCLK Fall Setup Time t
DIN to SCLK Fall Hold Time t
SCLK Rise to DOUT_ Valid
Propagation Delay
SCLK Fall to DOUTDC0 Valid
Propagation Delay
CS Rise to SCLK Fall Hold Time t
CS Pulse-Width High t
DSP Pulse-Width High t
DSP Pulse-Width Low
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK
CH
CL
CSS
DSS
CSH
CS0
DS0
DS
DH
t
DO1
t
DO2
CS1
CSW
DSW
t
DSPWL (Note 8)
1.8V < DVDD < 3.6V 10 MHz
(Note 7) 40 ns
(Note 7) 40 ns
CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode
CL = 20pF, UPIO_ = DOUTDC0 mode 60 ns
MICROWIRE and SPI modes 0 and 3 20 ns
20 ns
20 ns
10 ns
15 ns
20 ns
90 ns
40 ns
40 ns
20 ns
20 ns
100 ns
0ns
5ns
60 ns
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 9
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2) (continued)
(DVDD= 1.8V to 3.6V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1: For the force-sense versions, FB_ is connected to its respective OUT_. V
OUT
(max) = V
REF
/ 2, unless otherwise noted.
Note 2: Linearity guaranteed from decimal code 82 to 4095 for the MAX5290B/MAX5291B (12-bit, B-grade), code 21 to 1023 for the
MAX5292/MAX5293 (10-bit), and code 5 to 255 for the MAX5294/MAX5295 (8-bit).
Note 3: DAC-to-DAC crosstalk is measured as follows: outputs of DACA and DACB are set to full scale and the output of DACB is
measured. While keeping DACB unchanged, the output of DACA is transitioned to zero scale and the ∆V
OUT
of DACB is
measured. The procedure is repeated with DACA and DACB interchanged. DAC-to-DAC crosstalk is the maximum ∆V
OUT
measured.
Note 4: Represents the functional range. The linearity is guaranteed at V
REF
= 2.5V. See the Typical Operating Characteristics sec-
tion for linearity at other voltages.
Note 5: Guaranteed by design.
Note 6: The reference -3dB bandwidth is measured with a 0.1V
P-P
sine wave on V
REF
and with the input code at full scale.
Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-
lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns
(2.7V) or 50ns (1.8V).
Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low
and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of
operation.
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO_ Modes
DOUTRB Tri-State Time from CS
Rise
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
LDAC Pulse-Width Low t
LDAC Effective Delay t
CLR, MID, SET Pulse-Width Low t
GPO Output Settling Time t
GPO Output High-Impedance
Time
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
t
DOZ
t
DRBZ
t
ZEN
LDL
LDS
CMS
GP
t
GPZ
CL = 20pF, from end of write cycle to UPIO_
in high impedance
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
CL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state
Figure 5 40 ns
Figure 6 200 ns
Figure 5 40 ns
Figure 6 200 ns
200 ns
40 ns
40 ns
200 ns
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
10 ______________________________________________________________________________________
Typical Operating Characteristics
(AVDD= DVDD= 3V, V
REF
= 2.5V, RL= 10kΩ, CL= 100pF, speed mode = FAST, PU = floating, TA= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
4
UNITY GAIN
B-GRADE
3
2
1
0
INL (LSB)
-1
-2
-3
-4
0 4096
DIGITAL INPUT CODE
307220481024
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
0.50
UNITY GAIN
0.25
0
INL (LSB)
-0.25
MAX5290 toc01
MAX5290 toc03
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
1.00
UNITY GAIN
0.75
0.50
0.25
0
INL (LSB)
-0.25
-0.50
-0.75
-1.00
0 1024
DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
0.2
UNITY GAIN
B-GRADE
0.1
0
DNL (LSB)
-0.1
MAX5290 toc02
768512256
MAX5290 toc04
-0.50
0 256
DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
0.050
UNITY GAIN
0.025
0
DNL (LSB)
-0.025
-0.050
0 1024
DIGITAL INPUT CODE
19212864
MAX5290 toc05
768512256
-0.2
0 4096
DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
0.02
UNITY GAIN
0.01
0
DNL (LSB)
-0.01
-0.02
0 256
DIGITAL INPUT CODE
307220481024
19212864
MAX5290 toc06
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