Rainbow Electronics MAX5259 User Manual
General Description
The MAX5258/MAX5259 are +3V/+5V single-supply,
digital serial-input, voltage-output, 8-bit octal digital-toanalog converters (DACs). Internal precision buffers
swing Rail-to-Rail®, and the reference input range
extends from ground to the positive supply. The +5V
(MAX5258) and the +3V (MAX5259) feature a 10µA
(max) shutdown mode.
The serial interface is double-buffered. A 16-bit input
shift register is followed by eight 8-bit input registers
and eight 8-bit DAC registers. The 16-bit serial word
consists of two “don’t care” bits, three address bits,
three control bits, and eight data bits. The input and
DAC registers can both be updated independently or
simultaneously with a single software command. The
asynchronous control input (LDAC) provides simultaneous updating of all eight DAC registers.
The interface is compatible with SPI™, QSPI™ (CPOL =
CPHA = 0 or CPOL = CPHA = 1), and MICROWIRE™.
A buffered digital data output allows daisy-chaining of
serial devices.
The MAX5258/MAX5259 are available in a 16-pin QSOP
package.
________________________Applications
Digital Gain and Offset Adjustment
Programmable Attenuators
Programmable Current Sources
Portable Instruments
Features
♦ +2.7V to +5.5V Single-Supply Operation
♦ Low Supply Current: 1.3mA
♦ Low-Power Shutdown Mode
0.54mA (MAX5259)
0.80mA (MAX5258)
♦ ±1LSB DNL (max)
♦ ±1LSB INL (max)
♦ Ground to V
DD
Reference Input Range
♦ Output Buffer Amplifiers Swing Rail-to-Rail
♦ 10MHz Serial Interface, SPI, QSPI (CPOL = CPHA
= 0 or CPOL = CPHA = 1), and MICROWIRECompatible
♦ Double-Buffered Registers for Synchronous
Updating
♦ Serial Data Output for Daisy-Chaining
♦ Ultra-Small 16-Pin QSOP Package
+3V/+5V, Low-Power, 8-Bit Octal DACs
with Rail-to-Rail Output Buffers
________________________________________________________________ Maxim Integrated Products 1
Pin Configuration
19-1844; Rev 1; 4/01
Ordering Information
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
MAX5258/MAX5259
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP. RANGE PIN- PACK AGE
o
MAX5258EEE -40
MAX5259EEE -40oC to +85oC 16 QSOP +3.0
C to +85oC 16 QSOP +5.0
SU PPL Y
VO LT A G E
( V)
TOP VIEW
1
OUTB OUTC
OUTA
2
GND
3
MAX5258
4
V
DD
REF
LDAC
OUTE
OUTF
MAX5259
5
6
7
8
QSOP
16
15
OUTD
14
DOUT
13
DIN
SCLK
12
CS
11
10
OUTH
9
OUTG
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (MAX5258)
(VDD= +4.5V to +5.5V, V
REF
= +4.096V, GND = 0, RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at V
DD
= +5V and TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
DIN, DOUT, CS, SCLK, LDAC to GND.....................-0.3V to +6V
REF to GND................................................-0.3V to (V
DD
+ 0.3V)
OUT_ to GND ...........................................................-0.3V to V
DD
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T
A
= +70°C)
16-Pin Plastic QSOP (derate 8.3mW/°C about +70°C)...667mW
Operating Temperature Range ..........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
CONDITIONS
UNITS
STATIC ACCURACY
Resolution 8 Bits
Integral Nonlinearity (Note 1) INL
±1
LSB
Differential Nonlinearity (Note 1) DNL Guaranteed monotonic (all codes)
±1
LSB
Zero-Code Error ZCE Code = 0A hex
mV
Zero-Code Error Supply
Rejection
Code = 0A hex
1
LSB
Zero-Code Temperature
Coefficient
Code = 0A hex
µV/oC
Full-Scale Error Code = FF hex ±1
mV
Full-Scale Error Supply Rejection
Code = FF hex
1
LSB
Full-Scale Temperature
Coefficient
Code = FF hex
µV/oC
REFERENCE INPUTS
Input Voltage Range 0
V
Input Resistance
kΩ
Input Capacitance 20 pF
DAC OUTPUTS
Output Voltage Swing RL = 10kΩ to GND 0
V
DD
-
0.3
V
Output Voltage Range RL = 10kΩ to GND 0
V
DIGITAL INPUTS
Input High Voltage V
IH
V
Input Low Voltage V
IL
V
SYMBOL
MIN TYP MAX
161 230 300
0.7
V
✕
DD
±0.1
±0.05
±2.5 ±20
0.02
±10
0.25
±10
±30
V
V
REF
0.3
V
DD
✕
DD
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (MAX5258) (continued)
(VDD= +4.5V to +5.5V, V
REF
= +4.096V, GND = 0, RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at V
DD
= +5V and TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Current I
IN
VIN = 0 to V
DD
µA
Input Capacitance C
IN
(Note 3) 10 pF
DIGITAL OUTPUTS
Output High Voltage V
OH
I
SOURCE
= 0.2mA
V
DD
-
0.5
V
Output Low Voltage V
OL
I
SINK
= 1.6mA 0.4 V
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate Code = FF hex
V/µs
Output Settling Time
To 1/2 LSB, from code 0A to code FF hex
(Note 2)
10 µs
Digital Feedthrough Code = 00 hex
nV-s
Digital-to-Analog Glitch Impulse Code = 80 to code = 7F hex 30
nV-s
V
REF
= 4V
p-p
at 1kHz centered at 2.5V
code = FF hex
68
Signal-to-Noise Plus Distortion
Ratio
V
REF
= 4V
p-p
at 10kHz centered at 2.5V
code = FF hex
55
dB
Multiplying Bandwidth
V
REF
= 0.1V
p-p
centered at VDD/2, -3dB
bandwidth
kHz
Wideband Amplifier Noise 16 µV
POWER REQUIREMENTS
Power-Supply Voltage V
DD
4.5 5.5 V
Supply Current I
DD
1.4 2.6 mA
Shutdown Supply Current
10 µA
SINAD
±1.0
0.55
0.15
700
I
SHDN
0.45
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (MAX5259)
(VDD= +2.7V to +3.3V, V
REF
= +2.5V, GND = 0, RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at V
DD
= +3V, and TA= +25°C.)
STATIC ACCURACY
Resolution 8 Bits
Integral Non Linearity (Note 1) INL ±0.1 ±1 LSB
Differential Non Linearity (Note 1) DNL Guaranteed monotonic (all codes) ±0.1 ±1 LSB
Zero-Code Error ZCE Code = 0A hex ±2.5 ±20 mV
Zero-Code Error Supply
Rejection
Zero-Code Temperature
Coefficient
Full-Scale Error Code = FF hex ±0.7 ±30 mV
Full-Scale Error Supply Rejection Code = FF hex 0.2 1 LSB
Full-Scale Temperature
Coefficient
REFERENCE INPUTS
Input Voltage Range 0V
Input Resistance 161 218 300 kΩ
Input Capacitance 20 pF
DAC OUTPUTS
Output Voltage Swing RL = 10kΩto GND 0
Output Voltage Range RL = 10kΩ to GND 0 V
DIGITAL INPUTS
Input High Voltage V
Input Low Voltage V
Input Current I
Input Capacitance C
DIGITAL OUTPUTS
Output High Voltage V
Output Low Voltage V
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate Code = FF hex 0.55 V/µs
Output Settling Time
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Code = 0A hex. 0.15 1 LSB
Code = 0A hex ±10 µV/
Code = FF hex ±10 µV/
IH
IL
VIN = 0 to V
IN
(Note 3) 10 pF
IN
I
OH
OL
SOURCE
I
SINK
To 1/2 LSB, from code 0A to code FF hex
(Note 2)
DD
= 0.2mA
= 1.6mA 0.4 V
0.7 x
V
DD
V
–
DD
0.5
7 µs
DD
V
–
DD
0.3
REF
0.3 x
V
DD
±1.0 µA
o
C
o
C
V
V
V
V
V
V
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (MAX5259) (continued)
(VDD= +2.7V to +3.3V, V
REF
= +2.5V, GND = 0, RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at V
DD
= +3V, and TA= +25°C.)
TIMING CHARACTERISTICS (MAX5258)
(V
REF
= +4.096V, GND = 0, C
DOUT
= 100pF, TA= T
MIN
to TMAX, unless otherwise noted. Typical values are at V
DD
= +5V and
T
A
= +25°C.)
Digital Feedthrough
Digital-to-Analog Glitch Impulse Code = 80 to code = 7F hex 20 nV-S
Signal-to-Noise Plus Distortion
Ratio
Multiplying Bandwidth
Wideband Amplifier Noise 60 µV
POWER REQUIREMENTS
Power-Supply Voltage V
Supply Current I
Shutdown Supply Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Code = 00 hex
V
SINAD
DD
DD
SHDN
= 2.5V
REF
code = FF hex
V
= 2.5V
REF
code = FF hex
V
= 0.1V
REF
bandwidth
at 1kHz centered at 1.5V
p-p
at 10kHz centered at 1.5V
p-p
centered at VDD/2, -3dB
p-p
0.1 nV-s
65
54
700 kHz
2.7 3.6 V
1.3 2.6 mA
0.24 10 µA
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDD Rise-to-CS Fall-Setup Time t
LDAC Pulse Width Low t
CS Rise-to-LDAC Fall-Setup Time
(Note 4)
CS Pulse Width High t
SCLK Clock Frequency (Note 5) f
SCLK Pulse Width High t
SCLK Pulse Width Low t
CS Fall-to-SCLK Rise-Setup Time t
SCLK Rise-to-CS Rise-Hold Time t
DIN to SCLK Rise-to-Setup Time t
DIN to SCLK Rise-to-Hold Time t
SCLK Rise-to-DOUT Valid
Propagation Delay (Note 6)
SCLK Fall-to-DOUT Valid
Propagation Delay (Note 7)
CS Rise-to-SCLK Rise-Setup
Time
VDCS
LDAC
t
CLL
CSW
CLK
CH
CL
CSS
CSH
DS
DH
t
DO1
t
DO2
t
CS1
40 20 ns
40 ns
90 ns
40 ns
40 ns
40 ns
0ns
40 ns
0ns
40 ns
5 µs
10 MHz
200 ns
210 ns
dB
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS (MAX5259)
(V
REF
= +2.5V, GND = 0, C
DOUT
= 100pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at VDD= +3V and
T
A
= +25°C.)
Note 1: INL and DNL are measured with RLreferenced to ground. Nonlinearity is measured from the first code that is greater than or
equal to the maximum offset specification to code FF hex (full scale). (See DAC Linearity and Voltage Offset section.)
Note 2: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of the final value of V
OUT
.
Note 3: Guaranteed by design, not production tested.
Note 4: If LDAC is activated prior to the rising edge of CS, it must remain low for t
LDAC
or longer after CS goes high.
Note 5: When DOUT is not used. If DOUT is used, f
CLK
(max) is 4MHz due to SCLK to DOUT propagation delay.
Note 6: Serial data is clocked-out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of V
DD
).
Note 7: Serial data is clocked-out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of V
DD
).
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDD Rise-to-CS Fall-Setup Time t
LDAC Pulse Width Low t
CS Rise-to-LDAC Fall-Setup Time
(Note 4)
CS Pulse Width High t
SCLK Clock Frequency (Note 5) f
SCLK Pulse Width High t
SCLK Pulse Width Low t
CS Fall-to-SCLK Rise-Setup Time t
SCLK Rise-to-CS Rise-Hold Time t
DIN to SCLK Rise-to-Setup Time t
DIN to SCLK Rise-to-Hold Time t
SCLK Rise-to-DOUT Valid
Propagation Delay (Note 6)
SCLK Fall-to-DOUT Valid
Propagation Delay (Note 7)
CS Rise-to-SCLK Rise-Setup
Time
VDCS
LDAC
t
CLL
CSW
CLK
CH
CL
CSS
CSH
DS
DH
t
DO1
t
DO2
t
CS1
5 µs
40 20 ns
40 ns
90 ns
10 MHz
40 ns
40 ns
40 ns
0ns
40 ns
0ns
200 ns
210 ns
40 ns
Loading...