Rainbow Electronics MAX5253 User Manual

19-1123; Rev 0; 9/96

+3V, Quad, 12-Bit Voltage-Output DAC

with Serial Interface

__________________General Description

The MAX5253 combines four low-power, voltage-output,
12-bit digital-to-analog converters (DACs) and four pre­cision output amplifiers in a space-saving, 20-pin pack­age. In addition to the four voltage outputs, each
amplifier’s negative input is also available to the user.
This facilitates specific gain configurations, remote
sensing, and high output drive capacity, making the
MAX5253 ideal for industrial-process-control applica­tions. Other features include software shutdown, hard­ware shutdown lockout, an active-low reset which clears
all registers and DACs to zero, a user-programmable
logic output, and a serial-data output.

Each DAC has a double-buffered input organized as an
input register followed by a DAC register. A 16-bit serial
word loads data into each input/DAC register. The serial
interface is compatible with SPI™/QSPI™ and

______________________________Features

♦ Four 12-Bit DACs with Configurable

Output Amplifiers

♦ +3.0V to +3.6V Single-Supply Operation
♦ Low Supply Current: 0.82mA Normal Operation

3µA Shutdown Mode

♦ Reference Inputs are High Impedance in Shutdown
♦ Available in 20-Pin SSOP
♦ Power-On Reset Clears all Registers and

DACs to Zero

♦ SPI/QSPI and Microwire Compatible
♦ Simultaneous or Independent Control of DACs

via 3-Wire Serial Interface

♦ User-Programmable Digital Output

Microwire™. It allows the input and DAC registers to be
updated independently or simultaneously with a single
software command. The DAC registers can be simulta­neously updated via the 3-wire serial interface. All logic
inputs are TTL/CMOS-logic compatible.

________________________Applications

Industrial Process Controls
Automatic Test Equipment
Digital Offset and Gain Adjustment
Motion Control
Remote Industrial Controls
Microprocessor-Controlled Systems

_________________Ordering Information

PART

MAX5253ACPP
MAX5253BCPP 0°C to +70°C
MAX5253ACAP
MAX5253BCAP 0°C to +70°C

Ordering Information continued on last page.

Pin Configuration appears at end of data sheet.

TEMP. RANGE PIN-PACKAGE

0°C to +70°C

0°C to +70°C 20 SSOP

20 Plastic DIP
20 Plastic DIP

20 SSOP

INL

(LSB)

±1/2
±1
±1/2
±1

_________________________________________________________________________Functional Diagram

MAX5253

DOUT

CL

PDL

DGND

DECODE

CONTROL

16-BIT
SHIFT

REGISTER

SR

DIN

LOGIC

OUTPUT

SCLK

UPO REFCD

CONTROL

CS

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

________________________________________________________________

INPUT

REGISTER A

INPUT

REGISTER B

INPUT

REGISTER C

INPUT

REGISTER D

AGND

V

DD

REGISTER A

REGISTER B

REGISTER C

REGISTER D

DAC A

DAC B

DAC C

DAC D

MAX5253

REFAB

DAC A

DAC B

DAC C

DAC D

FBA

OUTA

FBB
OUTB

FBC
OUTC

FBD
OUTD

Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone]

+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface

ABSOLUTE MAXIMUM RATINGS

VDDto AGND...............................................................-0.3V, +6V

to DGND ..............................................................-0.3V, +6V

V

DD

AGND to DGND..................................................................±0.3V

REFAB, REFCD to AGND...........................-0.3V to (V

OUT_, FB_ to AGND...................................-0.3V to (V

Digital Inputs to DGND.............................................-0.3V to +6V

DOUT, UPO to DGND ................................-0.3V to (V

Continuous Current into Any Pin.......................................±20mA

Continuous Power Dissipation (T

MAX5253

Plastic DIP (derate 8.00mW/°C above +70°C).................640mW

SSOP (derate 8.00mW/°C above +70°C) ......................640mW

CERDIP (derate 11.11mW/°C above +70°C).................889mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

= +70°C)

A

DD
DD

DD

+ 0.3V)
+ 0.3V)

+ 0.3V)

ELECTRICAL CHARACTERISTICS

(VDD= +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD = 1.25V, RL= 5kΩ, CL= 100pF, TA= T
noted. Typical values are at T

STATIC PERFORMANCE—ANALOG SECTION

Integral Nonlinearity
(Note 1)

Offset Error

MATCHING PERFORMANCE (TA= +25°C)

REFERENCE INPUT

Reference Input Range
Reference Input Resistance

= +25°C. Output buffer connected in unity-gain configuration (Figure 9).)

A

MAX5253AC/E

INL

MAX5253BC/E
MAX5253BMJP ±2.0
Guaranteed monotonic

OS

VDD= +3.0V to +3.6V

REF

Code-dependent, minimum at code 555 hex

REF

Operating Temperature Ranges

MAX5253_C_P......................................................0°C to +70°C

MAX5253_E_P ...................................................-40°C to +85°C

MAX5253BMJP................................................-55°C to +125°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

to T

MIN

CONDITIONS

±0.25 ±0.5

, unless otherwise

MAX

±1.0

±6.0 mVV

- 1.4V

DD

UNITSMIN TYP MAXSYMBOLPARAMETER

LSB

LSB±1.0DNLDifferential Nonlinearity

ppm/°C6Offset-Error Tempco

LSBGEGain Error (Note 1) ±4.0

ppm/°C1Gain-Error Tempco

µV/VPSRRPower-Supply Rejection Ratio 300

LSB±4.0GEGain Error

LSB±0.35 ±1.0INLIntegral Nonlinearity

Bits12NResolution

mVOffset Error ±1.0 ±6.0

V0V

kΩ10R

2 _______________________________________________________________________________________

+3V, Quad, 12-Bit Voltage-Output DAC

with Serial Interface

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD = 1.25V, RL= 5kΩ, CL= 100pF, TA= T
noted. Typical values are at T

MULTIPLYING-MODE PERFORMANCE

Signal-to-Noise Plus
Distortion Ratio

DIGITAL INPUTS

Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance

DIGITAL OUTPUTS

Output High Voltage
Output Low Voltage

DYNAMIC PERFORMANCE

Output Voltage Swing

OUT_ Leakage Current
in Shutdown

Start-Up Time Exiting
Shutdown Mode

POWER SUPPLIES

Supply Voltage
Supply Current

Note 1: Guaranteed from code 11 to code 4095 in unity-gain configuration.
Note 2: Accuracy is better than 0.5LSB for V
Note 3: Remains operational with supply voltage as low as +2.7V.
Note 4: R

= ∞, digital inputs at DGND or VDD.

L

= +25°C. Output buffer connected in unity-gain configuration (Figure 9).)

A

CONDITIONS

V

= 0.67Vp-p

REF

Input code = all 0s, V
V

= 1Vp-p at 25kHz

REF

IH
IL

VIN= 0V or V

IN

IN

I

SOURCE

OH

I

= 2mA

SINK

OL

To ±1/2LSB, V
Rail to rail (Note 2)

RL= ∞

CS = VDD, DIN = 100kHz

(Note 3)

DD

(Note 4)

DD

(Note 4) µA320Supply Current in Shutdown

= 6mV to VDD- 80mV, guaranteed by PSR test on endpoints.

OUT

DD

= 2mA

STEP

REF

= 1.25V

= 1.6Vp-p at 1kHz dB-84Reference Feedthrough

MIN

to T

MAX

DD

MAX5253

, unless otherwise

UNITSMIN TYP MAXSYMBOLPARAMETER

kHz650Reference -3dB Bandwidth

dB72SINAD

V2.0V
V0.8V

µA0.01 ±0.1I

pF8C

VVDD- 0.5V
V0.13 0.4V

V/µs0.6SRVoltage Output Slew Rate

µs16Output Settling Time

V0 to V

µA0 0.1Current into FB_
µA0.01 ±1

µs20

nV-s5Digital Feedthrough
nV-s5Digital Crosstalk

V3.0 3.6V

mA0.82 0.98I

µA0.01 ±1Reference Current in Shutdown

_______________________________________________________________________________________ 3

+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface

TIMING CHARACTERISTICS

(VDD= +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD =1.25V, RL= 5kΩ, CL= 100pF, TA= T
noted. Typical values are at T

SCLK Clock Period
SCLK Pulse Width High
SCLK Pulse Width Low

MAX5253

CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time

DIN Setup Time
DIN Hold Time
SCLK Rise to DOUT Valid

Propagation Delay
SCLK Fall to DOUT Valid

Propagation Delay
SCLK Rise to CS Fall Delay

CS Rise to SCLK Rise Hold Time
CS Pulse Width High

= +25°C. Output buffer connected in unity-gain configuration (Figure 9).)

A

CONDITIONS

CP
CH
CL

CSS
CSH

DS
DH

t

CL= 200pF

D01

t

CL= 200pF

D02

CS0
CS1

CSW

MIN

to T

MAX

, unless otherwise

UNITSMIN TYP MAXSYMBOLPARAMETER

ns100t
ns40t
ns40t
ns40t

ns0t
ns40t
ns0t

120

ns

120 ns

ns40t
ns40t
ns100t

__________________________________________Typical Operating Characteristics

(V

= +3.3V, TA = +25°C, unless otherwise noted.)

DD

INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE

1

0

-1

-2

INL (LSB)

-3

-4
RL = 5kΩ

-5

0 0.5 1.0 1.5 2.0

REFERENCE VOLTAGE (V)

MAX5253-01

RELATIVE OUTPUT (dB)

2.5

4 _______________________________________________________________________________________

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

0

-4



-8

-12

-16

-20
100 560k 1.12M 1.68M 2.24M 2.8M



REFAB SWEPT 0.67Vp-p
RL = 5kΩ
CL = 100pF

FREQUENCY (Hz)

MAX5253-06

SUPPLY CURRENT

vs. TEMPERATURE

1000

950
900
850
800
750
700
650

SUPPLY CURRENT (µA)

600
550

CODE = FFF hex

500

-55 -40 -20 0 20 40 60 80 125100
TEMPERATURE (°C)



MAX5253-04

+3V, Quad, 12-Bit Voltage-Output DAC

with Serial Interface

____________________________Typical Operating Characteristics (continued)

(V

= +3.3V, TA = +25°C, unless otherwise noted.)

DD



SUPPLY CURRENT

1000

950
900
850
800
750
700
650

SUPPLY CURRENT (µA)

600
550
500

vs. SUPPLY VOLTAGE

CODE = FFF hex

2.7 2.8 3.02.9 3.1 3.2 3.3 3.4 3.6
SUPPLY VOLTAGE (V)

0

-1

-2

-3

-4

-5

-6

-7

FULL-SCALE ERROR (LSB)

-8

-9

-10

0.01 0.1 1 10 100

MAX5253-05

THD + NOISE (%)

3.5

FULL-SCALE ERROR

vs. LOAD

LOAD (kΩ)

TOTAL HARMONIC DISTORTION

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05
0

PLUS NOISE vs. LOAD

DAC CODE = ALL 1s
REFAB = 1Vp-p

= 5kΩ

R

L

= 100pF

C

L

0.1 1 10 100
FREQUENCY (kHz)

MAX5253-03

SIGNAL AMPLITUDE (dB)

-100

MAX5253-02

SIGNAL AMPLITUDE (dB)

REFERENCE FEEDTHROUGH

0

-20

-40

-60

-80

0.5 1.2 2.6

AT 1kHz

REFAB INPUT SIGNAL

OUTA FEEDTHROUGH

1.9 3.3 4.0

FREQUENCY (kHz)

0

-20

-40

-60

-80

-100

0.5 1.6 3.8

V

= 1.6Vp-p @ 1kHz

REF

= 5kΩ

R

L

= 100pF

C

L

V
R
C

FREQUENCY (kHz)

OUTPUT FFT PLOT



= 1kHz, 0.006V TO 1.6V

REF

= 5kΩ

L

= 100pF

L

2.7 4.9 6.0

MAX5253-11

MAX5253

MAX5253-10

_______________________________________________________________________________________

5

+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface

____________________________Typical Operating Characteristics (continued)

(V

= +3.3V, TA = +25°C, unless otherwise noted.)

DD

MAJOR-CARRY TRANSITION

MAX5253

V

= 1.25V, RL = 5kΩ, CL = 100pF

REF

GND

V

= 1.25V, RL = 5kΩ, CL = 100pF

REF

DAC A CODE SWITCHING FROM 00B hex TO FFF hex
DAC B CODE SET TO 800 hex

10µs/div

ANALOG CROSSTALK

10µs/div

MAX5253-07

MAX5253-12

CS
5V/div

OUTB,
AC COUPLED
50mV/div

OUTA, 
500mV/div

OUTB,
AC COUPLED
10mV/div

DIGITAL FEEDTHROUGH (SCLK = 100kHz)

2µs/div

V

= 1.25V, RL = 5kΩ, CL = 100pF

REF

CS = PDL = C

L = 3.3V, DIN = 0V

DAC A CODE SET TO 800 hex

DYNAMIC RESPONSE

10µs/div

V

= 1.25V, RL = 5kΩ, CL = 100pF

REF

SWITCHING FROM CODE 000 hex TO FB4 hex
OUTPUT AMPLIFIER GAIN = +2.6

MAX5253-08

MAX5253-13

SCLK,
2V/div

OUTA,
AC COUPLED
10mV/div



OUTA, 
500mV/div

6 _______________________________________________________________________________________

+3V, Quad, 12-Bit Voltage-Output DAC

with Serial Interface

______________________________________________________________Pin Description

PIN

14

20

Analog GroundAGND1
DAC A Output Amplifier FeedbackFBA2
DAC A Output VoltageOUTA3
DAC B Output VoltageOUTB4
DAC B Output Amplifier FeedbackFBB5

Reference Voltage Input for DAC A and DAC BREFAB6

7
8

CL

CS

PDL

DD

Clears All DACs and Registers. Resets all outputs (OUT_, UPO, DOUT) to 0, active low.
Chip-Select Input. Active low.

Serial-Data InputDIN9
Serial Clock InputSCLK10

Digital GroundDGND11
Serial-Data OutputDOUT12
User-Programmable Logic OutputUPO13
Power-Down Lockout. Active low. Locks out software shutdown if low.
Reference Voltage Input for DAC C and DAC DREFCD15
DAC C Output Amplifier FeedbackFBC16
DAC C Output VoltageOUTC17
DAC D Output VoltageOUTD18
DAC D Output Amplifier FeedbackFBD19
Positive Power SupplyV

FUNCTIONNAME

MAX5253

_______________________________________________________________________________________ 7

+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface

The impedance at each reference input is code-depen­dent, ranging from a low value of 10kΩ when both
DACs connected to the reference have an input code
of 555 hex, to a high value exceeding several gigohms
(leakage current) with an input code of 000 hex. Because
the input impedance at the reference pins is code­dependent, load regulation of the reference source is
important.

The REFAB and REFCD reference inputs have a 10kΩ
guaranteed minimum input impedance. When the two
reference inputs are driven from the same source, the
effective minimum impedance is 5kΩ. Driving the
REFAB and REFCD pins separately improves reference
accuracy.

In shutdown mode, the MAX5253’s REFAB and REFCD
inputs enter a high-impedance state with a typical input
leakage current of 0.01µA.

The reference input capacitance is also code depen­dent and typically ranges from 20pF with an input code
of all 0s to 100pF with an input code of all 1s.

All MAX5253 DAC outputs are internally buffered by pre­cision amplifiers with a typical slew rate of 0.6V/µs.
Access to the inverting input of each output amplifier
provides the user greater flexibility in output gain setting/
signal conditioning (see the
tion).

With a full-scale transition at the MAX5253 output, the
typical settling time to ±1/2LSB is 16µs when loaded
with 5kΩ in parallel with 100pF (loads less than 2kΩ
degrade performance).

The MAX5253 output amplifier’s output dynamic
responses and settling performances are shown in the

Typical Operating Characteristics

The MAX5253 features a software-programmable shut­down that reduces supply current to a typical value of
3µA. The power-down lockout (PDL) pin must be high to
enable the shutdown mode. Writing 1100XXXXXXXXXXXX
as the input-control word puts the MAX5253 in shutdown
mode (Table 1).

DD

RRR

2R 2R 2R 2R

2R

MAX5253

REF_

AGND

SHOWN FOR ALL 1s ON DAC

Figure 1. Simplified DAC Circuit Diagram

D0 D9 D10

D11

_______________Detailed Description

The MAX5253 contains four 12-bit, voltage-output digi­tal-to-analog converters (DACs) that are easily
addressed using a simple 3-wire serial interface. It
includes a 16-bit data-in/data-out shift register, and
each DAC has a doubled-buffered input composed of
an input register and a DAC register (see

Diagram

amplifier’s negative input is available to the user.
The DACs are inverted R-2R ladder networks that con-

vert 12-bit digital inputs into equivalent analog output
voltages in proportion to the applied reference voltage
inputs. DACs A and B share the REFAB reference input,
while DACs C and D share the REFCD reference input.
The two reference inputs allow different full-scale output
voltage ranges for each pair of DACs. Figure 1 shows a
simplified circuit diagram of one of the four DACs.

). In addition to the four voltage outputs, each

Reference Inputs

The two reference inputs accept positive DC and AC
signals. The voltage at each reference input sets the
full-scale output voltage for its two corresponding
DACs. The reference input voltage range is 0V to (V

- 1.4V). The output voltages (V
a digitally programmable voltage source as:

V

= (V

OUT_

where NB is the numeric value of the DAC’s binary
input code (0 to 4095), V
and Gain is the externally set voltage gain.

x NB / 4096 ) x Gain

REF

REF

are represented by

OUT_)

is the reference voltage,

Functional

FB_

OUT_

Output Amplifiers

Applications Information

.

Shutdown Mode

sec-

8 _______________________________________________________________________________________

+3V, Quad, 12-Bit Voltage-Output DAC

with Serial Interface

In shutdown mode, the MAX5253 output amplifiers and
the reference inputs enter a high-impedance state. The
serial interface remains active. Data in the input regis­ters is retained in shutdown, allowing the MAX5253 to
recall the output states prior to entering shutdown. Exit
shutdown mode by either recalling the previous config­uration or by updating the DACs with new data. When
powering up the device or bringing it out of shutdown,
allow 20µs for the outputs to stabilize.

Serial-Interface Configurations

The MAX5253’s 3-wire serial interface is compatible
with both Microwire™ (Figure 2) and SPI™/QSPI™
(Figure 3). The serial input word consists of two address
bits and two control bits followed by 12 data bits
(MSB first), as shown in Figure 4. The 4-bit address/
control code determines the MAX5253’s response out­lined in Table 1. The connection between DOUT and
the serial-interface port is not necessary, but may be
used for data echo. Data held in the MAX5253’s shift
register can be shifted out of DOUT and returned to the
microprocessor (µP) for data verification.

The MAX5253’s digital inputs are double buffered.
Depending on the command issued through the serial
interface, the input register(s) can be loaded without
affecting the DAC register(s), the DAC register(s) can
be loaded directly, or all four DAC registers can be
updated simultaneously from the input registers
(Table 1).

Serial-Interface Description

The MAX5253 requires 16 bits of serial data. Table 1
lists the serial-interface programming commands. For
certain commands, the 12 data bits are “don’t cares.”
Data is sent MSB first and can be sent in two 8-bit
packets or one 16-bit word (CS must remain low until
16 bits are transferred). The serial data is composed of
two DAC address bits (A1, A0) and two control bits
(C1,C0), followed by the 12 data bits D11…D0 (Figure

4).The 4-bit address/control code determines:

• The register(s) to be updated

• The clock edge on which data is to be clocked out

via the serial-data output (DOUT)

• The state of the user-programmable logic output
(UPO)

• If the part is to go into shutdown mode (assuming
PDL is high)

• How the part is configured when exiting shutdown
mode.

SCLK

DIN

MAX5253

*THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5253, 
BUT MAY BE USED FOR READBACK PURPOSES.

Figure 2. Connections for Microwire

MAX5253

*THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5253,
BUT MAY BE USED FOR READBACK PURPOSES.

Figure 3. Connections for SPI/QSPI

MSB..................................................................................LSB

Address

Bits

A1 A0 C1 C0 D11................................................D0

4 Address/

Control Bits

Figure 4. Serial-Data Format

DOUT*

CS

DOUT*

DIN

SCLK

CS

16 Bits of Serial Data

Control

Bits

MSB.............................................LSB

SK

SO

SI*

I/O

MISO*

MOSI

SCK

I/O

CPOL = 0,CPHA = 0

Data Bits

12 Data Bits

MICROWIRE

PORT

+3.3V

SS

SPI/QSPI

PORT

MAX5253

_______________________________________________________________________________________ 9

+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface

Table 1. Serial-Interface Programming Commands

16-BIT SERIAL WORD

A1 A0 C1 C0

00
01
10

MAX5253

11
00

01
10
11

01
10 Load all DAC registers from shift register (exit shutdown mode).

11
00
01
00 No operation (NOP) to DAC registers

11

10

“X” = Don’t care

01
01
01
01

11
11
11
11

00
00

00
10
10
00

10

10

D11.................D0

MSB LSB

12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data

12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data

XXXXXXXXXXXX
12-bit DAC data

XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX

XXXXXXXXXXXX

XXXXXXXXXXXX

Load input register A; DAC registers unchanged.
Load input register B; DAC registers unchanged.
Load input register C; DAC registers unchanged.
Load input register D; DAC registers unchanged.

Load input register A; all DAC registers updated.
Load input register B; all DAC registers updated.
Load input register C; all DAC registers updated.
Load input register D; all DAC registers updated.

Update all DAC registers from their respective input registers (exit
shutdown mode).

Enter shutdown mode (provided PDL = 1)
UPO goes low (default)
UPO goes high

Mode 1, DOUT clocked out on SCLK’s rising edge. All DAC registers
updated.

Mode 0, DOUT clocked out on SCLK’s falling edge. All DAC registers
updated (default).

FUNCTION

Figure 5 shows the serial-interface timing requirements.
The chip-select pin (CS) must be low to enable the
DAC’s serial interface. When CS is high, the interface
control circuitry is disabled. CS must go low at least
t

before the rising serial clock (SCLK) edge to prop-

CSS

erly clock in the first bit. When CS is low, data is
clocked into the internal shift register via the serial-data
input pin (DIN) on SCLK’s rising edge. The maximum
guaranteed clock frequency is 10MHz. Data is latched
into the appropriate MAX5253 input/DAC registers on
CS’s rising edge.

The programming command Load-All-DACs-From-Shift­Register allows all input and DAC registers to be simul­taneously loaded with the same digital code from the
input shift register. The no operation (NOP) command
leaves the register contents unaffected and is useful
when the MAX5253 is configured in a daisy chain (see
the

Daisy Chaining Devices

10 ______________________________________________________________________________________

section). The command to

change the clock edge on which serial data is shifted
out of DOUT also loads data from all input registers to
their respective DAC registers.

Serial-Data Output (DOUT)

The serial-data output, DOUT, is the internal shift regis­ter’s output. The MAX5253 can be programmed so that
data is clocked out of DOUT on SCLK’s rising edge
(Mode 1) or falling edge (Mode 0). In Mode 0, output
data at DOUT lags input data at DIN by 16.5 clock
cycles, maintaining compatibility with Microwire,
SPI/QSPI, and other serial interfaces. In Mode 1, output
data lags input data by 16 clock cycles. On power-up,
DOUT defaults to Mode 0 timing.

User-Programmable Logic Output (UPO)

The user-programmable logic output, UPO, allows an
external device to be controlled via the MAX5253 serial
interface (Table 1).

+3V, Quad, 12-Bit Voltage-Output DAC

CS

SCLK

DIN

DOUT

(MODE 0)

DOUT

(MODE 1)

Figure 5. Serial-Interface Timing Diagram

CS

SCLK

DIN

DOUT

1

A0

C1

A1 D0

A1 D0 A1

MSB FROM
PREVIOUS WRITE

A0

A1 D0 A1

MSB FROM



PREVIOUS WRITE

t

CSS

t

CSO

t

C0

A0

C1

C0

C1

C0

DS

t

DH

D11

D11

D11

t

CL

D10

D10

D10

8

D8

D9

DATA PACKET (N)

D8

D9

DATA PACKET (N-1)

D8

D9

DATA PACKET (N-1)

t

CH

with Serial Interface

MAX5253

COMMAND

EXECUTED

9

D6

D7

D6

D7

D6

D7

D5

D3

D5

D5

D4

t

D2

D4

D3

D2

D4

D3

D2

t

CP

t

DO2

DO1

16

D1

D1

DATA PACKET (N)

D1

DATA PACKET (N)

t

CSW

t

CSH

t

CS1

Figure 6. Detailed Serial-Interface Timing Diagram

Power-Down Lockout (

PDL

The power-down lockout pin PDL disables software
shutdown when low. When in shutdown, transitioning
PDL from high to low wakes up the part with the output
set to the state prior to shutdown. PDL could also be
used to asynchronously wake up the device.

Daisy-Chaining Devices

Any number of MAX5253s can be daisy chained by
connecting the DOUT pin of one device to the DIN pin
of the following device in the chain (Figure 7).

______________________________________________________________________________________ 11

Since the MAX5253’s DOUT pin has an internal active

)

pull-up, the DOUT sink/source capability determines
the time required to discharge/charge a capacitive
load. Refer to the serial-data-out V
cations in the

Electrical Characteristics.

and VOLspecifi-

OH

Figure 8 shows an alternate method of connecting sev­eral MAX5253s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy chain. More I/O lines are required in this configu­ration because a dedicated chip-select input (CS) is
required for each IC.

+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface

MAX5253

SCLK

DIN

CS

Figure 7. Daisy-Chaining MAX5253s

DIN

SCLK

CS1
CS2

CS3

SCLK
DIN
CS

CS

MAX5253

DOUT

SCLK
DIN
CS

CS

MAX5253

DOUT

SCLK
DIN
CS

MAX5253

CS

DOUT

TO OTHER 
SERIAL DEVICES

TO OTHER 
SERIAL DEVICES

MAX5253

SCLK

DIN

SCLK

DIN

MAX5253

MAX5253

SCLK

DIN

Figure 8. Multiple MAX5253s Sharing a Common DIN Line

12 ______________________________________________________________________________________

+3V, Quad, 12-Bit Voltage-Output DAC

with Serial Interface

__________Applications Information

For a unipolar output, the output voltages and the refer­ence inputs have the same polarity. Figure 9 shows the
MAX5253 unipolar output circuit, which is also the typi­cal operating circuit. Table 2 lists the unipolar output
codes.

For rail-to-rail outputs, see Figure 10. This circuit shows
the MAX5253 with the output amplifiers configured with
a closed-loop gain of +2.6 to provide 0V to 3.25V full­scale range when a 1.25V reference is used.

Unipolar Output

Table 2. Unipolar Code Table

DAC CONTENTS

MSB LSB

1111 1111 1111 +V

1000 0000 0001 +V

1000 0000 0000 +V

0111 1111 1111 +V

0000 0000 0001 +V
0000 0000 0000 0V

ANALOG OUTPUT

4095

(——— )

REF

4096
2049

(——— )

REF

4096

2048 +V

(——— )= ————

REF

4096 2

2047

(——— )

REF

4096

1

(——— )

REF

4096

REF

Table 3. Bipolar Code Table

The MAX5253 outputs can be configured for bipolar

Bipolar Output

operation using Figure 11’s circuit.

V

= V

OUT

[(2NB / 4096) - 1]

REF

where NB is the numeric value of the DAC’s binary
input code. Table 3 shows digital codes (offset binary)
and corresponding output voltages for Figure 11’s
circuit.

+3.3V

V

DD

FBA

OUTA

FBB

OUTB

FBC

OUTC

FBD

OUTD

DGNDAGND

MAX5253

REFERENCE INPUTS

REFAB



REFCD

DAC A

DAC B

DAC C

DAC D

MAX5253

DAC CONTENTS

MSB LSB

1111 1111 1111 +V

1000 0000 0001 +V
1000 0000 0000 0V
0111 1111 1111 -V

0000 0000 0001 -V

0000 0000 0000 -V

______________________________________________________________________________________ 13

ANALOG OUTPUT

(——— )

REF

(——— )

REF

(——— )

REF

(——— )

REF

2048

(——— )= -V

REF

2048

2047
2048

1

2048

1

2048
2047

2048

Figure 9. Unipolar Output Circuit

REF

+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface

REFERENCE INPUTS

MAX5253

REFAB



REFCD

DAC A

MAX5253

DAC B

DAC C

DAC D

= V

REFCD

= 1.25V

R1

V

REFAB

Figure 10. Unipolar Rail-to-Rail Output Circuit

+3.3V

V

DD

DGNDAGND

FBA

OUTA
FBB

OUTB
FBC

OUTC
FBD

OUTD

10k

16k

10k

16k

10k

16k

10k

16k

In applications where the reference has AC signal com­ponents, the MAX5253 has multiplying capability within
the reference input range specifications. Figure 12
shows a technique for applying a sine-wave signal to
the reference input where the AC signal is offset before
being applied to REFAB/REFCD. The reference voltage
must never be more negative than DGND.

The MAX5253’s total harmonic distortion plus noise
(THD + N) is typically less than -72dB, given a 1Vp-p
signal swing and input frequencies up to 25kHz. The
typical -3dB frequency is 650kHz, as shown in the

Typical Operating Characteristics

graphs.

Digitally Programmable Current Source

The circuit of Figure 13 places an NPN transistor
(2N3904 or similar) within the op-amp feedback loop to
implement a digitally programmable, unidirectional cur­rent source. This circuit can be used to drive 4mA to
20mA current loops, which are commonly used in
industrial-control applications. The output current is cal­culated with the following equation:

I

= (V

OUT

/ R) x (NB / 4096)

REF

where NB is the numeric value of the DAC’s binary
input code and R is the sense resistor shown in
Figure 13.

+3.3V



AC

Using an AC Reference

R2

REFERENCE 

26k

INPUT

1/2 MAX492

REF_

FB_

DAC

OUT_

MAX5253

Figure 11. Bipolar Output Circuit

+5V

-5V

R1 = R2 = 10kΩ ± 0.1%

500mVp-p

V

OUT

Figure 12. AC Reference Input Circuit

10k

REF_

DAC_

14 ______________________________________________________________________________________

V

DD

MAX5253

AGND DGND

OUT_

+3V, Quad, 12-Bit Voltage-Output DAC

with Serial Interface

REF_

V

OUT_

FB_

L

2N3904

R

I

OUT

MAX5253

DAC_

Figure 13. Digitally Programmable Current Source

Power-Supply Considerations

On power-up, all input and DAC registers are cleared
(set to zero code) and DOUT is in Mode 0 (serial data
is shifted out of DOUT on the clock’s falling edge).

For rated MAX5253 performance, limit REFAB/REFCD
to less than 1.4V below VDD. Bypass VDDwith a 4.7µF
capacitor in parallel with a 0.1µF capacitor to AGND.
Use short lead lengths and place the bypass capaci­tors as close to the supply pins as possible.

Grounding and Layout Considerations

Digital or AC transient signals between AGND and
DGND can create noise at the analog outputs. Tie
AGND and DGND together at the DAC, then tie this
point to the highest-quality ground available.

Good printed circuit board ground layout minimizes
crosstalk between DAC outputs, reference inputs, and
digital inputs. Reduce crosstalk by keeping analog
lines away from digital lines. Wire-wrapped boards are
not recommended.

__________________Pin Configuration

TOP VIEW

1

AGND

FBA

OUTA

FBB

REFAB

DIN

2
3
4

MAX5253

5
6
7

CL

8
9

10

DIP/SSOP

V

20

DD

FBD

19

OUTD

18

OUTCOUTB

17
16

FBC

15

REFCD

14

PDL

13

UPOCS

12

DOUT

11

DGNDSCLK

MAX5253

______________________________________________________________________________________ 15

+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface

_Ordering Information (continued) ___________________Chip Information

PART

TEMP. RANGE PIN-PACKAGE

MAX5253BC/D

MAX5253AEPP -40°C to +85°C
MAX5253BEPP
MAX5253AEAP

MAX5253

MAX5253BEAP -40°C to +85°C

-40°C to +85°C 20 Plastic DIP

-40°C to +85°C

0°C to +70°C

Dice*
20 Plastic DIP

20 SSOP
20 SSOP

INL

(LSBs)

±1
±1/2
±1
±1/2
±1

MAX5253BMJP -55°C to +125°C 20 CERDIP** ±2

*

Dice are specified at TA= +25°C, DC parameters only.

**

Contact factory for availability and processing to MIL-STD-883.

________________________________________________________Package Information

HE

C

TRANSISTOR COUNT: 4337

DIM



A

A1

B

C

α

L

D

E
e

H

L

α

INCHES

MIN

0.068

0.002

0.010

0.004
SEE VARIATIONS



0.205



0.301

0.025

0˚

MAX

0.078

0.008

0.015

0.008

0.209

0.311

0.037
8˚





MILLIMETERS

MIN

1.73

0.05

0.25

0.09


5.20

0.65 BSC0.0256 BSC



7.65

0.63

0˚

MAX

1.99

0.21

0.38

0.20


5.38


7.90

0.95

8˚

PINS

14
16
20
24
28

INCHES

MIN



0.239

0.239

0.278

0.317

0.397

DIM

e

SSOP

A

SHRINK

SMALL-OUTLINE

B

D

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]

16

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]

© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

A1

PACKAGE



D
D
D
D
D

MAX

0.249

0.249

0.289

0.328

0.407

MILLIMETERS

MAX

MIN

6.33

6.07

6.33

6.07

7.33

7.07

8.33

8.07

10.33

10.07

21-0056A