Page 1
19-1171; Rev 0; 12/96
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
__________________General Description
The +5V MAX5250 combines four low-power, voltageoutput, 10-bit digital-to-analog converters (DACs) and
four precision output amplifiers in a space-saving, 20pin package. In addition to the four voltage outputs,
each amplifier’s negative input is also available to the
user. This facilitates specific gain configurations, remote
sensing, and high output drive capacity, making the
MAX5250 ideal for industrial-process-control applications. Other features include software shutdown, hardware shutdown lockout, an active-low reset that clears
all registers and DACs to zero, a user-programmable
logic output, and a serial-data output.
Each DAC has a double-buffered input organized as an
input register followed by a DAC register. A 16-bit serial
word loads data into each input/DAC register. The
3-wire serial interface is compatible with SPI™/QSPI™
and Microwire™. It allows the input and DAC registers to
______________________________Features
♦ Four 10-Bit DACs with Configurable
Output Amplifiers
♦ +5V Single-Supply Operation
♦ Low Supply Current: 0.85mA Normal Operation
10µA Shutdown Mode
♦ Available in 20-Pin SSOP and DIP Packages
♦ Power-On Reset Clears all Registers and
DACs to Zero
♦ SPI/QSPI and Microwire Compatible
♦ Simultaneous or Independent Control of DACs
via 3-Wire Serial Interface
♦ User-Programmable Digital Output
♦ Schmitt-Trigger Inputs for Direct Optocoupler
Interface
♦ 12-Bit Upgrade Available: MAX525
be updated independently or simultaneously with a single software command. All logic inputs are TTL/CMOS-
_________________Ordering Information
logic compatible.
INL
(LSB)
±1/2
±1
±1/2
________________________Applications
Digital Offset and Gain Adjustment
Microprocessor-Controlled Systems
Industrial Process Controls
Automatic Test Equipment
Remote Industrial Controls
PART
MAX5250ACPP
MAX5250BCPP
MAX5250ACAP 0°C to +70°C
MAX5250BCAP 0°C to +70°C 20 SSOP ±1
Ordering Information continued on last page.
Pin Configuration appears at end of data sheet.
TEMP. RANGE PIN-PACKAGE
0°C to +70°C
0°C to +70°C
20 Plastic DIP
20 Plastic DIP
20 SSOP
Motion Control
_________________________________________________________________________Functional Diagram
MAX5250
DOUT
CL
16-BIT
SHIFT
REGISTER
SR
CONTROL
DIN
CS
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________
PDL
DGND
DECODE
CONTROL
LOGIC
OUTPUT
SCLK
UPO REFCD
AGND
INPUT
REGISTER A
INPUT
REGISTER B
INPUT
REGISTER C
INPUT
REGISTER D
V
DD
REGISTER A
REGISTER B
REGISTER C
REGISTER D
DAC
DAC
DAC
DAC
MAX5250
REFAB
DAC A
DAC B
DAC C
DAC D
FBA
OUTA
FBB
OUTB
FBC
OUTC
FBD
OUTD
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Page 2
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
ABSOLUTE MAXIMUM RATINGS
VDDto AGND............................................................-0.3V to +6V
to DGND ...........................................................-0.3V to +6V
V
DD
AGND to DGND..................................................................±0.3V
REFAB, REFCD to AGND...........................-0.3V to (V
OUT_, FB_ to AGND...................................-0.3V to (V
Digital Inputs to DGND.............................................-0.3V to +6V
DOUT, UPO to DGND ................................-0.3V to (V
Continuous Current into Any Pin.......................................±20mA
DD
DD
DD
+ 0.3V)
+ 0.3V)
+ 0.3V)
MAX5250
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Continuous Power Dissipation (T
Plastic DIP (derate 8.00mW/°C above +70°C).................640mW
SSOP (derate 8.00mW/°C above +70°C) ......................640mW
CERDIP (derate 11.11mW/°C above +70°C).................889mW
Operating Temperature Ranges
MAX5250_C_P......................................................0°C to +70°C
MAX5250_E_P ...................................................-40°C to +85°C
MAX5250BMJP................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
ELECTRICAL CHARACTERISTICS
(VDD= +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, RL= 5kΩ, CL= 100pF, TA= T
noted. Typical values are at T
= +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
A
= +70°C)
A
to T
MIN
, unless otherwise
MAX
PARAMETER SYMBOL MIN TYP MAX UNITS
STATIC PERFORMANCE—ANALOG SECTION
Resolution N 10 Bits
Integral Nonlinearity
(Note 1)
Differential Nonlinearity DNL ±1.0 LSB
Offset Error V
Offset-Error Tempco 6 ppm/°C
Gain Error (Note 1) GE ±1.0 LSB
Gain-Error Tempco 1 ppm/°C
Power-Supply Rejection Ratio PSRR 100 800 µV/V
REFERENCE INPUT
Reference Input Range V
Reference Input Resistance R
MULTIPLYING-MODE PERFORMANCE
Reference -3dB Bandwidth 650 kHz
Reference Feedthrough -84 dBInput code = all 0s, V
Signal-to-Noise Plus
Distortion Ratio
INL
REF
REF
SINAD 72 dB
MAX5250A
MAX5250B
Guaranteed monotonic
OS
4.5V ≤ VDD≤ 5.5V
Code dependent, minimum at code 554 hex
V
= 0.67Vp-p
REF
V
= 1Vp-p at 25kHz, code = full scale
REF
CONDITIONS
= 3.6Vp-p at 1kHz
REF
±0.25 ±0.5
±1.0
±6.0 mV
0V
10 kΩ
- 1.4 V
DD
LSB
2 _______________________________________________________________________________________
Page 3
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, RL= 5kΩ, CL= 100pF, TA= T
noted. Typical values are at T
PARAMETER SYMBOL MIN TYP MAX UNITS
DIGITAL INPUTS
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
Input Capacitance C
DIGITAL OUTPUTS
Output High Voltage V
Output Low Voltage V
DYNAMIC PERFORMANCE
Voltage Output Slew Rate SR 0.6 V/µs
Output Settling Time 10 µs
Output Voltage Swing 0 to V
Current into FB_ 0 0.1 µA
OUT_ Leakage Current
in Shutdown
Start-Up Time Exiting
Shutdown Mode
Digital Feedthrough 5 nV-s
Digital Crosstalk 5 nV-s
POWER SUPPLIES
Supply Voltage V
Supply Current I
Supply Current in Shutdown 10 20 µA
Reference Current in Shutdown 0.01 ±1 µA
= +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
A
CONDITIONS
2.4 V
VDD- 0.5 V
4.5 5.5 V
IN
OH
OL
DD
DD
IH
IL
VIN= 0V or V
IN
I
SOURCE
I
= 2mA
SINK
To ±1/2LSB, V
Rail-to-rail (Note 2)
RL= ∞
CS = VDD, DIN = 100kHz
(Note 3)
(Note 3)
DD
= 2mA
STEP
= 2.5V
to T
MIN
0.01 ±1.0 µA
0.13 0.4 V
0.01 ±1 µA
0.85 0.98 mA
, unless otherwise
MAX
0.8 V
8 pF
DD
15 µs
MAX5250
V
Note 1: Guaranteed from code 3 to code 1023 in unity-gain configuration.
Note 2: Accuracy is better than 1LSB for V
end points.
Note 3: R
= ∞, digital inputs at DGND or VDD.
L
_______________________________________________________________________________________ 3
= 6mV to VDD- 60mV, guaranteed by a power-supply rejection test at the
OUT
Page 4
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, RL= 5kΩ, CL= 100pF, TA= T
noted. Typical values are at T
= +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
A
CONDITIONS
TIMING CHARACTERISTICS (Figure 6)
SCLK Clock Period
SCLK Pulse Width High
MAX5250
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Raise to CS Rise Hold Time
DIN Setup Time
DIN Hold Time
SCLK Rise to DOUT Valid
Propagation Delay
SCLK Fall to DOUT Valid
Propagation Delay
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
CP
CH
CL
CSS
CSH
DS
DH
D01
D02
CS0
CS1
CSW
C
C
LOAD
LOAD
= 200pF
= 200pF
MIN
to T
, unless otherwise
MAX
UNITSMIN TYP MAXSYMBOLPARAMETER
ns100t
ns40t
ns40t
ns40t
ns0t
ns40t
ns0t
ns80t
ns80t
ns40t
ns40t
ns100t
__________________________________________Typical Operating Characteristics
(V
= +5V, TA = +25°C, unless otherwise noted.)
DD
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE
0.075
0.050
0.025
0
-0.025
INL (LSB)
-0.050
-0.075
-0.100
RL = 5kΩ
-0.125
0.4 1.2 2.0 2.8 3.6
REFERENCE VOLTAGE (V)
MAX5250-01
RELATIVE OUTPUT (dB)
4.4
-12
-16
-20
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
0
-4
-8
0 500k 1.0M 1.5M 2.0M 2.5M 3.0M
REFAB SWEPT 0.67Vp-p
RL = 5kΩ
CL = 100pF
FREQUENCY (Hz)
MAX5250-02
1000
950
900
850
800
750
700
650
SUPPLY CURRENT (µA)
600
550
500
-55 -40 -20 0 20 40 60 80 100 120
4 _______________________________________________________________________________________
SUPPLY CURRENT
vs. TEMPERATURE
CODE = FFC hex
TEMPERATURE (°C)
MAX5250-03
Page 5
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
____________________________Typical Operating Characteristics (continued)
(V
= +5V, TA = +25°C, unless otherwise noted.)
DD
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1000
950
900
850
800
750
SUPPLY CURRENT (µA)
700
650
CODE = FFC hex
600
4.0 4.2 4.64.4 4.8 5.0 5.2 5.4 5.6
SUPPLY VOLTAGE (V)
0
-0.25
-0.50
TOTAL HARMONIC DISTORTION PLUS NOISE
0.50
0.45
MAX5250-04
0.40
0.35
0.30
0.25
0.20
THD + NOISE (%)
0.15
0.10
0.05
0
FULL-SCALE ERROR
vs. LOAD
vs. FREQUENCY
DAC CODE = FULL SCALE
REFAB = 1Vp-p
= 5kΩ
R
L
= 100pF
C
L
1
FREQUENCY (kHz)
MAX5250-09
0
MAX5250-05
10
100
-20
-40
-60
SIGNAL AMPLITUDE (dB)
-80
-100
0.5 1.6 3.8
REFERENCE FEEDTHROUGH
AT 1kHz
0
-20
-40
REFAB INPUT SIGNAL
V
= 3.6Vp-p @ 1kHz
REF
= 5kΩ
R
L
= 100pF
C
L
OUTPUT FFT PLOT
V
= 1kHz, 0.006V TO 3.6V
REF
= 5kΩ
R
L
= 100pF
C
L
2.7 4.9 6.0
FREQUENCY (kHz)
MAX5250-11
MAX5250
MAX5250-10
-0.75
FULL-SCALE ERROR (LSB)
-1.00
-1.25
0.01 0.1 1 10 100
LOAD (kΩ)
-60
SIGNAL AMPLITUDE (dB)
-80
-100
0.5 1.2 2.6
OUTA FEEDTHROUGH
FREQUENCY (kHz)
1.9 3.3 4.0
_______________________________________________________________________________________
5
Page 6
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
____________________________Typical Operating Characteristics (continued)
(V
DD
= +5V, V
= 2.5V, RL= 5kΩ, CL= 100pF, TA = +25°C, unless otherwise noted.)
REF
MAX5250
GND
MAJOR-CARRY TRANSITION
10µs/div
ANALOG CROSSTALK
MAX5250-07
MAX5250-12
CS
5V/div
OUTB,
AC COUPLED
100mV/div
OUTA,
1V/div
DIGITAL FEEDTHROUGH (SCLK = 100kHz)
2µs/div
CS = PDL = C
DAC A CODE SET TO 800 hex
L = 5V, DIN = 0V
DYNAMIC RESPONSE
MAX5250-08
SCLK,
2V/div
OUTA,
AC COUPLED
10mV/div
MAX5250-13
OUTA,
1V/div
OUTB,
AC COUPLED
10mV/div
10µs/div
DAC A CODE SWITCHING FROM 00C hex TO FFC hex
DAC B CODE SET TO 800 hex
SWITCHING FROM CODE 000 hex TO FB4 hex
OUTPUT AMPLIFIER GAIN = +2
10µs/div
6 _______________________________________________________________________________________
Page 7
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
______________________________________________________________Pin Description
PIN NAME FUNCTION
1 AGND Analog Ground
2 FBA DAC A Output Amplifier Feedback
3 OUTA DAC A Output Voltage
4 OUTB DAC B Output Voltage
5 FBB DAC B Output Amplifier Feedback
6 REFAB Reference Voltage Input for DAC A and DAC B
7
8
9 DIN Serial-Data Input
10 SCLK Serial-Clock Input
11 DGND Digital Ground
12 DOUT Serial-Data Output
13 UPO User-Programmable Logic Output
14
CL
CS
PDL
Clear All DACs and Registers. Resets all outputs (OUT_, UPO, DOUT) to 0, active low.
Chip-Select Input. Active low.
Power-Down Lockout. Active low. Locks out software shutdown if low.
MAX5250
15 REFCD Reference Voltage Input for DAC C and DAC D
16 FBC DAC C Output Amplifier Feedback
17 OUTC DAC C Output Voltage
18 OUTD DAC D Output Voltage
19 FBD DAC D Output Amplifier Feedback
20 V
DD
Positive Power Supply
_______________________________________________________________________________________ 7
Page 8
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
The impedance at each reference input is code dependent, ranging from a low value of 10kΩ when both
DACs connected to the reference have an input code
of 554 hex, to a high value exceeding several giga
ohms (leakage currents) with an input code of 000 hex.
Because the input impedance at the reference pins is
code dependent, load regulation of the reference
source is important.
The REFAB and REFCD reference inputs have a 10kΩ
guaranteed minimum input impedance. When the two
reference inputs are driven from the same source, the
effective minimum impedance is 5kΩ. A voltage reference with a load regulation of 6ppm/mA, such as the
MAX873, would typically deviate by 0.006LSB (0.015LSB
worst case) when driving both MAX5250 reference
inputs simultaneously at 2.5V. Driving the REFAB and
REFCD pins separately improves reference accuracy.
In shutdown mode, the MAX5250’s REFAB and REFCD
inputs enter a high-impedance state with a typical input
leakage current of 0.01µA.
The reference input capacitance is also code dependent and typically ranges from 20pF with an input code
of all 0s to 100pF at full scale.
Output Amplifiers
All MAX5250 DAC outputs are internally buffered by precision amplifiers with a typical slew rate of 0.6V/µs.
Access to each output amplifier’s inverting input provides
the user greater flexibility in output gain setting/
signal conditioning (see the
section).
With a full-scale transition at the MAX5250 output, the
typical settling time to ±1/2LSB is 10µs when loaded
with 5kΩ in parallel with 100pF (loads less than 2kΩ
degrade performance).
The MAX5250 output amplifier’s output dynamic
responses and settling performances are shown in the
Typical Operating Characteristics
Applications Information
.
Power-Down Mode
The MAX5250 features a software-programmable shutdown that reduces supply current to a typical value of
10µA. The power-down lockout pin (PDL) must be high to
enable shutdown mode. Writing 1100XXXXXXXXXXXX as
the input-control word puts the MAX5250 in power-down
mode (Table 1).
RRR
2R 2R 2R 2R
2R
MAX5250
S0 S1 D0
REF_
AGND
SHOWN FOR ALL 1s ON DAC
Figure 1. Simplified DAC Circuit Diagram
_______________Detailed Description
The MAX5250 contains four 10-bit, voltage-output digital-to-analog converters (DACs) that are easily
addressed using a simple 3-wire serial interface. It
includes a 16-bit data-in/data-out shift register, and
each DAC has a doubled-buffered input composed of
an input register and a DAC register (see
Diagram
amplifier’s negative input is available to the user.
The DACs are inverted R-2R ladder networks that con-
vert a digital input (10 data bits plus 2 sub-bits) into
equivalent analog output voltages in proportion to the
applied reference voltage inputs. DACs A and B share
the REFAB reference input, while DACs C and D share
the REFCD reference input. The two reference inputs
allow different full-scale output voltage ranges for each
pair of DACs. Figure 1 shows a simplified circuit diagram of one of the four DACs.
The two reference inputs accept positive DC and AC
signals. The voltage at each reference input sets the
full-scale output voltage for its two corresponding
DACs. The reference input voltage range is 0V to
(VDD- 1.4V). The output voltages (V
sented by a digitally programmable voltage source as:
where NB is the numeric value of the DAC’s binary
input code (0 to 1023), V
and Gain is the externally set voltage gain.
). In addition to the four voltage outputs, each
V
OUT_
= (V
x NB / 1024) x Gain
REF
is the reference voltage,
REF
D9
Functional
Reference Inputs
are repre-
OUT_)
FB_
OUT_
8 _______________________________________________________________________________________
Page 9
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
In power-down mode, the MAX5250 output amplifiers
and the reference inputs enter a high-impedance state.
The serial interface remains active. Data in the input
registers is retained in power-down, allowing the
MAX5250 to recall the output states prior to entering
shutdown. Start up from power-down either by recalling
the previous configuration or by updating the DACs
with new data. When powering up the device or bringing it out of shutdown, allow 15µs for the outputs to
stabilize.
Serial-Interface Configurations
The MAX5250’s 3-wire serial interface is compatible
with both Microwire™ (Figure 2) and SPI™/QSPI™
(Figure 3). The serial input word consists of two address
bits and two control bits followed by 10+2 data bits
(MSB first), as shown in Figure 4. The 4-bit address/
control code determines the MAX5250’s response outlined in Table 1. The connection between DOUT and
the serial-interface port is not necessary, but may be
used for data echo. Data held in the MAX5250’s shift
register can be shifted out of DOUT and returned to the
microprocessor (µP) for data verification.
The MAX5250’s digital inputs are double buffered.
Depending on the command issued through the serial
interface, the input register(s) can be loaded without
affecting the DAC register(s), the DAC register(s) can
be loaded directly, or all four DAC registers can be
updated simultaneously from the input registers
(Table 1).
Serial-Interface Description
The MAX5250 requires 16 bits of serial data. Table 1
lists the serial-interface programming commands. For
certain commands, the 10+2 data bits are “don’t
cares.” Data is sent MSB first and can be sent in two
8-bit packets or one 16-bit word (CS must remain low
until 16 bits are transferred). The serial data is composed of two DAC address bits (A1, A0) and two control bits (C1, C0), followed by the 10+2 data bits
D9…D0, S1, S0 (Figure 4). Set both sub-bits (S1, S0) to
zero. The 4-bit address/control code determines:
• The register(s) to be updated
• The clock edge on which data is to be clocked out
via the serial-data output (DOUT)
• The state of the user-programmable logic output
(UPO)
• If the part is to go into shutdown mode (assuming
PDL is high)
• How the part is configured when coming out of shutdown mode.
SCLK
DIN
MAX5250
*THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5250,
BUT MAY BE USED FOR READBACK PURPOSES.
Figure 2. Connections for Microwire
MAX5250
*THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5250,
BUT MAY BE USED FOR READBACK PURPOSES.
Figure 3. Connections for SPI/QSPI
MSB..................................................................................LSB
Address
Bits
A1 A0 C1 C0 D9 .....................................D0, S1, S0
4 Address/
Control Bits
Figure 4. Serial-Data Format
DOUT*
CS
DOUT*
DIN
SCLK
CS
16 Bits of Serial Data
Control
Bits
MSB..................................LSB
SK
SO
MICROWIRE
SI*
I/O
MISO*
MOSI
SPI/QSPI
SCK
I/O
CPOL = 0,CPHA = 0
Data Bits
10+2 Data Bits
PORT
+5V
SS
PORT
MAX5250
_______________________________________________________________________________________ 9
Page 10
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
A1 A0 C1 C0
D9.................D0
MSB.............LSB
S1 S0
FUNCTION
00
01
10
MAX5250
11
00
01
10
11
0100 XXXXXXXXXX XX
100010-bit DAC data 00Load all DAC registers from shift register (also exit shutdown mode).
1100 XXXXXXXXXX XX
0010 XXXXXXXXXX XXUPO goes low (default).
0110 XXXXXXXXXX XXUPO goes high.
0000 XXXXXXXXXX XXNo operation (NOP) to DAC registers
1110 XXXXXXXXXX XX
1010 XXXXXXXXXX XX
“X” = Don’t care
Figure 5 shows the serial-interface timing requirements.
The chip-select pin (CS) must be low to enable the
DAC’s serial interface. When CS is high, the interface
control circuitry is disabled. CS must go low at least
t
before the rising serial clock (SCLK) edge to prop-
CSS
erly clock in the first bit. When CS is low, data is
clocked into the internal shift register via the serial-data
input pin (DIN) on SCLK’s rising edge. The maximum
guaranteed clock frequency is 10MHz. Data is latched
into the appropriate MAX5250 input/DAC registers on
CS’s rising edge.
The programming command Load-All-DACs-From-ShiftRegister allows all input and DAC registers to be simultaneously loaded with the same digital code from the
input shift register. The no operation (NOP) command
leaves the register contents unaffected and is useful
when the MAX5250 is configured in a daisy chain (see
the
Daisy Chaining Devices
01
01
01
01
11
11
11
11
10-bit DAC data
10-bit DAC data
10-bit DAC data
10-bit DAC data
10-bit DAC data
10-bit DAC data
10-bit DAC data
10-bit DAC data
00
00
00
00
00
00
00
00
section). The command to
Load input register A; DAC registers unchanged.
Load input register B; DAC registers unchanged.
Load input register C; DAC registers unchanged.
Load input register D; DAC registers unchanged.
Load input register A; all DAC registers updated.
Load input register B; all DAC registers updated.
Load input register C; all DAC registers updated.
Load input register D; all DAC registers updated.
Update all DAC registers from their respective input registers (also exit
shutdown mode).
Enter shutdown mode (provided PDL = 1).
Mode 1, DOUT clocked out on SCLK’s rising edge. All DAC registers
updated.
Mode 0, DOUT clocked out on SCLK’s falling edge. All DAC registers
updated (default).
change the clock edge on which serial data is shifted
out of DOUT also loads data from all input registers to
their respective DAC registers.
Serial-Data Output (DOUT)
The serial-data output, DOUT, is the internal shift register’s output. The MAX5250 can be programmed so that
data is clocked out of DOUT on SCLK’s rising edge
(Mode 1) or falling edge (Mode 0). In Mode 0, output
data at DOUT lags input data at DIN by 16.5 clock
cycles, maintaining compatibility with Microwire,
SPI/QSPI, and other serial interfaces. In Mode 1, output
data lags input data by 16 clock cycles. On power-up,
DOUT defaults to Mode 0 timing.
User-Programmable Logic Output (UPO)
The user-programmable logic output, UPO, allows an
external device to be controlled via the MAX5250 serial
interface (Table 1).
10 ______________________________________________________________________________________
Page 11
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
CS
COMMAND
SCLK
1
8
9
EXECUTED
16
MAX5250
A0
DIN
DOUT
(MODE 0)
DOUT
(MODE 1)
A1 S0
A1 S0 A1
A1 S0 A1
C1
A0
C1
MSB FROM
PREVIOUS WRITE
C1
A0
MSB FROM
PREVIOUS WRITE
C0
Figure 5. Serial-Interface Timing Diagram
CS
t
CSS
t
DS
t
DH
SCLK
DIN
DOUT
t
CSO
D9
C0
C0
D8
D9
D8
D9
D8
t
CL
D6
D7
DATA PACKET (N)
D6
D7
DATA PACKET (N-1)
D6
D7
DATA PACKET (N-1)
t
CH
D5
D4
D5
D5
D3
D4
D3
D4
D3
t
DO1
D1
D2
D1
D2
D1
D2
t
CP
t
DO2
S1
D0
S1
D0
DATA PACKET (N)
S1
D0
DATA PACKET (N)
t
CSW
t
CSH
t
CS1
Figure 6. Detailed Serial-Interface Timing Diagram
Power-Down (PDL)
The power-down lockout pin PDL disables software
shutdown when low. When in shutdown, transitioning
PDL from high to low wakes up the part with the output
set to the state prior to shutdown. PDL can also be
used to wake up the device asynchronously.
Daisy Chaining Devices
Any number of MAX5250s can be daisy chained by
connecting the DOUT pin of one device to the DIN pin
of the following device in the chain (Figure 7).
______________________________________________________________________________________ 11
Since the MAX5250’s DOUT pin has an internal active
pull-up, the DOUT sink/source capability determines
the time required to discharge/charge a capacitive
load. Refer to the serial-data-out V
cations in the
Electrical Characteristics.
and VOLspecifi-
OH
Figure 8 shows an alternate method of connecting several MAX5250s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is
required for each IC.
Page 12
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
MAX5250
SCLK
DIN
CS
Figure 7. Daisy-Chaining MAX5250s
DIN
SCLK
CS1
CS2
CS3
SCLK
DIN
CS
MAX5250
DOUT
SCLK
DIN
CS
MAX5250
DOUT
SCLK
DIN
CS
MAX5250
DOUT
TO OTHER
SERIAL DEVICES
TO OTHER
SERIAL DEVICES
CS
MAX5250
SCLK
DIN
CS
SCLK
DIN
MAX5250
CS
MAX5250
SCLK
DIN
Figure 8. Multiple MAX5250s Sharing a Common DIN Line
12 ______________________________________________________________________________________
Page 13
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
__________Applications Information
Unipolar Output
For a unipolar output, the output voltages and the reference inputs have the same polarity. Figure 9 shows the
MAX5250 unipolar output circuit, which is also the typical operating circuit. Table 2 lists the unipolar output
codes.
For rail-to-rail outputs, see Figure 10. This circuit shows
the MAX5250 with the output amplifiers configured with
a closed-loop gain of +2 to provide 0V to 5V full-scale
range when a 2.5V reference is used.
Table 2. Unipolar Code Table
DAC CONTENTS
MSB LSB
1111 1111 11(00) +V
1000 0000 01(00) +V
1000 0000 00(00) +V
0111 1111 11(00) +V
0000 0000 01(00) +V
0000 0000 00(00) 0V
ANALOG OUTPUT
1023
(——— )
REF
1024
513
(——— )
REF
1024
512 +V
(——— )= ————
REF
1024 2
511
(——— )
REF
1024
1
(——— )
REF
1024
REF
Bipolar Output
The MAX5250 outputs can be configured for bipolar
operation using Figure 11’s circuit:
V
= V
OUT
where NB is the numeric value of the DAC’s binary
input code. Table 3 shows digital codes (offset binary)
and corresponding output voltages for Figure 11’s
circuit.
MAX5250
REFERENCE INPUTS
REFAB
[(2NB / 1024) - 1]
REF
REFCD
DAC A
DAC B
DAC C
DAC D
+5V
V
DD
DGNDAGND
FBA
OUTA
FBB
OUTB
FBC
OUTC
FBD
OUTD
MAX5250
Table 3. Bipolar Code Table
DAC CONTENTS
MSB LSB
1111 1111 11(00) +V
1000 0000 01(00) +V
1000 0000 00(00) 0V
0111 1111 11(00) -V
0000 0000 01(00) -V
0000 0000 00(00) -V
( ) Sub-bits
______________________________________________________________________________________ 13
ANALOG OUTPUT
REF
511
(——— )
REF
512
1
(——— )
REF
512
1
(——— )
REF
512
511
(——— )
REF
512
512
(——— )= -V
512
Figure 9. Unipolar Output Circuit
REF
Page 14
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
Using an AC Reference
REFERENCE INPUTS
MAX5250
REFAB
REFCD
DAC A
MAX5250
DAC B
DAC C
DAC D
= V
REFCD
= 2.5V
V
REFAB
Figure 10. Unipolar Rail-to-Rail Output Circuit
+5V
V
DD
DGNDAGND
FBA
OUTA
FBB
OUTB
FBC
OUTC
FBD
OUTD
10k
10k
10k
10k
10k
10k
10k
10k
In applications where the reference has AC signal components, the MAX5250 has multiplying capability within
the reference input range specifications. Figure 12
shows a technique for applying a sine-wave signal to
the reference input where the AC signal is offset before
being applied to REFAB/REFCD. The reference voltage
must never be more negative than DGND.
The MAX5250’s total harmonic distortion plus noise
(THD + N) is typically less than -72dB (full-scale code),
given a 1Vp-p signal swing and input frequencies up to
25kHz. The typical -3dB frequency is 650kHz, as
shown in the
Typical Operating Characteristics
Digitally Programmable Current Source
The circuit of Figure 13 places an NPN transistor
(2N3904 or similar) within the op-amp feedback loop to
implement a digitally programmable, unidirectional current source. This circuit can be used to drive 4–20mA
current loops, which are commonly used in industrialcontrol applications. The output current is calculated
with the following equation:
I
= (V
OUT
where NB is the numeric value of the DAC’s binary
input code and R is the sense resistor shown in
Figure 13.
/ R) x (NB / 1024)
REF
graphs.
+5V
AC
R1
REF_
FB_
DAC
OUT_
MAX5250
Figure 11. Bipolar Output Circuit
+5V
-5V
R1 = R2 = 10kΩ ± 0.1%
R2
V
OUT
REFERENCE
INPUT
500mVp-p
Figure 12. AC Reference Input Circuit
26k
10k
1/2 MAX492
REF_
DAC_
AGND DGND
14 ______________________________________________________________________________________
V
DD
MAX5250
OUT_
Page 15
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
REF_
V
L
MAX5250
I
DAC_
OUT_
FB_
OUT
2N3904
R
Figure 13. Digitally Programmable Current Source
Power-Supply Considerations
On power-up, all input and DAC registers are cleared
(set to zero code) and DOUT is in Mode 0 (serial data
is shifted out of DOUT on the clock’s falling edge).
For rated MAX5250 performance, limit REFAB/REFCD
to less than 1.4V below VDD. Bypass VDDwith a 4.7µF
capacitor in parallel with a 0.1µF capacitor to AGND.
Use short lead lengths and place the bypass capacitors as close to the supply pins as possible.
__________________Pin Configuration
TOP VIEW
1
AGND
FBA
OUTA
FBB
REFAB
DIN
2
3
4
MAX5250
5
6
7
CL
8
9
10
DIP/SSOP
V
20
DD
FBD
19
OUTD
18
OUTCOUTB
17
16
FBC
15
REFCD
14
PDL
13
UPOCS
12
DOUT
11
DGNDSCLK
MAX5250
Grounding and Layout Considerations
Digital or AC transient signals between AGND and
DGND can create noise at the analog outputs. Tie
AGND and DGND together at the DAC, then tie this
point to the highest-quality ground available.
Good printed circuit board ground layout minimizes
crosstalk between DAC outputs, reference inputs, and
digital inputs. Reduce crosstalk by keeping analog
lines away from digital lines. Wire-wrapped boards are
not recommended.
______________________________________________________________________________________ 15
Page 16
Low-Power, Quad, 10-Bit Voltage-Output DAC
with Serial Interface
_Ordering Information (continued) ___________________Chip Information
PART
MAX5250AEPP
MAX5250BEPP
MAX5250AEAP -40°C to +85°C
TEMP. RANGE PIN-PACKAGE
-40°C to +85°C
-40°C to +85°C
20 Plastic DIP
20 Plastic DIP
20 SSOP
MAX5250BEAP -40°C to +85°C 20 SSOP ±1
MAX5250BMJP
MAX5250
*
Contact factory for availability and processing to MIL-STD-883.
-55°C to +125°C
20 CERDIP* ±1
INL
(LSB)
±1/2
±1
±1/2
TRANSISTOR COUNT: 4337
________________________________________________________Package Information
DIM
A1
C
α
D
HE
H
C
e
A
SMALL-OUTLINE
B
A1
L
SSOP
SHRINK
PACKAGE
DIM
D
D
D
D
D
INCHES
MIN
A
0.068
0.002
B
0.010
0.004
E
0.205
e
0.301
L
0.025
α
PINS
14
16
20
24
28
MAX
0.078
0.008
0.015
0.008
SEE VARIATIONS
0.209
0.311
0.037
0˚
INCHES
MIN
0.239
0.239
0.278
0.317
0.397
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
8˚
MAX
0.249
0.249
0.289
0.328
0.407
MILLIMETERS
MIN
1.73
0.05
0.25
0.09
5.20
7.65
0.63
MAX
1.99
0.21
0.38
0.20
0.65 BSC0.0256 BSC
0˚
MILLIMETERS
MIN
6.07
6.07
7.07
8.07
10.07
5.38
7.90
0.95
8˚
MAX
6.33
6.33
7.33
8.33
10.33
21-0056A
Loading...