MAX5223
Low-Power, Dual, 8-Bit, Voltage Output
Serial DAC in 8-Pin SOT23
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Note 1: The outputs may be shorted to VDDor GND if the package power dissipation is not exceeded. Typical short-circuit current to
GND is 70mA.
Note 2: Reduced digital code range (code 24 through code 232) is due to swing limitations of the output amplifiers. See Typical
Operating Characteristics.
Note 3: Reference input resistance is code-dependent. The lowest input resistance occurs at code 55hex. See the Reference Input
section.
Note 4: Guaranteed by design. Not production tested.
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +2.7V to +5.5V, REF = VDD, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
TIMING CHARACTERISTICS
(Figure 3, VDD= +2.7V to +5.5V, TA= T
MIN
to T
MAX
, unless otherwise noted.) (Note 4)
VDD= +3.6V
VDD= +5.5V
100 220
µA
150 275
All inputs = 0I
DD
Supply Current
50
µA0.6VDD= +5.5VShutdown Supply Current
V2.7 5.5V
DD
Supply Voltage Range
nV-s0.25All zeros to all ones
Digital Feedthrough
and Crosstalk
µs
To ±1⁄2LSB, CL= 100pF
Voltage Output Settling Time
V/µs0.15CL= 100pFSRVoltage Output Slew Rate
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
SERIAL INTERFACE TIMING
CONDITIONS
ns50t
CSPWH
–C—S–
Pulse Width High
ns20t
CL
SCLK Pulse Width Low
ns20t
CH
SCLK Pulse Width High
ns20t
DH
DIN to SCLK Rise Hold Time
ns20t
DS
DIN to SCLK Rise Setup Time
UNITSMIN TYP MAXSYMBOLPARAMETER
ns50t
CSS
ns50t
CSH
SCLK Rise to –C—S–Rise Setup Time
DYNAMIC PERFORMANCE
POWER SUPPLY
–C—S–
Fall to SCLK Rise Setup Time