For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX5187 is an 8-bit, current-output digital-to-analog converter (DAC) designed for superior performance
in signal reconstruction or arbitrary waveform generation applications requiring analog signal reconstruction
with low distortion and low-power operation. The voltage-output MAX5190 provides equal specifications,
with on-chip precision resistors for voltage output operation. Both devices are designed for a 10pVs glitch
operation to minimize unwanted spurious signal components at the output. An on-board +1.2V bandgap circuit provides a well-regulated, low-noise reference that
can be disabled for external reference operation.
The MAX5187/MAX5190 are designed to provide a high
level of signal integrity for the least amount of power
dissipation. They operate from a single supply of +2.7V
to +3.3V. Additionally, these DACs have three modes of
operation: normal, low-power standby, and full shutdown, which provides the lowest possible power dissipation with a 1µA (max) shutdown current. A fast
wake-up time (0.5µs) from standby mode to full DAC
operation allows for power conservation by activating
the DAC only when required.
The MAX5187/MAX5190 are packaged in a 24-pin
QSOP and are specified for the extended (-40°C to
+85°C) temperature range. For higher resolution, 10-bit
versions, see the MAX5181/MAX5184 data sheet.
Applications
Signal Reconstruction
Digital Signal Processing
Arbitrary Waveform Generation (AWG)
Imaging Applications
Features
♦ +2.7V to +3.3V Single-Supply Operation
♦ Wide Spurious-Free Dynamic Range:
70dB at f
OUT
= 2.2MHz
♦ Fully Differential Output
♦ Low-Current Standby or Full Shutdown Modes
♦ Internal +1.2V Low-Noise Bandgap Reference
♦ Small 24-Pin QSOP Package
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
________________________________________________________________ Maxim Integrated Products 1
19-1582; Rev 2; 12/01
PART
MAX5187BEEG
-40°C to +85°C
TEMP. RANGE PIN-PACKAGE
24 QSOP
Pin Configuration
Ordering Information
MAX5190BEEG
-40°C to +85°C 24 QSOP
TOP VIEW
CREF
OUTP
OUTN
AGND
AV
DACEN
CLK
REN
DGND
1
2
3
4
5
DD
PD
CS
MAX5187
6
MAX5190
7
8
9
10
11
12
QSOP
REFO
24
REFR
23
DGND
22
DV
21
DD
20
D7
19
D6
18
D5
17
D4
16
D3
15
D2
14
D1
13
D0DGND
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= DVDD= +3V ±10%, AGND = DGND = 0, f
CLK
= 40MHz, IFS= 1mA, 400Ω differential output, CL= 5pF, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDDto AGND, DGND .................................-0.3V to +6V
Digital Input to DGND...............................................-0.3V to +6V
OUTP, OUTN, CREF to AGND .................................-0.3V to +6V
V
REF
to AGND ..........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AV
DD
to DVDD.....................................................................±3.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T
A
= +70°C)
24-Pin QSOP (derate 9.50mW/°C above +70°C)........762mW
Operating Temperature Ranges
MAX5187BEEG/MAX5190BEEG ....................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
f
OUT
= 2.2MHz, TA= +25°C
f
OUT
= 550kHz
f
OUT
= 2.2MHz, TA= +25°C
f
OUT
= 550kHz
f
OUT
= 2.2MHz, TA= +25°C
ANALOG OUTPUT
DYNAMIC PERFORMANCE
STATIC PERFORMANCE
Full-Scale Output Current I
FS
0.5 1 1.5
mA
DAC External Output Resistor
Load
R
L
400
Ω
MAX5187 only
MAX5187 only
PARAMETER SYMBOL MIN TYP MAX UNITS
Full-Scale Error
-20 ±4 +20
LSB
Zero-Scale Error
-4 +4
LSB
Differential Nonlinearity DNL
-1 ±0.25 +1
LSB
Output Settling Time
25
ns
Glitch Impulse
10
pVs
Spurious-Free Dynamic Range
to Nyquist
SFDR
72
dBc
57 70
Resolution N
8
Bits
Integral Nonlinearity INL
-1 ±0.25 +1
LSB
Total Harmonic Distortion
to Nyquist
THD
-70
dB
-68 -63
Signal-to-Noise Ratio
to Nyquist
SNR
52
dB
46 52
Clock and Data Feedthrough
50
nVs
Output Noise
10
pA/√Hz
Full-Scale Output Voltage V
FS
400
mV
Voltage Compliance of Output
-0.3 0.8
V
Output Leakage Current
-1 1
µA
CONDITIONS
(Note 1)
MAX5191
Guaranteed monotonic
To ±0.5LSB error band
All 0s to all 1s
DACEN = 0, MAX5187 only
MAX5182
-1 +1
STATIC PERFORMANCE
DYNAMIC PERFORMANCE
ANALOG OUTPUT
f
OUT
= 550kHz
f
CLK
= 40MHz
f
CLK
= 40MHz
f
CLK
= 40MHz
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= +3V ±10%, AGND = DGND = 0, f
CLK
= 40MHz, IFS= 1mA, 400Ω differential output, CL= 5pF, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
PD = 1, DACEN = X, digital inputs at 0
or DV
DD
(X = don’t care)
PD = 0, DACEN = 0, digital inputs at 0
or DV
DD
PD = 0, DACEN = 1, digital inputs at 0
or DV
DD
PD = 0, DACEN = 1, digital inputs at 0
or DV
DD
µA
0.5 1
I
SHDN
Shutdown Current
mA
1 1.5
I
STANDBY
Standby Current
mA
4.2 5
I
DVDD
Digital Supply Current
V
2.7 3.3
DV
DD
Digital Power-Supply Voltage
mA
1.7 4
I
AVDD
Analog Supply Current
V
2.7 3.3
AV
DD
Analog Power-Supply Voltage
mA/mA
8
Current Gain (IFS/ I
REF
)
mV/V
0.5
Reference Supply Rejection
µA
10
I
REFOUT
Reference Output Drive
Capability
ppm/°C
50
TCV
REF
Output Voltage Temperature
Drift
V
1.12 1.2 1.28
V
REF
Output Voltage Range
VIN= 0 or DV
DD
ns
0
t
DH
DAC CLK Rise to DATA
Hold Time
ns
10
t
DS
DAC DATA to CLK Rise
Setup Time
pF
10
C
IN
Digital Input Capacitance
µA
±1
I
IN
Digital Input Current
V
0.8
V
IL
Digital Input Voltage Low
V
2
V
IH
Digital Input Voltage High
ns
10
t
CL
Clock Low Time
ns
10
t
CH
Clock High Time
ns
25
t
CLK
Clock Period
µs
50
PD Fall Time to V
OUT
µs
0.5
DACEN Rise Time to V
OUT
ns
5
CS Fall to CLK Fall Time
ns
5
CS Fall to CLK Rise Time
REFERENCE
POWER REQUIREMENTS
LOGIC INPUTS AND OUTPUTS
TIMING CHARACTERISTICS
Note 1: Excludes reference and reference resistor (MAX5190) tolerance.
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
4 _______________________________________________________________________________________
Typical Operating Characteristics
(AVDD= DVDD= +3V, AGND = DGND = 0, 400Ω differential output, IFS= 1mA, CL= 5pF, TA= +25°C, unless otherwise noted.)
3.0
2.5
1.5
2.0
1.0
-40 35-15 10 60 85
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX5187/90-04
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT (mA)
MAX5187
MAX5190
8
7
6
5
4
3
2.5 4.03.0 3.5 4.5 5.0 5.5
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5187/90-05
SUPPLY VOLTAGE (V)
DIGITAL SUPPLY CURRENT (mA)
MAX5190
MAX5187
4.00
3.75
3.25
3.50
3.00
-40 35-15 10 60 85
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
MAX5187/90-06
TEMPERATURE (°C)
DIGITAL SUPPLY CURRENT (mA)
MAX5190
MAX5187
610
600
590
580
570
2.5 4.03.0 3.5 4.5 5.0 5.5
STANDBY CURRENT
vs. SUPPLY VOLTAGE
MAX5187/90-07
SUPPLY VOLTAGE (V)
STANDBY CURRENT (µA)
MAX5190
MAX5187
600
590
570
560
580
550
-40 35-15 10 60 85
STANDBY CURRENT
vs. TEMPERATURE
MAX5187/90-08
TEMPERATURE (°C)
STANDBY CURRENT (µA)
MAX5190
MAX5187
0.14
0.12
0.10
0.06
0.08
0.04
2.5 4.03.0 3.5 4.5 5.0 5.5
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX5187/90-09
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (µA)
MAX5190
MAX5187
INTEGRAL NONLINEARITY
vs. INPUT CODE
0.150
0.125
0.100
0.075
0.050
INL (LSB)
0.025
0
-0.025
-0.050
0 32 64 96 128 160 192 224 256
INPUT CODE
MAX5187/90-01
DNL (LSB)
-0.075
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
0.100
0.075
0.050
0.025
0
-0.025
-0.050
0 32 64 96 128 160 192 224 256
INPUT CODE
3.0
MAX5187/90-02
2.5
2.0
1.5
ANALOG SUPPLY CURRENT (mA)
1.0
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5190
2.5 4.03.0 3.5 4.5 5.0 5.5
MAX5187
SUPPLY VOLTAGE (V)
MAX5187/90-03
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(AVDD= DVDD= +3V, AGND = DGND = 0, 400Ω differential output, IFS= 1mA, CL= 5pF, TA= +25°C, unless otherwise noted.)
4
3
1
2
0
0 300100 200 400 500
OUTPUT CURRENT
vs. REFERENCE CURRENT
MAX5187/90-13
REFERENCE CURRENT (µA)
OUTPUT CURRENT (mA)
DYNAMIC RESPONSE RISE TIME
MAX5187/90-14
50ns/div
OUTP
150mV/
div
OUTN
150mV/
div
DYNAMIC RESPONSE FALL TIME
MAX5187/90-15
50ns/div
OUTP
150mV/
div
OUTN
150mV/
div
SETTLING TIME
MAX5187/90-16
12.5ns/div
OUTN
100mV/
div
OUTP
100mV/
div
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0246
81012141618
20
FFT PLOT
MAX5187/90-17
OUTPUT FREQUENCY (MHz)
(dBc)
f
OUT
= 2.2MHz
f
CLK
= 40MHz
SHUTDOWN CURRENT
vs. TEMPERATURE
0.13
0.11
0.09
0.07
SHUTDOWN CURRENT (µA)
0.05
0.03
MAX5190
MAX5187
-40 35-15 10 60 85
TEMPERATURE (°C)
1.28
MAX5187/90-10
1.27
1.26
1.25
REFERENCE VOLTAGE (V)
1.24
1.23
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX5187/90-11
MAX5190
MAX5187
REFERENCE VOLTAGE (V)
2.5 4.03.0 3.5 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
1.28
1.27
1.26
MAX5187
1.25
1.24
1.23
-40 35-15 10 60 85
MAX5190
TEMPERATURE (°C)
MAX5187/90-12
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD= DVDD= +3V, AGND = DGND = 0, 400Ω differential output, IFS= 1mA, CL= 5pF, TA= +25°C, unless otherwise noted.)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0 2.5 5 7.5
10 12.5 15 2017.5
MULTITONE SPURIOUS-FREE DYNAMIC
RANGE vs. OUTPUT FREQUENCY
MAX5187/90-21
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
60
62
64
66
68
70
72
74
0.50 0.75 1.00 1.25 1.50
SPURIOUS-FREE DYNAMIC RANGE
vs. FULL-SCALE OUTPUT CURRENT
MAX5187/90-22
FULL-SCALE OUTPUT CURRENT (mA)
SFDR (dBc)
100
90
70
60
50
80
40
0 20253035404550556015
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
MAX5187/90-18
CLOCK FREQUENCY (MHz)
SFDR (dBc)
78
76
74
72
SFDR (dBc)
70
68
66
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT
FREQUENCY AND CLOCK FREQUENCY
f
= 50MHz f
OUT
f
OUT
500 1100 1300700 900 1500 1700 1900 2100 2300
= 20MHz
OUT
= 10MHz
f
= 60MHz
OUT
f
OUT
OUTPUT FREQUENCY (kHz)
= 30MHz
OUT
= 40MHzf
MAX5187/90-19
SIGNAL-TO-NOISE PLUS DISTORTION
vs. OUTPUT FREQUENCY
62.4
62.2
62.0
61.8
61.6
SINAD (dB)
61.4
61.2
61.0
60.8
0 1500500 1000 2000 2500
OUPUT FREQUENCY (kHz)
MAX5187/90-20
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________ 7
Pin Description
14–19 D1–D6 Data Bit D1–D6
20 D7 Data Bit D7 (MSB)
21 DV
DD
Digital Supply, +2.7V to +3.3V
24 REFO Reference Output
23 REFR Reference Input
NAME FUNCTION
1 CREF Reference Bias Bypass
2 OUTP Positive Analog Output. Current output for MAX5187; voltage output for MAX5190.
PIN
3 OUTN Negative Analog Output. Current output for MAX5187; voltage output for MAX5190.
4 AGND Analog Ground
7 PD
Power-Down Select
0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DVDD)
1: Enter shutdown mode
6 DACEN
DAC Enable, Digital Input
0: Enter DAC standby mode with PD = DGND
1: Power-up DAC with PD = DGND
X: Enter shutdown mode with PD = DV
DD
(X = don’t care)
5 AV
DD
Analog Positive Supply, +2.7V to +3.3V
13 D0 Data Bit D0 (LSB)
11, 12, 22 DGND Digital Ground
10
REN
Active-Low Reference Enable. Connect to DGND to activate on-chip +1.2V reference.
9 CLK Clock Input
8
CS
Active-Low Chip Select
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
8 _______________________________________________________________________________________
Detailed Description
The MAX5187/MAX5190 are 8-bit DACs capable of
operating with clock speeds up to 40MHz. Each converter consists of separate input and DAC registers, followed by a current-source array capable of generating
up to 1.5mA full-scale output current (Figure 1). An integrated +1.2V voltage reference and control amplifier
determine the data converters’ full-scale output currents/voltages. Careful reference design ensures close
gain matching and excellent drift characteristics. The
MAX5190’s voltage-output operation features matched
400Ω on-chip resistors that convert the current array
current into a voltage.
Internal Reference
and Control Amplifier
The MAX5187/MAX5190 provide an integrated
50ppm/°C, +1.2V, low-noise bandgap reference that
can be disabled and overridden by an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is
connected to DGND, the internal reference is selected
and REFO provides a +1.2V output. Due to its limited
10µA output drive capability, REFO must be buffered
with an external amplifier if heavier loading is required.
The MAX5187/MAX5190 also employ a control amplifier, designed to simultaneously regulate the full-scale
output current (I
FS
) for both outputs of the devices. The
output current is calculated as follows:
I
FS
= 8 x I
REF
where I
REF
is the reference output current (I
REF
=
V
REFO / RSET
) and IFSis the full-scale output current.
R
SET
is the reference resistor that determines the
amplifier’s output current on the MAX5187 (Figure 2).
This current is mirrored into the current-source array,
where it is equally distributed between matched current
segments and summed to valid output current readings
for the DACs.
The MAX5190 converts this output current into a differential output voltage (V
OUT
) with two internal, ground-
referenced 400Ω load resistors. Using the internal
+1.2V reference voltage, the MAX5190’s integrated
reference output current resistor (R
SET
= 9.6kΩ) sets
I
REF
to 125µA and IFSto 1mA.
Figure 1. Functional Diagram
REN
1.2V REF
REFO
REFR
9.6k*
CLK
*INTERNAL 400Ω AND 9.6kΩ
RESISTORS FOR MAX5190 ONLY.
AV
DAC SWITCHES
OUTPUT
LATCHES
MSB DECODE
INPUT
LATCHES
AGND CS DACEN PD
DD
CURRENT-
SOURCE ARRAY
OUTPUT
LATCHES
MSB DECODE
INPUT
LATCHES
D7–D0
400Ω
MAX5187
MAX5190
DV
DD
CREF
OUTP
OUTN
*
400Ω*
DGND
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________ 9
Figure 3. MAX5187/MAX5190 with External Reference
Figure 2. Setting IFSwith the Internal +1.2V Reference and the Control Amplifier
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
MAX4040
AGND
I
=
REF
*COMPENSATION CAPACITOR (C
REFO
C
*
COMP
V
REF
R
SET
= 100nF) **9.6kΩ REFERENCE CURRENT SET RESISTOR
COMP
AGND
R
SET
REFR
I
REF
R
SET
9.6kΩ
REN
+1.2V
BANDGAP
REFERENCE
**
DV
DGND
CURRENT-
SOURCE ARRAY
MAX5187
MAX5190
INTERNAL TO MAX5190 ONLY. USE EXTERNAL
FOR MAX5188.
R
SET
DD
I
FS
AV
DD
MAX6520
EXTERNAL
+1.21V
REFERENCE
AGND
R
SET
AGND
REFO
REFR
I
REF
REN
+1.21V
BANDGAP
REFERENCE
9.6kΩ*
DGND
MAX5187
MAX5190
*9.6kΩ REFERENCE CURRENT SET RESISTOR
INTERNAL TO MAX5190 ONLY. USE EXTERNAL
FOR MAX5188.
R
SET
0.1µF10µF
CURRENT-
SOURCE ARRAY
I
FS
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
10 ______________________________________________________________________________________
PD
(POWER-DOWN SELECT)
DACEN
(DAC ENABLE)
POWER-DOWN MODE OUTPUT STATE
0 0 Standby
MAX5187 High-Z
MAX5190 AGND
0 1 Wake-Up Last state prior to standby mode
1 X Shutdown
MAX5187 High-Z
MAX5190 AGND
Table 1. Power-Down Mode Selection
X = Don’t care
External Reference
To disable the MAX5187/MAX5190’s internal reference,
connect REN to DVDD. A temperature-stable external reference may now be applied to drive the REFO pin to set
the full-scale output (Figure 3). Choose a reference that
can supply at least 150µA to drive the bias circuit that
generates the cascode current for the current array. For
improved accuracy and drift performance, choose a voltage reference with a fixed output voltage, such as the
+1.2V, 25ppm/°C MAX6520 bandgap reference.
Standby Mode
To enter the lower power standby mode, connect the
digital inputs PD and DACEN to DGND. In standby,
both the reference and the control amplifier are active
with the current array inactive. To exit this condition,
DACEN must be pulled high with PD held at DGND.
Both the MAX5187 and MAX5190 typically require 50µs
to wake up and allow both the outputs and the reference to settle.
Shutdown Mode
For lowest power consumption, the MAX5187/MAX5190
provide a power-down mode in which the reference,
control amplifier, and current array are inactive and the
DAC’s supply current is reduced to 1µA. To enter this
mode, connect PD to DVDD. To return to active mode,
connect PD to DGND and DACEN to DVDD. About 50µs
are required for the parts to leave shutdown mode and
settle to their outputs’ values prior to shutdown.
Timing Information
Figure 4 shows a detailed timing diagram for the
MAX5187/MAX5190. With each high transition of the
clock, the input latch is loaded with the digital value set
by bits D7 through D0. The content of the input latch is
then shifted to the DAC register, and the output
updates at the rising edge of the next clock.
Figure 4. Timing Diagram
t
CLK
CLK
t
CL
t
CH
D0–D7
t
DS
OUT N - 1
N - 1
N
t
DH
N
N + 1
N + 1
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
______________________________________________________________________________________ 11
Outputs
The MAX5187 output is designed to supply full-scale
output currents of 1mA into 400Ω loads in parallel with
a capacitive load of 5pF. The MAX5190 features integrated 400Ω resistors that restore the array current to
proportional, differential voltages of 400mV. These differential output voltages can then be used to drive a
balun transformer or a low-distortion, high-speed operational amplifier to convert the differential voltage into a
single-ended voltage.
Applications Information
Static and Dynamic
Performance Definitions
Integral Nonlinearity
Integral nonlinearity (INL) (Figure 5a) is the deviation of
the values on an actual transfer function from either a
best-straight-line fit (closest approximation to the actual
transfer curve) or a line drawn between the endpoints
of the transfer function once offset and gain errors have
been nullified. For a DAC, the deviations are measured
every single step.
Differential Nonlinearity
Differential nonlinearity (DNL) (Figure 5b) is the difference between an actual step height and the ideal value
of 1LSB. A DNL error specification of less than 1LSB
guarantees no missing codes and a monotonic transfer
function.
Offset Error
Offset error (Figure 5c) is the difference between the
ideal and the actual offset point. For a DAC, the offset
point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated by trimming.
Figure 5a. Integral Nonlinearity
Figure 5b. Differential Nonlinearity
Figure 5c. Offset Error
Figure 5d. Gain Error
7
6
5
4
3
ANALOG OUTPUT VALUE
2
1
0
000 010001 011 100 101 110
AT STEP
001 (1/4 LSB )
DIGITAL INPUT CODE
AT STEP
011 (1/2 LSB )
111
6
5
4
3
2
ANALOG OUTPUT VALUE
1
0
000 010001 011 100 101
1 LSB
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
1 LSB
ACTUAL
OFFSET
POINT
IDEAL OFFSET
POINT
ACTUAL
DIAGRAM
DIGITAL INPUT CODE
3
2
1
ANALOG OUTPUT VALUE
0
000 010001 011
IDEAL DIAGRAM
OFFSET ERROR
(+1 1/4 LSB)
7
6
5
ANALOG OUTPUT VALUE
4
0
000 101100 110 111
IDEAL FULL-SCALE OUTPUT
GAIN ERROR
(-1 1/4 LSB)
IDEAL DIAGRAM
DIGITAL INPUT CODE
ACTUAL
FULL-SCALE
OUTPUT
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
12 ______________________________________________________________________________________
Gain Error
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corresponds to the same percentage error in each step.
Settling Time
Settling time is the amount of time required from the start
of a transition until the DAC output settles its new output
value to within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first four harmonics to the fundamental itself. This is expressed as:
where V
1
is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high-input bandwidth
amplifier may be used to generate a voltage from the
array current output of the MAX5187. The differential
voltage across OUTP and OUTN is converted into a
single-ended voltage by designing an appropriate
operational amplifier configuration (Figure 6).
I/Q Reconstruction in a QAM Application
The low-distortion performance of two MAX5187/
MAX5190s supports analog reconstruction of in-phase
(I) and quadrature (Q) carrier components typically
used in quadrature amplitude modulation (QAM) architectures, where two separate buses carry the I and Q
data. A QAM signal is both amplitude and phase modulated, created by summing two independently modulated carriers of identical frequency but different phase
(90° phase difference).
THD 20 log
VVVV
V
223
242
5
2
1
=×
+++
Figure 6. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier
+3V
+3V
D0–D7
SET
0.1µF
0.1µF
**
10µF
*400Ω RESISTORS INTERNAL TO MAX5190 ONLY.
**MAX5187 ONLY
R
AV
CLK
REFO
REFR
DD
10µF
DV
DD
MAX5187
MAX5190
REN AGNDDGND
0.1µF
CREF
OUTP
OUTN
AV
DD
0.1µF
402Ω
402Ω
400Ω*
402Ω
400Ω*
+5V
OUTPUT
MAX4108
-5V
402Ω
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
______________________________________________________________________________________ 13
In a typical QAM application (Figure 7), the modulation
occurs in the digital domain, and two DACs such as the
MAX5187/MAX5190 may be used to reconstruct the
analog I and Q components.
The I/Q reconstruction system is completed by a quadrature modulator that combines the reconstructed components with in-phase and quadrature carrier
frequencies and then sums both outputs to provide the
QAM signal.
Using the MAX5187/MAX5190 for
Arbitrary Waveform Generation
Designing a traditional AWG requires five major functional blocks (Figure 8a): clock generator, counter,
waveform memory, digital-to-analog converter for
waveform reconstruction, and output filter. The waveform memory contains a sequentially stored digital
replica of the desired analog waveforms. This memory
shares a common clock with the DAC.
For each clock cycle, a counter adds one count to the
address for the waveform memory. The memory then
loads the next value to the DAC, which generates an
analog output voltage corresponding to that data value
until the next clock cycle. A DAC output filter can either
be a simple or complex lowpass filter, depending on
the AWG requirements for waveform function and frequencies. The main limitations of the AWG’s flexibility
are DAC resolution and dynamic performance, memory
length, clock/playback frequency, and filter characteristics.
Although the MAX5187/MAX5190 offer high-frequency
operation and excellent dynamics, they are suitable for
relaxed requirements in resolution (8-bit AWGs). To
increase an AWG’s high-frequency accuracy, temperature stability, wideband tuning, and past phase continuous-frequency switching, the user may approach a
direct digital synthesis (DDS) AWG (Figure 8b). This
DDS loop supports standard waveforms that are repetitive, such as sine, square, TTL, and triangular waveforms. DDS allows for precise control of the data
stream input to the DAC. Data for one complete output
waveform cycle is sequentially stored in RAM. As the
RAM addresses change, the DAC converts the incoming data bits into a corresponding voltage waveform.
The resulting output signal frequency is proportional to
the frequency rate at which the RAM addresses are
changed.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influence the MAX5187/MAX5190’s performance. Unwanted
digital crosstalk may couple through the input, reference,
power-supply, and ground connections, which may
affect dynamic specifications like signal-to-noise ratio or
spurious-free dynamic range. In addition, electromagnet-
Figure 7. Using the MAX5187/MAX5190 for I/Q Signal Reconstruction
AV
DV
DD
+3V
8
DIGITAL
SIGNAL
PROCESSOR
8
DD
MAX5187
MAX5190
AV
DD
MAX5187
MAX5190
I COMPONENT
DV
DD
Q COMPONENT
+3V
BP
FILTER
CARRIER
FREQUENCY
BP
FILTER
0°
90°
MAX2452
QUADRATURE
MODULATOR
IF
Σ
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
14 ______________________________________________________________________________________
ic interference (EMI) can either couple into or be generated by the MAX5187/MAX5190. Therefore, grounding
and power-supply decoupling guidelines for highspeed, high-frequency applications should be closely
followed.
First, a multilayer PC board with separate ground and
power-supply planes is recommended. High-speed
signals should be run on controlled impedance lines
directly above the ground plane. Since the MAX5187/
MAX5190 have separate analog and digital ground
buses (AGND and DGND, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two. Digital
signals should run above the digital ground plane, and
analog signals should run above the analog ground
plane.
Both devices have two power-supply inputs: analog
VDD(AVDD) and digital VDD(DVDD). Each AVDDinput
should be decoupled with parallel 10µF and 0.1µF
ceramic chip capacitors. These capacitors should be
as close to the pin as possible, and their opposite ends
should be as close as possible to the ground plane.
The DVDDpins should also have separate 10µF and
0.1µF capacitors adjacent to their respective pins. Try
to minimize the analog load capacitance for proper
operation. For best performance, bypass with low-ESR
0.1µF capacitors to AVDD.
The power-supply voltages should also be decoupled
with large tantalum or electrolytic capacitors at the
point they enter the PC board. Ferrite beads with additional decoupling capacitors forming a pi-network can
also improve performance.
Figure 8a. Traditional Arbitrary Waveform Generation (AWG)
Figure 8b. Direct Digital Synthesis AWG (DDS AWG)
Chip Information
TRANSISTOR COUNT: 9464
SUBSTRATE CONNECTED TO AGND
AV
DV
DD
COUNTER
CLOCK
GENERATOR
*MAX5187 ONLY
CLOCK
GENERATOR
PIR
PHASE
INCREMENT
REGISTER
A
D
D
E
R
PHASE
ACCUMULATOR
ACCUMULATOR
FEEDBACK LOOP
FOR DATA BITS
ADR
WAVEFORM
MEMORY
(RAM)
WAVEFORM
MEMORY
(RAM)
DD
8ADR
MAX5187
MAX5190
9.6k*
DATA
8
9.6k*
AV
DD
MAX5187
MAX5190
REFR
400Ω*
DV
DD
400Ω*
LOWPASS
RECONSTRUCTION
FILTER
VARIABLE
f
C
LOWPASS
RECONSTRUCTION
FILTER
VARIABLE
f
C
FILTERED
WAVEFORM
(ANALOG OUTPUT)
FILTERED
WAVEFORM
(ANALOG OUTPUT)
*MAX5187 ONLY
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
QSOP.EPS
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