For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX5180 contains two 10-bit, simultaneousupdate, current-output digital-to-analog converters
(DACs) designed for superior performance in communications systems requiring analog signal reconstruction
with low distortion and low-power operation. The
MAX5183 provides equal specifications, with on-chip
precision resistors for voltage output operation. The
devices are designed for 10pVs glitch operation to minimize unwanted spurious signal components at the output. An on-board +1.2V bandgap circuit provides a
well-regulated, low-noise reference that can be disabled for external reference operation.
The MAX5180/MAX5183 are designed to provide a high
level of signal integrity for the least amount of power dissipation. The DACs operate from a single supply of
+2.7V to +3.3V. Additionally, these DACs have three
modes of operation: normal, low-power standby, and
complete shutdown, which provides the lowest possible
power dissipation with 1µA (max) shutdown current. A
fast wake-up time (0.5µs) from standby mode to full DAC
operation conserves power by activating the DACs only
when required.
The MAX5180/MAX5183 are packaged in a 28-pin QSOP
and are specified for the extended (-40°C to +85°C)
temperature range. For lower-resolution, dual 8-bit
versions, refer to the MAX5186/MAX5189 data sheet.
Applications
Signal Reconstruction of I and Q Transmit
Signals
Digital Signal Processing
Arbitrary Waveform Generation (AWG)
Imaging
Features
♦ +2.7V to +3.3V Single-Supply Operation
♦ Wide Spurious-Free Dynamic Range: 70dB
at f
OUT
= 2.2MHz
♦ Fully Differential Outputs for Each DAC
♦ ±0.5% FSR Gain Mismatch
♦ ±0.2° Phase Mismatch
♦ Low-Current Standby or Full-Shutdown Modes
♦ Internal +1.2V Low-Noise Bandgap Reference
♦ Small 28-Pin QSOP Package
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
________________________________________________________________ Maxim Integrated Products 1
19-1577; Rev 3; 12/01
PART
MAX5180BEEI
-40°C to +85°C
TEMP RANGE PIN-PACKAGE
28 QSOP
Pin Configuration
Ordering Information
MAX5183BEEI
-40°C to +85°C 28 QSOP
TOP VIEW
CREF1
OUT1P
OUT1N
AGND
AV
DACEN
CLK
N.C.
REN
1
2
3
4
5
DD
PD
CS
D0
D1
D2
MAX5180
6
MAX5183
7
8
9
10
11
12
13
14
28
CREF2
27
OUT2P
26
OUT2N
25
REFO
24
REFR
23
DGND
22
DV
DD
21
D9
20
D8
19
D7
18
D6
17
D5
16
D4
15
D3
QSOP
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= DVDD= +3V ±10%, AGND = DGND = 0, f
CLK
= 40MHz, IFS= 1mA, 400Ω differential output, CL= 5pF, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDDto AGND, DGND .................................-0.3V to +6V
Digital Inputs to DGND.............................................-0.3V to +6V
OUT1P, OUT1N, OUT2P, OUT2N, CREF1,
CREF2 to AGND ...................................................-0.3V to +6V
V
REF
to AGND ..........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AVDDto DVDD.................................................................... ±3.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T
A
= +70°C)
28-Pin QSOP (derate 9.00mW/°C above +70°C)....... 725mW
Operating Temperature Range
MAX518_BEEI.................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
-8 +8
MAX5183
MAX5180
f
CLK
= 40MHz
DACEN = 0, MAX5180 only
f
OUT
= 2.2MHz
f
OUT
= 2.2MHz, TA=+25°C
All 0s to all 1s
f
OUT
= 2.2MHz
f
CLK
= 40MHz
To ±0.5LSB error band
Guaranteed monotonic
(Note 1)
f
CLK
= 40MHz
CONDITIONS
µA
-1 1
Output Leakage Current
V
-0.3 0.8
Voltage Compliance of Output
mV
400
V
FS
Full-Scale Output Voltage
degrees
±0.15
Phase Mismatch Between
DAC Outputs
%FSR
±0.5 ±1
Gain Mismatch Between
DAC Outputs
pA/√Hz
10
Output Noise
nVs
50
Clock and Data Feedthrough
dB
-60
DAC-to-DAC Output Isolation
59
dB
61
SNRSignal-to-Noise Ratio to Nyquist
-68 -63
dB
-70
THD
Total Harmonic Distortion to
Nyquist
LSB
-2 ±0.5 +2
INLIntegral Nonlinearity
Bits
10
NResolution
57 70
dBc
72
SFDR
Spurious-Free Dynamic Range
to Nyquist
pVs
10
Glitch Impulse
ns
25
Output Settling Time
LSB
-1 ±0.5 +1
DNLDifferential Nonlinearity
LSB
-2 +2
Zero-Scale Error
LSB
-40 ±15 +40
Full-Scale Error
UNITSMIN TYP MAXSYMBOLPARAMETER
MAX5180 only
MAX5180 only
Ω
400
R
L
DAC External Output Resistor
Load
mA
0.5 1 1.5
I
FS
Full-Scale Output Current
f
OUT
= 550kHz
f
OUT
= 2.2MHz, TA=+25°C
f
OUT
= 550kHz
f
OUT
= 2.2MHz, TA=+25°C
f
OUT
= 550kHz
f
OUT
= 2.2MHz, TA=+25°C
DYNAMIC PERFORMANCE
ANALOG OUTPUT
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= +3V ±10%, AGND = DGND = 0, f
CLK
= 40MHz, IFS= 1mA, 400Ω differential output, CL= 5pF, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
PD = 1, DACEN = X, digital inputs at 0
or DV
DD
(X = don’t care)
PD = 0, DACEN = 0, digital inputs at 0
or DV
DD
PD = 0, DACEN = 1, digital inputs at 0
or DV
DD
PD = 0, DACEN = 1, digital inputs at 0
or DV
DD
µA
0.5 1.0
I
SHDN
Shutdown Current
mA
1.0 1.5
I
STANDBY
Standby Current
mA
4.2 5.0
I
DVDD
Digital Supply Current
V
2.7 3.3
DV
DD
Digital Power-Supply Voltage
mA
2.7 5.0
I
AVDD
Analog Supply Current
V
2.7 3.3
AV
DD
Analog Power-Supply Voltage
mA/mA
8
Current Gain (I
FS
/ I
REF
)
mV/V
0.5
Reference Supply Rejection
µA
10
I
REFOUT
Reference Output Drive
Capability
ppm/°C
50
TCV
REF
Output Voltage Temperature
Drift
V
1.12 1.2 1.28
V
REF
Output Voltage Range
VIN= 0 or DV
DD
ns
0
t
DH2
DAC2 CLK Fall to DATA
Hold Time
ns
0
t
DH1
DAC1 CLK Rise to DATA
Hold Time
ns
10
t
DS2
DAC2 DATA to CLK Fall
Setup Time
ns
10
t
DS1
DAC1 DATA to CLK Rise
Setup Time
pF
10
C
IN
Digital Input Capacitance
µA
±1
I
IN
Digital Input Current
V
0.8
V
IL
Digital Input Voltage Low
V
2
V
IH
Digital Input Voltage High
ns
10
t
CL
Clock Low Time
ns
10
t
CH
Clock High Time
ns
25
t
CP
Clock Period
µs
50
PD Fall Time to V
OUT_
µs
0.5
DACEN Rise Time to V
OUT_
ns
5
CS Fall to CLK Fall Time
ns
5
CS Fall to CLK Rise Time
REFERENCE
POWER REQUIREMENTS
LOGIC INPUTS AND OUTPUTS
TIMING CHARACTERISTICS
1.5
2.0
3.0
2.5
3.5
4.0
-40 -15 10 35 60 85
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX5180/83-04
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT (mA)
MAX5180
MAX5183
0
2
6
4
8
10
2.5 3.53.0 4.0 4.5 5.0 5.5
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5180/83-05
SUPPLY VOLTAGE (V)
DIGITAL SUPPLY CURRENT (mA)
MAX5183
MAX5180
0
1
3
2
4
5
-40 -15 10 35 60 85
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
MAX5180/83-06
TEMPERATURE (°C)
DIGITAL SUPPLY CURRENT (mA)
MAX5180
MAX5183
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
0 128 256 384 512 640 768 896 1024
INTEGRAL NONLINEARITY
vs. INPUT CODE
MAX5180/83-01
INPUT CODE
INL (LSB)
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0 128 256 384 512 640 768 896 1024
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
MAX5180/83-02
INPUT CODE
DNL (LSB)
2.45
2.47
2.51
2.49
2.53
2.55
2.5 3.53.0 4.0 4.5 5.0 5.5
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5180/83-03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
MAX5180
MAX5183
560
570
590
580
600
610
2.5 3.53.0 4.0 4.5 5.0 5.5
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX5180/83-07
SUPPLY VOLTAGE (V)
STANDBY CURRENT (µA)
MAX5183
MAX5180
540
560
550
580
570
590
600
-40 10-15 35 60 85
STANDBY CURRENT vs. TEMPERATURE
MAX5180/83-08
TEMPERATURE (°C)
STANDBY CURRENT (µA)
MAX5180
MAX5183
0.45
0.55
0.50
0.60
0.65
0.70
0.75
0.80
2.5 3.53.0 4.5
4.0
5.0 5.5
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
MAX5180/83-09
SUPPLY VOLTAGE (V)
SHUITDOWN CURRENT (µA)
MAX5180
MAX5183
Typical Operating Characteristics
(AVDD= DVDD= +3V, AGND = DGND = 0, 400Ω differential output, IFS= 1mA, CL= 5pF, TA= +25°C, unless otherwise noted.)
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
4 _______________________________________________________________________________________
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(AVDD= DVDD= +3V, AGND = DGND = 0, 400Ω differential output, IFS= 1mA, CL= 5pF, TA= +25°C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.28
1.27
1.26
1.25
REFERENCE VOLTAGE (V)
1.24
1.23
2.5 3.53.0 4.0 4.5 5.0 5.5
DYNAMIC RESPONSE RISE TIME
MAX5180
MAX5183
SUPPLY VOLTAGE (V)
1.28
MAX5180/83-10
1.27
1.26
1.25
REFERENCE VOLTAGE (V)
1.24
1.23
MAX5180/83-13
OUT_P
150mV/div
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX5183
MAX5180
-40 -15 10 35 60 85
TEMPERATURE (°C)
DYNAMIC RESPONSE FALL TIME
MAX5180/83-11
OUTPUT CURRENT (mA)
MAX5180/83-14
OUT_P
150mV/div
OUTPUT CURRENT vs. REFERENCE CURRENT
4
3
2
1
0
0 200100 400
REFERENCE CURRENT (µA)
300
SETTLING TIME
MAX5180/83-12
500
MAX5180/83-15
OUT_N
100mV/div
0
-10
-20
-30
-40
-50
-60
(dBc)
-70
-80
-90
-100
-110
-120
0246
OUT_N
150mV/div
12.5ns/div
50ns/div
OUT_N
150mV/div
50ns/div
SPURIOUS-FREE DYNAMIC RANGE
FFT PLOT, DAC1
f
f
81012141618
FREQUENCY (MHz)
OUT
CLK
= 2.2MHz
= 40MHz
20
MAX5180/83-16
0
-10
-20
-30
-40
-50
-60
(dBc)
-70
-80
-90
-100
-110
-120
0246
FFT PLOT, DAC2
81012141618
FREQUENCY (MHz)
f
OUT
f
CLK
= 2.2MHz
= 40MHz
MAX5180/83-17
20
100
90
80
70
SFDR (dBc)
60
50
40
vs. CLOCK FREQUENCY
DAC2
DAC1
10 302515 20 35 40 45 50 55 60
CLOCK FREQUENCY (MHz)
OUT_P
100mV/div
MAX5180/83-18
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD= DVDD= +3V, AGND = DGND = 0, 400Ω differential output, IFS= 1mA, CL= 5pF, TA= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT
FREQUENCY AND CLOCK FREQUENCY, DAC1
78
76
74
72
SFDR (dBc)
70
68
66
500 1100 1300700 900 1500 1700 1900 2100 2300
f
= 60MHz
CLK
f
= 40MHz
CLK
f
= 50MHz
CLK
f
CLK
OUTPUT FREQUENCY (kHz)
f
= 10MHz
f
CLK
= 20MHz
CLK
= 30MHz
MAX5180/83-19
78
76
74
72
SFDR (dBc)
70
68
66
FREQUENCY AND CLOCK FREQUENCY, DAC2
f
= 50MHz f
CLK
f
CLK
500 1100 1300700 900 1500 1700 1900 2100 2300
= 20MHz
CLK
= 10MHz
f
= 60MHz
CLK
f
CLK
OUTPUT FREQUENCY (kHz)
= 30MHz
CLK
= 40MHzf
MAX5180/83-20
SIGNAL-TO-NOISE PLUS DISTORTION
vs. OUTPUT FREQUENCY
62.5
62.0
61.5
SINAD (dB)
61.0
60.5
60.0
0 1500500 1000 2000 2500
OUPUT FREQUENCY (kHz)
DAC1
MAX5180/83-21
DAC2
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
20
0
-20
-40
-60
-80
SFDR (dBc)
-100
-120
-140
-160
0105 15202530
OUTPUT FREQUENCY (MHz)
MAX5180/83-22
MULITONE SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
20
0
-20
-40
-60
SFDR (dBc)
-80
-100
-120
-140
06421081412 1816 20
OUTPUT FREQUENCY (MHz)
MAX5180/83-23
SPURIOUS-FREE DYNAMIC RANGE
vs. FULL-SCALE OUTPUT CURRENT
74
72
70
68
SFDR (dBc)
66
64
62
60
0.5 0.75 1 1.25 1.5
FULL-SCALE OUTPUT CURRENT (mA)
MAX5180/83-24
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
_______________________________________________________________________________________ 7
Clock InputCLK9
No Connect. Do not connect to this pin.N.C.10
Active-Low Reference Enable. Connect to DGND to activate on-chip +1.2V reference.
REN
11
Data Bit D0 (LSB)D012
Data Bits D1–D8D1–D813–20
Analog Positive Supply, +2.7V to +3.3VAV
DD
5
DAC Enable, Digital Input
0: Enter DAC standby mode with PD = DGND
1: Power-up DAC with PD = DGND
X: Enter shutdown mode with PD = DV
DD
(X = don’t care)
DACEN6
Power-Down Select
0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DVDD)
1: Enter shutdown mode.
PD7
Active-Low Chip Select
CS
8
Analog GroundAGND4
Negative Analog Output, DAC1. Current output for MAX5180; voltage output for MAX5183.OUT1N3
PIN
Positive Analog Output, DAC1. Current output for MAX5180; voltage output for MAX5183.OUT1P2
Reference Bias Bypass, DAC1CREF11
FUNCTIONNAME
Reference OutputREFO25
Negative Analog Output, DAC2. Current output for MAX5180; voltage output for MAX5183.OUT2N26
Positive Analog Output, DAC2. Current output for MAX5180; voltage output for MAX5183.OUT2P27
Reference Bias Bypass, DAC2CREF228
Reference InputREFR24
Digital GroundDGND23
Digital Supply, +2.7V to +3.3VDV
DD
22
Data Bit D9 (MSB)D921
______________________________________________________________Pin Description
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
8 _______________________________________________________________________________________
Detailed Description
The MAX5180/MAX5183 are dual, 10-bit digital-to-analog converters (DACs) capable of operating with clock
speeds up to 40MHz. Each of these dual converters
consists of separate input and DAC registers, followed
by a current source array capable of generating up to
1.5mA full-scale output current (Figure 1). An integrated +1.2V voltage reference and control amplifier determine the data converters’ full-scale output currents/
voltages. Careful reference design ensures close gain
matching and excellent drift characteristics. The
MAX5183’s voltage output operation features matched
400Ω on-chip resistors that convert the current array
current into a voltage.
Internal Reference and Control Amplifier
The MAX5180/MAX5183 provide an integrated
50ppm/°C, +1.2V, low-noise bandgap reference that
can be disabled and overridden by an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is
connected to AGND, the internal reference is selected
and REFO provides a +1.2V output. Due to its limited
10µA output drive capability, REFO must be buffered
with an external amplifier, if heavier loading is required.
The MAX5180/MAX5183 also employ a control amplifier
designed to simultaneously regulate the full-scale output current (I
FS
) for both outputs of the devices. The
output current is calculated as follows:
I
FS
= 8 × I
REF
where I
REF
is the reference output current (I
REF
=
V
REFO/RSET
) and IFSis the full-scale output current.
R
SET
is the reference resistor that determines the
amplifier’s output current on the MAX5180 (Figure 2).
This current is mirrored into the current-source array
where it is equally distributed between matched current
segments and summed to valid output current readings
for the DACs.
The MAX5183 converts each output current (DAC1 and
DAC2) into an output voltage (V
OUT1
, V
OUT2
) with two
internal, ground-referenced 400Ω load resistors. Using
the internal +1.2V reference voltage, the MAX5183’s
integrated reference output current resistor (R
SET
=
9.6kΩ) sets I
REF
to 125µA and IFSto 1mA.
Figure 1. Functional Diagram
REN
1.2V REF
REFO
REFR
*
9.6k
CLK
*INTERNAL 400Ω AND 9.6kΩ
RESISTORS FOR MAX5183 ONLY.
AV
DAC 1 SWITCHES
DAC 2 SWITCHES
OUTPUT
LATCHES
MSB DECODE
INPUT
LATCHES
AGND DACEN PD
DD
CURRENT-
SOURCE ARRAY
OUTPUT
LATCHES
MSB DECODE
LATCHES
D9–D0
CS
INPUT
CREF1
CREF2
OUT1P
OUT1N
OUT2P
OUT2N
*
*
*
*
400Ω
MAX5180
MAX5183
DV
DD
400Ω
400Ω
DGND
400Ω
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
_______________________________________________________________________________________ 9
Figure 3. MAX5180/MAX5183 with External Reference
Figure 2. Setting IFSwith the Internal +1.2V Reference and the Control Amplifier
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
MAX4040
REFERENCE
REFO
C
*
AGND
I
REF
*COMPENSATION CAPACITOR (C
**9.6kΩ REFERENCE CURRENT-SET RESISTOR
INTERNAL TO MAX5183 ONLY. USE EXTERNAL
FOR MAX5180.
R
SET
COMP
≈ 100nF).
COMP
V
REF
=
R
SET
AGND
R
SET
REFR
I
REF
R
**
SET
9.6k
AV
REN
+1.2V
BANDGAP
DD
AGND
MAX5180
MAX5183
I
CURRENT-
SOURCE ARRAY
0.1µF10µF
FS
AV
DD
EXTERNAL
+1.2V
REFERENCE
MAX6520
*9.6kΩ REFERENCE CURRENT-SET RESISTOR
INTERNAL TO MAX5183 ONLY. USE EXTERNAL
FOR MAX5180.
R
SET
AGND
AGND
REFO
REFR
I
REF
R
SET
R
9.6k
SET
REN
+1.2V
BANDGAP
REFERENCE
*
MAX5180
MAX5183
AGND
CURRENT-
SOURCE ARRAY
I
FS
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
10 ______________________________________________________________________________________
PD
(POWER-DOWN SELECT)
DACEN
(DAC ENABLE)
POWER-DOWN MODE OUTPUT STATE
0 0 Standby
MAX5180 High-Z
MAX5183 AGND
0 1 Wake-Up Last state prior to standby mode
1 X Shutdown
MAX5180 High-Z
MAX5183 AGND
Table 1. Power-Down Mode Selection
X = Don’t care
External Reference
To disable the MAX5180/MAX5183’s internal reference,
connect REN to AVDD. A temperature-stable, external
reference may now be applied to drive the REFO pin to
set the full-scale output (Figure 3). Choose a reference
capable of supplying at least 150µA to drive the bias
circuit that generates the cascode current for the current array. For improved accuracy and drift performance, choose a fixed output voltage reference such
as the +1.2V, 25ppm/°C MAX6520 bandgap reference.
Standby Mode
To enter the lower power standby mode, connect digital
inputs PD and DACEN to DGND. In standby, both the
reference and the control amplifier are active with the
current array inactive. To exit this condition, DACEN
must be pulled high with PD held at DGND. Both the
MAX5180 and MAX5183 typically require 50µs to wake
up and allow both the outputs and the reference to settle.
Shutdown Mode
For lowest power consumption, the MAX5180/MAX5183
provide a power-down mode in which the reference,
control amplifier, and current array are inactive and the
DAC supply current is reduced to 1µA. To enter this
mode, connect PD to DVDD. To return to active mode,
connect PD to DGND and DACEN to DVDD. Table 1
lists the power-down mode selection. About 50µs are
required for the parts to leave shutdown mode and settle to their outputs’ values prior to shutdown.
Timing Information
Both DAC cells in the MAX5180/MAX5183 write to their
outputs simultaneously (Figure 4). The input latch of the
first DAC (DAC1) is loaded after the clock signal transitions high. When the clock signal transitions low, the
input latch of the second DAC (DAC2) is loaded.
Simultaneously at the rising edge of the next clock, the
contents of both input latches are shifted to the DAC
registers and their outputs are updated.
Figure 4. Timing Diagram
t
CP
CLK
D0–D9
N - 1
DAC1 DAC2 DAC1 DAC2 DAC1 DAC2
N - 1
t
CL
N
N
t
CH
N + 1 N + 1
t
DS1
OUT1 N - 2
OUT2 N - 2 N - 1 N
t
DS2
t
DH1
t
DH2
N - 1
N
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
______________________________________________________________________________________ 11
Outputs
The MAX5180 outputs are designed to supply full-scale
output currents of 1mA into 400Ω loads in parallel with
a capacitive load of 5pF. The MAX5183 features integrated 400Ω resistors that restore the array currents to
proportional, differential voltages of 400mV. These differential output voltages can then be used to drive a
balun transformer or a low-distortion, high-speed operational amplifier to convert the differential voltage into a
single-ended voltage.
Applications Information
Static and Dynamic Performance
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) (Figure 5a) is the deviation of
the values on an actual transfer function from either a
best-straight-line fit (closest approximation to the actual
transfer curve) or a line drawn between the endpoints
of the transfer function once offset and gain errors have
been nullified. For a DAC, the deviations are measured
every single step.
Differential Nonlinearity
Differential nonlinearity (DNL) (Figure 5b) is the difference between an actual step height and the ideal value
of 1LSB. A DNL error specification of less than 1LSB
guarantees no missing codes and a monotonic transfer
function.
Offset Error
Offset error (Figure 5c) is the difference between the
ideal and the actual offset point. For a DAC, the offset
point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated by trimming.
Figure 5a. Integral Nonlinearity
Figure 5b. Differential Nonlinearity
Figure 5c. Offset Error
Figure 5d. Gain Error
7
6
5
4
3
ANALOG OUTPUT VALUE
2
1
0
000 010001 011 100 101 110
AT STEP
001 (1/4 LSB )
DIGITAL INPUT CODE
AT STEP
011 (1/2 LSB )
111
6
5
4
3
2
ANALOG OUTPUT VALUE
1
0
000 010001 011 100 101
1 LSB
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
1 LSB
ACTUAL
OFFSET
POINT
IDEAL OFFSET
POINT
ACTUAL
DIAGRAM
DIGITAL INPUT CODE
3
2
1
ANALOG OUTPUT VALUE
0
000 010001 011
IDEAL DIAGRAM
OFFSET ERROR
(+1 1/4 LSB)
7
6
5
ANALOG OUTPUT VALUE
4
0
000 101100 110 111
IDEAL FULL-SCALE OUTPUT
GAIN ERROR
(-1 1/4 LSB)
IDEAL DIAGRAM
DIGITAL INPUT CODE
ACTUAL
FULL-SCALE
OUTPUT
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
12 ______________________________________________________________________________________
Gain Error
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve after nullifying the offset error. This error
alters the slope of the transfer function and corresponds to the same percentage error in each step.
Settling Time
Settling time is the amount of time required from the start
of a transition until the DAC output settles its new output
value to within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first four harmonics to the fundamental itself. This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion
component.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high-input bandwidth
amplifier may be used to generate a voltage from the
array current output of the MAX5180. The differential
voltage across OUT1P (or OUT2P) and OUT1N (or
OUT2N) is converted into a single-ended voltage by
designing an appropriate operational amplifier configuration (Figure 6).
I/Q Reconstruction in a QAM Application
The MAX5180/MAX5183’s low-distortion supports analog reconstruction of in-phase (I) and quadrature (Q)
carrier components typically used in QAM (quadrature
amplitude modulation) architectures where I and Q
data are interleaved on a common data bus. A QAM
signal is a carrier frequency that is both amplitude and
phase modulated, and is created by summing two
independently modulated carriers of identical frequency
but different phase (90° phase difference).
In a typical QAM application (Figure 7), the modulation
occurs in the digital domain and the MAX5180/
MAX5183’s dual DACs may be used to reconstruct the
analog I and Q components.
The I/Q reconstruction system is completed by a quadrature modulator that combines the reconstructed I and
Q components with in-phase and quadrature phase
carrier frequencies, then sums both outputs to provide
the QAM signal.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influence the MAX5180/MAX5183’s performance. Unwanted
digital crosstalk may couple through the input, reference, power-supply, and ground connections, which
may affect dynamic specifications like signal-to-noise
ratio or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or
be generated by the MAX5180/MAX5183. Therefore,
grounding and power-supply decoupling guidelines for
high-speed, high-frequency applications should be
closely followed.
First, a multilayer pc board with separate ground and
power-supply planes is recommended. High-speed
signals should be run on controlled impedance lines
directly above the ground plane. Since the MAX5180/
MAX5183 have separate analog and digital ground
buses (AGND and DGND, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two. Digital
signals should run above the digital ground plane, and
analog signals should run above the analog ground
plane.
Both devices have two power-supply inputs: analog
VDD(AVDD) and digital VDD(DVDD). Each AVDDinput
should be decoupled with parallel 10µF and 0.1µF
ceramic-chip capacitors. These capacitors should be as
close to the pin as possible, and their opposite ends
should be as close to the ground plane as possible. The
DVDDpins should also have separate 10µF and 0.1µF
capacitors adjacent to their respective pins. Try to minimize analog load capacitance for proper operation. For
best performance, it is recommended to bypass CREF1
and CREF2 with low-ESR 0.1µF capacitors to AVDD.
THD
VVVV
V
=×
+++
20
2232425
2
1
log
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
______________________________________________________________________________________ 13
The power-supply voltages should also be decoupled
with large tantalum or electrolytic capacitors at the
point they enter the PC board. Ferrite beads with additional decoupling capacitors forming a pi network can
also improve performance.
Chip Information
TRANSISTOR COUNT: 9464
SUBSTRATE CONNECTED TO AGND
Figure 6. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier
+3V
+3V
10µF
R
SET
D0–D9
0.1µF
**
0.1µF
AV
CLK
REFO
REFR
AVDDAV
DD
10µF
DD
MAX5180
MAX5183
REN
0.1µF
0.1µF
DV
CREF1
DD
CREF2
OUT1P
OUT1N
OUT2P
OUT2N
AGNDDGND
400Ω*
400Ω*
400Ω*
400Ω*
0.1µF
402Ω
402Ω
402Ω
402Ω
402Ω
+5V
OUTPUT1
MAX4108
-5V
402Ω
402Ω
+5V
OUTPUT2
MAX4108
-5V
402Ω
*400Ω RESISTORS INTERNAL TO MAX5183 ONLY.
**MAX5180 ONLY
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
14 ______________________________________________________________________________________
Figure 7. Using the MAX5180/MAX5183 for I/Q Signal Reconstruction
+3V
DIGITAL
SIGNAL
PROCESSOR
+3V
DAC1
MAX5180
MAX5183
DAC2
I COMPONENT
Q COMPONENT
BP
FILTER
CARRIER
FREQUENCY
BP
FILTER
0°
QUADRATURE
MODULATOR
90°
+3V
IF
Σ
MAX2452
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
MAX5180/MAX5183
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
QSOP.EPS
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