_______________General Description
The MAX517/MAX518/MAX519 are 8-bit voltage output
digital-to-analog converters (DACs) with a simple 2-wire
serial interface that allows communication between
multiple devices. They operate from a single 5V supply
and their internal precision buffers allow the DAC outputs to swing rail-to-rail.
The MAX517 is a single DAC and the MAX518/MAX519
are dual DACs. The MAX518 uses the supply voltage
as the reference for both DACs. The MAX517 has a reference input for its single DAC and each of the
MAX519’s two DACs has its own reference input.
The MAX517/MAX518/MAX519 feature a serial interface
and internal software protocol, allowing communication
at data rates up to 400kbps. The interface, combined
with the double-buffered input configuration, allows the
DAC registers of the dual devices to be updated individually or simultaneously. In addition, the devices can
be put into a low-power shutdown mode that reduces
supply current to 4µA. Power-on reset ensures the DAC
outputs are at 0V when power is initially applied.
The MAX517/MAX518 are available in space-saving 8pin DIP and SO packages. The MAX519 comes in 16pin DIP and SO packages.
________________________Applications
Minimum Component Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Automatic Test Equipment
Programmable Attenuators
____________________________Features
♦ Single +5V Supply
♦ Simple 2-Wire Serial Interface
♦ I2C Compatible
♦ Output Buffer Amplifiers Swing Rail-to-Rail
♦ Space-Saving 8-pin DIP/SO Packages
(MAX517/MAX518)
♦ Reference Input Range Includes Both Supply Rails
(MAX517/MAX519)
♦ Power-On Reset Clears All Latches
♦ 4µA Power-Down Mode
______________Ordering Information
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
________________________________________________________________ Maxim Integrated Products 1
_________________Pin Configurations
INPUT
LATCH 0
OUTPUT
LATCH 0
START/STOP
DETECTOR
DAC0
INPUT
LATCH 1
8-BIT
SHIFT
REGISTER
OUT0
REF
REF
OUT1
MAX518
8
1
DECODE
ADDRESS
COMPARATOR
DAC1
OUTPUT
LATCH 1
V
DD
7
SCL
SDA
AD0 AD1
3
4
65
GND
2
________________Functional Diagram
19-0393; Rev 1; 9/02
PART
MAX517ACPA
MAX517BCPA
MAX517ACSA 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP RANGE PIN-PACKAGE
8 Plastic DIP
8 Plastic DIP
8 SO
TUE
(LSB)
1
1.5
1
MAX517BCSA
MAX517BC/D 0°C to +70°C
0°C to +70°C 8 SO
Dice*
1.5
1.5
Ordering Information continued at end of data sheet.
*Dice are specified at T
A
= +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.
( ) ARE FOR MAX517
Pin Configurations continued at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
TOP VIEW
OUT0
GND
SCL
SDA
1
2
MAX517
3
MAX518
4
DIP/SO
8
OUT1 (REF0)
7
V
6
AD0
5
AD1
DD
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= 5V ±10%, V
REF_
= 4V (MAX517, MAX519), RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
OUT_ ..........................................................-0.3V to (V
DD
+ 0.3V)
REF_ (MAX517, MAX519)...........................-0.3V to (V
DD
+ 0.3V)
AD_.............................................................-0.3V to (V
DD
+ 0.3V)
SCL, SDA to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T
A
= +70°C)
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) ...727mW
8-Pin SO (derate 5.88mW/°C above +70°C)................471mW
8-Pin CERDIP (derate 8.00mW/°C above +70°C)........640mW
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)..842mW
16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ...696mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C) ......800mW
Operating Temperature Ranges
MAX51_C_ _ .......................................................0°C to +70°C
MAX51_E_ _.....................................................-40°C to +85°C
MAX51_MJB ..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
±1MAX51 _BM
±1MAX51 _E
MAX51 _C
Full-Scale-Error Temperature Coefficient
Full-Scale-Error Supply Rejection
±1
mV
±10 µV/°C
MAX517, MAX519
Code = FF hex
V
DD
= +5V ±10%
Code = FF hex
±20MAX51 _E
mV
MAX51 _C
±1MAX51 _BM
±1MAX51 _E
MAX51 _C
20MAX51 _BM
20MAX51 _E
MAX51 _C
MAX51 _A
PARAMETER SYMBOL MIN TYP MAX UNITS
Resolution 8 Bits
TUE
±1
Differential Nonlinearity (Note 1) DNL ±1 LSB
Zero-Code Error ZCE
18
mV
Zero-Code-Error Supply Rejection
±1
Zero-Code-Error Temperature Coefficient ±10 µV/°C
Full-Scale Error
±18
CONDITIONS
Guaranteed monotonic
Code = 00 hex
Code = 00 hex
Code = 00 hex
Code = FF hex,
MAX518 unloaded
mV
MAX51 _B ±1.5
Total Unadjusted Error (Note 1) LSB
±20
MAX51 _BM
STATIC ACCURACY
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 5V ±10%, V
REF_
= 4V (MAX517, MAX519), RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are T
A
= +25°C.)
0.6I
SINK
= 6mA
I
SINK
= 3mA
0.3V
DD
Input High Voltage V
IH
0.7V
DD
V
Input Leakage Current I
IN
±10 µA
Output Low Voltage V
OL
0.4
V
Three-State Leakage Current I
L
±10 µA
Three-State Output Capacitance C
OUT
10
0V ≤ VIN≤ V
DD
VIN= 0V to V
DD
(Note 6)
PARAMETER SYMBOL MIN TYP MAX UNITS
Output Leakage Current ±10 µA
CONDITIONS
OUT_ = 0V to VDD, power-down mode
pF
LSB
1.5
V
IL
Input Hysteresis V
HYST
0.05V
DD
V
Input Capacitance C
IN
10 pF(Note 6)
Input High Voltage V
IH
2.4 V
Input Low Voltage V
IL
0.8 V
Input Leakage Current I
IN
±10 µAVIN= 0V to V
DD
Voltage Output Slew Rate
2.0
Positive and negative V/µs
MAX51 _C
Output Settling Time µs
Digital Feedthrough 5Code = 00 hex, all digital inputs from 0V to V
DD
nV-s
1.4MAX51 _E
1.0MAX51 _M
Input Voltage Range 0V
DD
V
Input Resistance R
IN
16 24 kΩCode = 55 hex (Note 2)
Input Current ±10 µAPower-down mode
Input Capacitance 30 pFCode = FF hex (Note 3)
Channel-to-Channel Isolation
(MAX519)
-60(Note 4)
MAX51 _M, REF_ = V
DD
(MAX517, MAX519), code = FF hex,
0µA to 500µA
2.0
AC Feedthrough -70
dB
(Note 5)
MAX51 _C/E, REF_ = V
DD
(MAX517, MAX519), code = FF hex,
0µA to 500µA
Full-Scale Output Voltage 0V
DD
V
Output Load Regulation
0.25OUT_ = 4V, 0mA to 2.5mA
6To 1/2 LSB, 10kΩ and 100pF load (Note 8)
DAC OUTPUTS
DIGITAL INPUTS SCL, SDA
DIGITAL INPUTS AD0, AD1, AD2, AD3
DIGITAL OUTPUT SDA (Note 7)
DYNAMIC PERFORMANCE
REFERENCE INPUTS (MAX517, MAX519)
dB
Input Low Voltage V
mA
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
4 _______________________________________________________________________________________
Note 1: For the MAX518 (full-scale = VDD) the last three codes are excluded from the TUE and DNL specifications, due to the limited
output swing when loaded with 10kΩ to GND.
Note 2: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 3: Input capacitance is code dependent. The highest input capacitance occurs at code FF hex.
Note 4: V
REF_
= 4V
P-P
, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
code of all other DACs to 00 hex.
Note 5: V
REF_
= 4Vp-p, 10kHz, DAC code = 00 hex.
Note 6: Guaranteed by design.
Note 7: I
2
C compatible mode. R
PULLUP
= 1.7kΩ.
Note 8: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
Note 9: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 10: Cb = total capacitance of one bus line in pF. t
R
and tFmeasured between 0.3VDDand 0.7VDD.
Note 11: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Hold Time, (Repeated) Start Condition t
HD, STA
0.6 µs
Low Period of the SCL Clock t
LOW
1.3 µs
High Period of the SCL Clock t
HIGH
0.6
PARAMETER SYMBOL MIN TYP MAX UNITS
Serial Clock Frequency f
SCL
0400kHz
Bus Free Time Between a STOP and a
START Condition
t
BUF
1.3 µs
CONDITIONS
µs
Setup Time for a Repeated START Condition t
SU, STA
0.6 µs
Data Hold Time t
HD, DAT
0 0.9 µs
Data Setup Time t
SU, DAT
100
(Note 9)
ns
Fall Time of SDA Transmitting t
F
20 + 0.1Cb 250 ns
Setup Time for STOP Condition t
SU, STO
0.6 µs
Capacitive Load for Each Bus Line Cb 400
I
SINK
≤ 6mA (Notes 7, 10)
pF
Rise Time of Both SDA and SCL Signals, Receiving t
R
20 + 0.1Cb 300 ns
Fall Time of Both SDA and SCL Signals, Receiving t
F
20 + 0.1Cb 300
(Note 10)
(Note 10) ns
Pulse Width of Spike Suppressed t
SP
050(Notes 6, 11) ns
TIMING CHARACTERISTICS
(VDD= 5V ±10%, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are TA= +25°C.)
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 5V ±10%, V
REF_
= 4V (MAX517, MAX519), RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are T
A
= +25°C.)
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
Digital-Analog Glitch Impulse 12Code 128 to 127 nV-s
Signal to Noise + Distortion
Ratio (MAX517, MAX519)
SINAD 87
V
REF_
= 4Vp-p at 1kHz, VDD= 5V,
Code = FF hex
dB
Multiplying Bandwidth
(MAX517, MAX519)
1 MHz
Wideband Amplifier Noise 60 µV
RMS
Supply Voltage V
DD
4.5 5.5 V
1.5 3.0
MAX517E/M
MAX517C
2.5 5
1.5 3.5
V
REF_
= 4Vp-p, 3dB bandwidth
Supply Current
Normal mode, output(s)
unloaded, all digital inputs
at 0V or V
DD
2.5 6
MAX518C, MAX519C
MAX518E/M, MAX519E/M
I
DD
Power-down mode 420µA
POWER REQUIREMENTS
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________ 5
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
OUT0 LOADED WITH 10kΩ II 100pF
REF0 = 4V (MAX517/MAX519)
DAC CODE = 00 HEX to FF HEX
1µs/div
POSITIVE FULL-SCALE STEP RESPONSE
OUT0
1V/div
FULL-SCALE ERROR vs. SOURCE CURRENT
= VDD)
(V
10
VDD = V
DAC CODE = FF HEX
LOAD TO AGND
8
6
4
FULL-SCALE ERROR (LSB)
2
0
0 0.5 1.5 2.5 3.0 3.5 4.0
OUTPUT SOURCE CURRENT (mA)
REF
= 5V
REF
1.0 2.0
MAX518 SUPPLY CURRENT
vs. TEMPERATURE
3.5
3.0
2.5
2.0
1.5
1.0
SUPPLY CURRENT (mA)
0.5
0
-55 -35
DAC CODE = 1B HEX
-15
56545 125105
TEMPERATURE (°C)
VDD = 5.5V
AD0, AD1 = V
DAC CODE = FF HEX
DAC CODE = 00 HEX
25
ZERO-CODE ERROR
vs. SINK CURRENT
10
VDD = V
= 5V
MAX517-01
8
6
4
ZERO-CODE ERROR (LSB)
2
0
REF
DAC CODE = 00 HEX
LOAD to V
DD
0 0.5 2.0
OUTPUT SINK CURRENT (mA)
1.0 1.5
MAX517-02
MAX518 SUPPLY CURRENT
vs. DAC CODE
3.0
MAX517-04
DD
85
2.5
2.0
1.5
1.0
SUPPLY CURRENT (mA)
0.5
0
32 64 96 128 160 192 224 256
0
DAC CODE (DECIMAL)
VDD = 5.5V
BOTH DACS SET
MAX517-05
MAX517/MAX519 SUPPLY CURRENT
vs. TEMPERATURE
3.0
2.5
2.0
MAX519, DAC CODE = FF HEX
1.5
1.0
SUPPLY CURRENT (mA)
0.5
0
-55 -15 5-35 65
VDD = 5.5V
REF_ INPUTS = 0.6V
ALL DIGITAL INPUTS to V
MAX517, DAC CODE = FF HEX
MAX517, MAX519
DAC CODE = 00 HEX
4525 85 105
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
6
5
4
3
2
1
SHUTDOWN SUPPLY CURRENT (µA)
0
-55 -15-35 45 65 125
VDD = 5.5V
ALL DIGITAL INPUTS to V
255 85 105
TEMPERATURE (°C)
DD
125
DD
MAX517-03
MAX517-07
MAX517/MAX519 SUPPLY CURRENT
vs. REFERENCE VOLTAGE
2.5
2.0
1.5
1.0
SUPPLY CURRENT (mA)
0.5
MAX519
MAX517
0
010.5 32.5 54.5
REFERENCE VOLTAGE (V)
MAX517/MAX519 REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
VDD = 5V
DAC CODE(S) FF HEX
21.5 43.5
MAX517-08
0
-4
4V
SINE
-8
-12
RELATIVE OUTPUT (dB)
-16
P-P
SINE
2V
P-P
SINE
1V
P-P
SINE
0.5V
P-P
VDD = 5V
= SINE WAVE
V
REF
CENTERED AT 2.5V
1k 100k10k 1M 10M
FREQUENCY (Hz)
MAX517-09
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
6 _______________________________________________________________________________________
______________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
A = SCL, 400kHz, 5V/div
B = OUT0, 5mV/div
DAC CODE = 7F HEX
REF0 = 5V (MAX517/MAX519)
CLOCK FEEDTHROUGH
B
A
A = REF0, 1V/div (4V
P-P
)
B = OUT0, 50µV/div, UNLOADED
FILTER PASSBAND = 100Hz to 10kHz
DAC CODE = 00 HEX
MAX517/MAX519
REFERENCE FEEDTHROUGH AT 1kHz
B
A
A = REF0, 1V/div (4V
P-P
)
B = OUT0, 50µV/div, UNLOADED
FILTER PASSBAND = 1kHz to 100kHz
DAC CODE = 00 HEX
MAX517/MAX519
REFERENCE FEEDTHROUGH AT 10kHz
B
A
OUT0 LOADED WITH 10kΩ II 100pF
REF0 = 4V (MAX517/MAX519)
DAC CODE = FF HEX to 00 HEX
1µs/div
NEGATIVE FULL-SCALE STEP RESPONSE
OUT0
1V/div
REF0 = 5V (MAX517/MAX519)
DAC CODE = 80 HEX to 7F HEX
500ns/div
WORST-CASE 1LSB STEP CHANGE
OUT0
20mV/div
AC COUPLED
REFERENCE FEEDTHROUGH AT 100kHz
A = REF0, 1V/div (4V
B = OUT0, 50µV/div, UNLOADED
FILTER PASSBAND = 10kHz to 1MHz
DAC CODE = 00 HEX
MAX517/MAX519
)
P-P
A
B
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________ 7
Figure 1. MAX517/MAX519 Functional Diagram
_______________Detailed Description
Serial Interface
The MAX517/MAX518/MAX519 use a simple 2-wire
serial interface requiring only two I/O lines (2-wire bus)
of a standard microprocessor (µP) port. Figure 2 shows
the timing diagram for signals on the 2-wire bus.
Figure 3 shows a typical application. The 2-wire bus can
have several devices (in addition to the MAX517/
MAX518/MAX519) attached. The two bus lines (SDA and
SCL) must be high when the bus is not in use. When in
use, the port bits are toggled to generate the appropriate
signals for SDA and SCL. External pull-up resistors are
not required on these lines. The MAX517/MAX518/
MAX519 can be used in applications where pull-up resistors are required (such as in I2C systems) to maintain
compatibility with existing circuitry.
The MAX517/MAX518/MAX519 are receive-only devices
and must be controlled by a bus master device. They
operate at SCL rates up to 400kHz. A master device
sends information to the devices by transmitting their
address over the bus and then transmitting the desired
information. Each transmission consists of a START
condition, the MAX517/MAX518/MAX519’s programmable slave-address, one or more command-byte/output-byte pairs (or a command byte alone, if it is the last
byte in the transmission), and finally, a STOP condition
(Figure 4).
______________________________________________________________Pin Description
PIN
MAX517 MAX518 MAX519
NAME FUNCTION
1 1 1 OUT0 DAC0 Voltage Output
2 2 4 GND Ground
— — 5 AD3 Address Input 3; sets IC’s slave address
3 3 6 SCL Serial Clock Input
4 4 8 SDA Serial Data Input
— — 9 AD2 Address Input 2; sets IC’s slave address
5 5 10 AD1 Address Input 1; sets IC’s slave address
6 6 11 AD0 Address Input 0; sets IC’s slave address
7 7 12 VDD Power Supply, +5V; used as reference for MAX518
— — 13 REF1 Reference Voltage Input for DAC1
8 — 15 REF0 Reference Voltage Input for DAC0
— 8 16 OUT1 DAC1 Voltage Output
— — 2, 3, 7, 14 N.C. No Connect—not internally connected.
V
INPUT
LATCH 0
INPUT
LATCH 1
8-BIT
SHIFT
REGISTER
SCL
SDA
DECODE
AD0 (AD2)
AD1 (AD3)
( ) ARE FOR MAX519
OUTPUT
LATCH 0
OUTPUT
LATCH 1
ADDRESS
COMPARATOR
START/STOP
DETECTOR
DD
REF0 (REF1)
DAC0
DAC1
MAX519 ONLY
MAX517/MAX519
GND
OUT0
(OUT1)
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
8 _______________________________________________________________________________________
The address byte and pairs of command and output
bytes are transmitted between the START and STOP conditions. The SDA state is allowed to change only while
SCL is low, with the exception of START and STOP conditions. SDA’s state is sampled, and therefore must remain
stable while SCL is high. Data is transmitted in 8-bit
bytes. Nine clock cycles are required to transfer the data
bits to the MAX517/MAX518/MAX519. Set SDA low during the 9th clock cycle as the MAX517/MAX518/MAX519
pull SDA low during this time. RC(see Figure 3) limits the
current that flows during this time if SDA stays high for
short periods of time.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from
high to low while SCL is high (Figure 5). When the master has finished communicating with the slave, it issues
a STOP condition by transitioning SDA from low to high
while SCL is high. The bus is then free for another
transmission.
The Slave Address
The MAX517/MAX518/MAX519 each have a 7-bit long
slave address (Figure 6). The first three bits (MSBs) of
the slave address have been factory programmed and
are always 010. In addition, the MAX517 and MAX518
have the next two bits factory programmed to 1s. The
logic state of the address inputs (AD0 and AD1 on the
MAX517/MAX518; AD0, AD1, AD2, and AD3 on the
MAX519) determine the LSB bits of the 7-bit slave
address. These input pins may be connected to VDD or
DGND, or they may be actively driven by TTL or CMOS
logic levels. The MAX517/MAX518 have four possible
slave addresses and therefore a maximum of four of
Figure 3. MAX517/MAX518/MAX519 Application Circuit
Figure 2. Two-Wire Serial Interface Timing Diagram
SDA
tSU,
DAT
SCL
tHD,
STA
t
LOW
t
HIGH
t
R
tHD,
DAT
t
F
+1V
+4V
OFFSET ADJUSTMENT
GAIN ADJUSTMENT
DUAL
DAC
MAX519
REF0
REF1
OUT0
OUT1
µC
SDA SCL
R
C
1kΩ
SCL
SDA
AD0
AD1
AD2
AD3
tSU,
STA
tHD,
STA
tSU,
STO
t
BUF
START CONDITIONSTOP CONDITIONREPEATED START CONDITIONSTART CONDITION
SCL
SDA
AD0
AD1
DUAL
DAC
MAX518
OUT0
OUT1
BRIGHTNESS ADJUSTMENT
CONTRAST ADJUSTMENT
+2.5V
THRESHOLD ADJUSTMENT
+5V
SCL
SDA
AD0
AD1
SINGLE
DAC
MAX517
REF0
OUT0
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________ 9
these devices may share the bus. The MAX519 has 16
possible slave addresses. The eighth bit (LSB) in the
slave address byte should be low when writing to the
MAX517/MAX518/MAX519.
The MAX517/MAX518/MAX519 monitor the bus continuously, waiting for a START condition followed by their
slave address. When a device recognizes its slave
address, it is ready to accept data.
The Command Byte and Output Byte
A command byte follows the slave address. Figure 7
shows the format for the command byte. A command
byte is usually followed by an output byte unless it is
the last byte in the transmission. If it is the last byte, all
bits except PD (power-down) and RST (reset) are
ignored. If an output byte follows the command byte,
A0 of the command byte indicates the digital address
of the DAC whose input data latch receives the digital
output data. Set this bit to 0 when writing to the
MAX517. The data is transferred to the DAC’s output
latch during the STOP condition following the transmission. This allows both DACs of the MAX518/MAX519 to
be updated simultaneously (Figure 8).
Setting the PD bit high powers down the MAX517/
MAX518/MAX519 following a STOP condition (Figure
9a). If a command byte with PD set high is followed by
an output byte, the addressed DAC’s input latch will be
updated and the data will be transferred to the DAC’s
output latch following the STOP condition (Figure 9b).
Figure 6. Address Byte
SLAVE ADDRESS BITS AD0, AD1, AD2, AND AD3 CORRESPOND TO THE LOGIC
STATE OF THE ADDRESS INPUT PINS.
Figure 7. Command Byte
R2, R1, R0: RESERVED BITS. SET TO 0.
RST: RESET BIT, SET TO 1 TO RESET ALL DAC REGISTERS.
PD: POWER-DOWN BIT. SET TO 1 TO PLACE THE DEVICE IN THE 4µA SHUTDOWN
MODE. SET TO 0 TO RETURN TO THE NORMAL OPERATIONAL STATE.
A0: ADDRESS BIT. DETERMINES WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS
OF DATA IN THE NEXT BYTE. SET TO 0 FOR MAX517.
ACK: ACKNOWLEDGE BIT. THE MAX517/MAX518/MAX519 PULLS SDA LOW DURING
THE 9TH CLOCK PULSE.
X: DON’T CARE.
Figure 4. A Complete Serial Transmission
Figure 5. All communications begin with a START condition and
end with a STOP condition, both generated by a bus master.
OUTPUT BYTECOMMAND BYTESLAVE ADDRESS BYTE
SDA
SCL
START CONDITION
SDA
SCL
START CONDITION
SDA
SCL
MSB MSB MSBLSB LSB LSBACK ACK ACK
STOP CONDITION
SLAVE ADDRESS
00 1 or
10AD1 AD0
AD3
1 or
AD2
ACK
LSB
STOP CONDITION
R2 R1 R0 RST PD
SDA
SCL
X
A0/0 ACK
X
LSBMSB
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
10 ______________________________________________________________________________________
Figure 8a. Setting One DAC Output (MAX517/MAX518/MAX519)
Figure 8b. Setting Both DAC Outputs (MAX518/MAX519)
Figure 9. Entering the Power-Down State
1
1
or
or
AD3
ADDRESS BYTE ACK
AD0 0 0000000000
AD2AD1
COMMAND BYTE
(ADDRESSING DAC0)
ACK
111
OUTPUT BYTE
(FULL SCALE)
SDA
0
START
CONDITION
10
11
11
DAC0 INPUT LATCH
( )
SET TO FULL SCALE
0
1
ACK
STOP
CONDITION
DAC OUTPUT CHANGES HERE:
DAC0 GOES TO FULL SCALE.
( )
SDA
START
CONDITION
SDA
1
1
or
0
10
or
AD3
AD2AD1 AD0 0 0000000000
ADDRESS BYTE ACK
11 1111110
OUTPUT BYTE
(FULL SCALE)
DAC1 INPUT LATCH
( )
SET TO FULL SCALE
COMMAND BYTE
(ADDRESSING DAC0)
ACK
STOP
CONDITION
DAC OUTPUTS CHANGE HERE:
DAC0 AND DAC1 GO TO FULL SCALE.
( )
ACK
1
1
or
(a)
SDA
START
CONDITION
(b)
SDA
START
CONDITION
NOTE: X = DON'T CARE
0
0
10
10
or
AD3
AD2 AD1AD0 0 0 000001
ADDRESS BYTE ACK
1
1
or
or
AD3
AD2
AD1AD0 0 0 0
ADDRESS BYTE ACK
00001 0
(PD)
X X X
COMMAND BYTE
(PD)
X X
COMMAND BYTE
(ADDRESSING DAC0)
111
OUTPUT BYTE
(FULL SCALE)
ACK
STOP
CONDITION
1111111
ACK
11
11
DAC0 INPUT LATCH
( )
SET TO FULL SCALE
DEVICE ENTERS
POWER-DOWN STATE
( )
OUTPUT BYTE
(FULL SCALE)
DAC0 INPUT LATCH
( )
SET TO FULL SCALE.
0000000
1
ACK
COMMAND BYTE
(ADDRESSING DAC1)
0
1
ACK
STOP
CONDITION
DEVICE ENTERS POWER-DOWN STATE.
( )
DAC0 OUTPUT LATCH SET TO FULL SCALE.
00
1
ACK
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
______________________________________________________________________________________ 11
Furthermore if the transmission’s last command byte
has PD high, the output latches are updated, but voltage outputs will not reflect the newly entered data
because the DAC enters power-down mode when the
STOP condition is detected. When in power-down, the
DAC outputs float. In this mode, the supply current is a
maximum of 20µA. A command byte with the PD bit low
returns the MAX517/MAX518/MAX519 to normal operation following a STOP condition, with the voltage outputs reflecting the output-latch contents (Figures 10a
and 10b). Because each subsequent command byte
overwrites the previous PD bit, only the last command
byte of a transmission affects the power-down state.
Setting the RST bit high clears the DAC input latches.
The DAC outputs remain unchanged until a STOP condition is detected (Figure 11a). If a reset is issued, the
following output byte is ignored. Subsequent pairs of
command/output bytes overwrite the input latches
(Figure 11b).
All changes made during a transmission affect the
MAX517/MAX518/MAX519’s outputs only when the
transmission ends and a STOP has been recognized.
The R0, R1, and R2 bits are reserved and must be set
to zero.
I2C Compatibility
The MAX517/MAX518/MAX519 are fully compatible
with existing I
2
C systems. SCL and SDA are highimpedance inputs; SDA has an open drain that pulls
the data line low during the 9th clock pulse. Figure 12
shows a typical I2C application.
Figure 11. Resetting DAC Outputs
Figure 10. Returning to Normal Operation from Power-Down
1
1
or
(a)
SDA
START
CONDITION
(b)
SDA
START
CONDITION
NOTE: X = DON'T CARE
or
0
10
AD2 AD1AD0 0 0 000000
AD3
ADDRESS BYTE ACK
1
1
or
0
10
or
AD1AD0 0 00 0000
AD3
AD2
ADDRESS BYTE ACK
(PD)
X X X
COMMAND BYTE
(PD)
X X
COMMAND BYTE
(ADDRESSING DAC0)
ACK
STOP
CONDITION
ACK
DEVICE RETURNS TO
NORMAL OPERATION
( )
00
000
0
0
OUTPUT BYTE
00
(SET TO 0)
DAC0 INPUT
( )
LATCH SET TO 0.
00
ACK
STOP
CONDITION
DEVICE RETURNS TO NORMAL OPERATION.
( )
DAC0 SET TO 0.
(a)
SDA
START
CONDITION
(b)
SDA
START
CONDITION
NOTE: X = DON'T CARE
1
1
or
0
0
10
10
or
AD1AD000 00010 0
AD3
AD2
ADDRESS BYTE ACK
1
1
or
or
AD1AD00000010 0 0
AD3
AD2
ADDRESS BYTE ACK
(RST)
X X X
COMMAND BYTE
ALL INPUT LATCHES
( )
SET TO 0.
(RST)
X X X X X X X X X X X
COMMAND BYTE
ALL INPUT LATCHES
( )
ACK
STOP
CONDITION
ALL OUTPUTS
( )
SET TO 0.
ACK
SET TO 0.
"DUMMY"
OUTPUT BYTE
ACK
ADDITIONAL
COMMAND BYTE/
OUTPUT BYTE PAIRS
STOP
CONDITION
DAC OUTPUTS SET TO 0 UNLESS
CHANGED BY ADDITIONAL COMMAND
( )
BYTE/OUTPUT BYTE PAIRS.
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
12 ______________________________________________________________________________________
Additional START Conditions
It is possible to interrupt a transmission to a device with
a new START (repeated start) condition (perhaps
addressing another device), which leaves the input
latches with data that has not been transferred to the
output latches (Figure 13). Only the currently addressed
device will recognize a STOP condition and transfer
data to its output latches. If the device is left with data in
its input latches, the data can be transferred to the output latches the next time the device is addressed, as
long as it receives at least one command byte and a
STOP condition.
Early STOP Conditions
The addressed device recognizes a STOP condition at
any point in a transmission. If the STOP occurs during a
command byte, all previous uninterrupted command
and output byte pairs are accepted, the interrupted
command byte is ignored, and the transmission ends
(Figure 14a). If the STOP occurs during an output byte,
all previous uninterrupted command and output byte
pairs are accepted, the final command byte
’
s PD and
RST bits are accepted, the interrupted output byte is
ignored, and the transmission ends (Figure 14b).
Analog Section
DAC Operation
The MAX518 and MAX519 contain two matched voltage-output DACs. The MAX517 contains a single DAC.
The DACs are inverted R-2R ladder networks that convert 8-bit digital words into equivalent analog output
voltages in proportion to the applied reference voltages. The MAX518 has both DAC’s reference inputs
connected to VDD. Figure 15 shows a simplified diagram of one DAC.
MAX517/MAX519 Reference Inputs
The MAX517 and MAX519 can be used for multiplying
applications. The reference accepts a 0V to VDDvolt-
Figure 13. Repeated START Conditions
Figure 12. MAX517/MAX518/MAX519 Used in a Typical I2C
Application Circuit
µC
SDA SCL
+5V
SCL
SDA
SCL
SDA
AD0
AD1
SCL
SDA
AD0
AD1
E2 PROM
XICOR
X24C04
DUAL
DAC
MAX518
SINGLE
DAC
MAX517
OUT0
OUT1
OUT0
0
SDA
START
CONDITION
10110000 0
ADDRESS BYTE
(DEVICE 0)
00000 000 0101 101001
ACK
COMMAND BYTE
ADDRESSING DAC0
ACK
1111 111
OUTPUT BYTE
(FULL SCALE)
DAC0 INPUT LATCH
( )
SET TO FULL SCALE.
ACK
DEVICE 0's
0
ADDRESS BYTE
(DEVICE 1)
REPEATED START
CONDITION
ACK
0000 00 00 0011111 111
SDA
COMMAND BYTE
(ADDRESSING DAC0)
ACK ACK
OUTPUT BYTE
(FULL SCALE)
DEVICE 1's DAC0
INPUT LATCH SET
( )
TO FULL SCALE.
STOP
CONDITION
ONLY DEVICE 1's DAC0 OUTPUT LATCH SET TO FULL
( )
SCALE. DEVICE 0's OUTPUT LATCH UNCHANGED.
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
______________________________________________________________________________________ 13
age, both DC and AC signals. The voltage at each REF
input sets the full-scale output voltage for its respective
DAC. The reference voltage must be positive. The
DAC’s input impedance is code dependent, with the
lowest value occurring when the input code is 55 hex or
0101 0101, and the maximum value occurring when the
input code is 00 hex. Since the REF input resistance
(RIN) is code dependent, it must be driven by a circuit
with low output impedance (no more than RIN ÷ 2000)
to maintain output linearity. The REF input capacitance
is also code dependent, with the maximum value
occurring at code FF hex (typically 30pF). The output
voltage for any DAC can be represented by a digitally
programmable voltage source as: V
OUT
= (N x V
REF
) /
256, where N is the numerical value of the DAC’s binary
input code.
Output Buffer Amplifiers
The DAC voltage outputs are internally buffered precision unity-gain followers that slew up to 1V/µs. The outputs can swing from 0V to V
DD
. With a 0V to 4V (or 4V
to 0V) output transition, the amplifier outputs typically
settle to 1/2LSB in 6µs when loaded with 10kΩ in parallel with 100pF. The buffer amplifiers are stable with any
combination of resistive loads ≥2kΩ and capacitive
loads ≤300pF.
The MAX517/MAX518/MAX519 are designed for unipolar-output, single-quadrant multiplication where the output voltages and the reference inputs are positive with
respect to AGND. Table 1 shows the unipolar code.
Table 1. Unipolar Code Table
Figure 15. DAC Simplified Circuit Diagram
1
Figure 14. Early STOP Conditions
DAC CONTENTS
ANALOG OUTPUT
11111111
255
+ V
REF
(
———)
256
10000001
129
+ V
REF
(———)
256
10000000
128 V
REF
+ V
REF
(
———)
= ——
256 2
01111111
127
+ V
REF
(
———)
256
00000001
1
+ V
REF
(
———)
256
00000000 0V
1
or
(a)
SDA
(b)
SDA
START
CONDITION
START
CONDITION
0
0
10
10
or
AD1AD0 0 0 0 0 0011
AD3
AD2
ADDRESS BYTE ACK
1
1
or
or
AD3
AD2
AD1AD000000 000011100RST 1
ADDRESS BYTE ACK
INTERRUPTED
COMMAND BYTE
(RST) (PD)
STOP CONDITION
(PD)
COMMAND BYTE
(POWER DOWN)
EARLY
X X
MAX517/MAX518/MAX519's
STATE REMAINS UNCHANGED.
( )
INTERRUPTED
ACK
OUTPUT BYTE
REF_*
GND
SHOWN FOR ALL 1s ON DAC
*REF = V
EARLY
STOP CONDITION
R
2R 2R 2R 2R 2R
D0 D5 D6 D7
FOR THE MAX518
DD
MAX517/MAX518/MAX519
POWER DOWN; INPUT LATCH
UNCHANGED IF RST = 0,
( )
DAC OUTPUT(S) RESET IF RST = 1.
RR
2R
OUT_
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
14 ______________________________________________________________________________________
__________Applications Information
Power-Supply Bypassing and
Ground Management
Bypass VDDwith a 0.1µF capacitor, located as close to
VDDand GND as possible. Careful PC board layout
minimizes crosstalk among DAC outputs, reference
inputs, and digital inputs. Figure 16 shows the suggested PC board layout to minimize crosstalk.
When using the MAX518 (or the MAX517/MAX519 with
VDDas the reference), you may want to add a noise filter to the VDDsupply (Figure 17) or to the reference
input(s) (Figure 18), especially in noisy environments.
The reference input’s bandwidth exceeds 1MHz for AC
signals, so disturbances on the reference input can
easily affect the DAC output(s).
The maximum input current for a single reference input
is V
REF
/16kΩ = I
REF
(max). In Figure 17, choose RFso
that changes in the reference input current will have little effect on the reference voltage. For example, with R
F
= 6Ω, the maximum output error due to RFis given by:
6Ω x I
REF
(max) = 1.9mV or 0.1LSB
In Figure 18, there is a voltage drop across RFthat
adds to the TUE. This voltage drop is due to the sum of
the reference input current (V
REF
/16kΩ maximum), supply current (6mA maximum), and the amplifier output
current (V
REF/RLOAD
). Choose RFto limit this voltage
drop to an acceptable value. For example, with a 10kΩ
load, you can limit the error due to RFto 0.5LSB
(9.8mV) by selecting RFso that:
RF= V
R
F
/ I
R
F
≤ 9.8mV / (5V / 16kΩ + 6mA +
5V / 10kΩ)
RF≤ 1.4Ω
Figure 16. PC Board Layout for Minimizing MAX519 Crosstalk
(bottom view)
Figure 17. Reference Filter When Using VDDas a Reference
Figure 18. VDDFilter When Using VDDas a Reference
SYSTEM GND
OUT1
REF0
N.C.
REF1
OUT0
N.C.
N.C.
GND
+5V
+5V
0.1µF
V
REF_
DD
MAX517
MAX519
V
DD
MAX518
0.1µF
R
F
C
F
R
F
C
F
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
______________________________________________________________________________________ 15
__Ordering Information (continued)
*Dice are specified at TA= +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.
MAX517BMJA -55°C to +125°C 8 CERDIP** 1.5
MAX517BEPA -40°C to +85°C 8 Plastic DIP 1.5
MAX517AEPA -40°C to +85°C 8 Plastic DIP 1
MAX518ACPA
0°C to +70°C 8 Plastic DIP 1
1.516 CERDIP**-55°C to +125°C
1.516 Narrow SO-40°C to +85°CMAX519BESE
116 Narrow SO-40°C to +85°CMAX519AESE
1.516 Plastic DIP-40°C to +85°CMAX519BEPE
116 Plastic DIP-40°C to +85°CMAX519AEPE
1.5Dice*0°C to +70°CMAX519BC/D
1.516 Narrow SO0°C to +70°CMAX519BCSE
116 Narrow SO0°C to +70°CMAX519ACSE
1.516 Plastic DIP0°C to +70°CMAX519BCPE
116 Plastic DIP0°C to +70°C
MAX519ACPE
1.58 CERDIP**-55°C to +125°CMAX518BMJA
1.58 SO-40°C to +85°CMAX518BESA
18 SO-40°C to +85°CMAX518AESA
PART TEMP RANGE PIN-PACKAGE
TUE
(LSB)
MAX518BCPA
MAX518ACSA 0°C to +70°C
0°C to +70°C 8 Plastic DIP
8 SO
1.5
1
MAX518BCSA
MAX518BC/D
MAX518AEPA -40°C to +85°C
0°C to +70°C
0°C to +70°C 8 SO
Dice*
8 Plastic DIP
1.5
1.5
1
MAX518BEPA -40°C to +85°C 8 Plastic DIP 1.5
MAX519BMJE
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OUT1
REF0
N.C.
REF1
GND
N.C.
N.C.
OUT0
MAX519
V
DD
AD0
AD1
AD2
SDA
N.C.
SCL
AD3
DIP/SO
_____Pin Configurations (continued)
MAX517BESA -40°C to +85°C 8 SO 1.5
MAX517AESA -40°C to +85°C 8 SO 1
TOP VIEW
TRANSISTOR COUNT: 1797
SUBSTRATE CONNECTED TO V
DD
____________________Chip Topography
REF0
(MAX517/
MAX519)
REF1
(MAX519)
VDD
AD0
OUT0
OUT1
(MAX518/MAX519)
SDA
AD2
(MAX519)
AD1
0.135"
(3.429mm)
0.078"
(1.981mm)
AD3
(MAX519)
SCL
GND
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PDIPN.EPS
N
HE
1
TOP VIEW
D
C
L
SIDE VIEW
e
FRONT VIEW
A
B
A1
INCHES
DIM
A1
B
C
e 0.050 BSC 1.27 BSC
E
H 0.2440.228 5.80 6.20
VARIATIONS:
D
D
0-8
MAX
MIN
0.069
0.053A
0.010
0.004
0.014
0.019
0.007
0.010
0.150
0.157
0.016L
0.050
INCHES
MAX
MINDIM
0.189 0.197 AA5.004.80 8
0.337 0.344 AB8.758.55 14
0.3940.386D
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
MILLIMETERS
MAX
MIN
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
3.80 4.00
0.40 1.27
MILLIMETERS
MAX
MIN
9.80 10.00
21-0041
N MS012
16
REV.DOCUMENT CONTROL NO.APPROVAL
SOICN .EPS
AC
1
B
1
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