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General Description
The MAX5174/MAX5176 low-power, serial, voltage-output, 12-bit digital-to-analog converters (DACs) feature a
precision output amplifier in a space-saving 16-pin
QSOP package. The MAX5174 operates from a single
+5V supply, and the MAX5176 operates from a single
+3V supply. Both devices draw only 280µA of supply
current, which reduces to 1µA in shutdown. In addition,
the programmable power-up reset feature allows for a
user-selectable output voltage state of either 0 or midscale.
The 3-wire, digital, serial interface is compatible with
SPI™/QSPI™, and MICROWIRE™ standards. An input
register followed by a DAC register provides a doublebuffered input, allowing the input and DAC registers to
be updated independently or simultaneously with a 16bit serial word. Additional features include software and
hardware shutdown, shutdown lockout, a hardware
clear pin, and a reference input capable of accepting
DC and offset AC signals. These devices provide a programmable digital output pin for added functionality
and a serial-data output pin for daisy-chaining. All logic
inputs are TTL/CMOS compatible and are internally
buffered with Schmitt triggers to allow direct interfacing
to optocouplers.
The MAX5174/MAX5176 incorporate a proprietary onchip circuit that keeps the output voltage virtually
“glitch free,” limiting the glitches to a few millivolts during power-up.
Both devices are available in 16-pin QSOP packages
and are specified for the extended (-40°C to +85°C)
temperature range. The MAX5170/MAX5172 are pincompatible 14-bit upgrades to the MAX5174/MAX5176.
For 100% pin-compatible DACs with internal reference,
see the 13-bit MAX5130/MAX5131 and the 12-bit
MAX5120/MAX5121 data sheets.
Applications
Industrial Process Controls
Digital Offset and Gain Adjustment
Motion Control
Automatic Test Equipment (ATE)
Remote Industrial Controls
µP-Controlled Systems
Features
♦ ±1 LSB INL
♦ 1µA Shutdown Current
♦ “Glitch Free” Output Voltage at Power-Up
♦ Single-Supply Operation
+5V (MAX5174)
+3V (MAX5176)
♦ Full-Scale Output Range
+2.048V (MAX5176, V
REF
= +1.25V)
+4.096V (MAX5174, V
REF
= +2.5V )
♦ Rail-to-Rail®Output Amplifier
♦ Adjustable Output Offset
♦ Low THD (-80dB) in Multiplying Operation
♦ SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial
Interface
♦ Programmable Shutdown Mode and Power-Up
Reset
♦ Buffered Output Capable of Driving 5kΩ || 100pF
Loads
♦ User-Programmable Digital Output Pin Allows
Serial Control of External Components
♦ 14-Bit Upgrades Available (MAX5170/MAX5172)
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
________________________________________________________________
Maxim Integrated Products
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OS V
DD
N.C.
REF
AGND
PDL
UPO
DOUT
DGND
TOP VIEW
MAX5174
MAX5176
QSOP
OUT
RS
CS
SHDN
CLR
DIN
SCLK
19-1475; Rev 0; 4/99
PART
MAX5174AEEE
MAX5174BEEE
MAX5176AEEE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP. RANGE PIN-PACKAGE
16 QSOP
16 QSOP
16 QSOP
Pin Configuration
Ordering Information
MAX5176BEEE -40°C to +85°C 16 QSOP
INL
(LSB)
±1
±2
±2
±4
Functional Diagram appears at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS—MAX5174
(VDD= +5V ±10%, V
REF
= 2.5V, OS = AGND = DGND, RL= 5kΩ, CL= 100pF referenced to ground, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND, DGND............................................-0.3V to +6.0V
AGND to DGND.....................................................-0.3V to +0.3V
Digital Inputs to DGND..........................................-0.3V to +6.0V
DOUT, UPO to DGND ................................-0.3V to (VDD+ 0.3V)
OUT, REF to AGND ...................................-0.3V to (VDD+ 0.3V)
OS to AGND ...............................(AGND - 4.0V) to (VDD+ 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP (derate 8mW/°C above +70°C)..............667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
Bits12Resolution
MAX5174A ±1
MAX5174B
LSB
±2
INLIntegral Nonlinearity (Note 1)
LSB±1DNLDifferential Nonlinearity
mV±10V
OS
Offset Error (Note 2)
RL= ∞
LSB
-0.6 ±4
GEGain Error
RL= 5kΩ -1.6 ±8
µV/V10 120PSRRPower-Supply Rejection Ratio
f = 100kHz LSBp-p1Output Noise Voltage
nV/√Hz
80Output Thermal Noise Density
V0V
DD
- 1.4V
REF
Reference Input Range
kΩ18R
REF
Reference Input Resistance
V
REF
= 0.5Vp-p + 1.5VDC, slew-rate limited kHz350Reference -3dB Bandwidth
V
REF
= 2Vp-p + 1.5VDC, f = 10kHz,
code = FFF hex
dB82SINAD
Signal-to-Noise Plus Distortion
Ratio
V3V
IH
Input High Voltage
V0.8V
IL
Input Low Voltage
mV200V
HYS
Input Hysteresis
VIN= 0 or V
DD
µA0.001 ±1I
IN
Input Leakage Current
pF8C
IN
Input Capacitance
I
SOURCE
= 2mA VVDD- 0.5V
OH
Output High Voltage
I
SINK
= 2mA V0.13 0.4V
OL
Output Low Voltage
V
REF
= 3.6Vp-p + 1.8VDC, f = 1kHz,
code = all 0s
dB-80Reference Feedthrough
STATIC PERFORMANCE
REFERENCE
MULTIPLYING-MODE PERFORMANCE
DIGITAL INPUTS
DIGITAL OUTPUTS
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—MAX5174 (continued)
(VDD= +5V ±10%, V
REF
= 2.5V, OS = AGND = DGND, RL= 5kΩ, CL= 100pF referenced to ground, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.)
CONDITIONS
V/µs0.6SRVoltage Output Slew Rate
V0V
DD
Output Voltage Swing (Note 3)
kΩ80 120OS Pin Input Resistance
µs40Time Required to Exit Shutdown
UNITSMIN TYP MAXSYMBOLPARAMETER
CS = VDD, f
SCLK
= 100kHz, V
SCLK
= 5Vp-p
nV-s1Digital Feedthrough
V4.5 5.5V
DD
Positive Supply Voltage
mA0.35 0.4I
DD
Power-Supply Current (Note 4)
µA110Shutdown Current (Note 4)
ns100t
CP
SCLK Clock Period
ns40t
CH
SCLK Pulse Width High
ns40t
CL
SCLK Pulse Width Low
ns40t
CSS
CS Fall to SCLK Rise Setup
Time
ns40t
DS
SDI Setup Time
ns0t
DH
SDI Hold Time
C
LOAD
= 200pF ns80t
DO1
SCLK Rise to DOUT Valid
Propagation Delay
C
LOAD
= 200pF ns80t
DO2
SCLK Fall to DOUT Valid
Propagation Delay
ns10t
CS0
SCLK Rise to CS Fall Delay
ns100t
CSW
CS Pulse Width High
ns0t
CSH
SCLK Rise to CS Rise Hold
Time
ns40t
CS1
CS Rise to SCLK Rise Hold Time
To ±0.5LSB, from 10mV to full-scale µs18Output Settling Time
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX5176
(VDD= +2.7V to +3.6V, V
REF
= 1.25V, OS = AGND = DGND, RL= 5kΩ, CL= 100pF referenced to ground, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C).
Bits12Resolution
MAX5176A ±2
V
REF
= 1.6Vp-p + 0.8VDC, f = 1kHz,
code = all 0s
dB
MAX5176B
LSB
±4
INLIntegral Nonlinearity (Note 5)
LSB±1DNLDifferential Nonlinearity
mV±10
CONDITIONS
V
OS
Offset Error (Note 2)
RL= ∞
LSB
-0.6 ±4
GEGain Error
RL= 5kΩ -1.6 ±8
-80
µV/V10 120PSRRPower-Supply Rejection Ratio
f = 100kHz LSBp-p2Output Noise Voltage
nV/√Hz
80Output Thermal Noise Density
V0V
DD
- 1.4V
REF
Reference Input Range
kΩ18R
REF
Reference Input Resistance
V
REF
= 0.5Vp-p + 0.75VDC, slew-rate limited kHz350Reference -3dB Bandwidth
V
REF
= 0.6Vp-p + 0.9VDC, f = 10kHz,
code = FFF hex
dB78SINAD
Signal-to-Noise Plus Distortion
Ratio
Reference Feedthrough
V2.2V
IH
Input High Voltage
V0.8V
IL
Input Low Voltage
mV200V
HYS
Input Hysteresis
VIN= 0 or V
DD
µA0.001 ±1I
IN
Input Leakage Current
UNITSMIN TYP MAXSYMBOLPARAMETER
pF8C
IN
Input Capacitance
I
SOURCE
= 2mA VVDD- 0.5V
OH
Output High Voltage
I
SINK
= 2mA V0.13 0.4V
OL
Output Low Voltage
STATIC PERFORMANCE
REFERENCE
MULTIPLYING-MODE PERFORMANCE
DIGITAL INPUT
DIGITAL OUTPUT
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
_______________________________________________________________________________________ 5
Note 1: INL guaranteed between codes 10 and 4095.
Note 2: Offset is measured at the code that comes closest to 10mV.
Note 3: Accuracy is better than 1 LSB for V
OUT
= 10mV to VDD- 180mV. Guaranteed by PSR test on end points.
Note 4: R
L
= open and digital inputs are either VDDor DGND.
Note 5: INL guaranteed between codes 20 and 4095.
ELECTRICAL CHARACTERISTICS—MAX5176 (continued)
(VDD= +2.7V to +3.6V, V
REF
= 1.25V, OS = AGND = DGND, RL= 5kΩ, CL= 100pF referenced to ground, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C).
Power-Supply Current (Note 4) I
DD
0.35 0.4 mA
Positive Supply Voltage V
DD
2.7 3.6 V
Digital Feedthrough 1 nV-s
CS = VDD, DIN = 50kHz; f
SCLK
= 100kHz,
V
SCLK
= 3Vp-p
PARAMETER SYMBOL MIN TYP MAX UNITS
Time Required to Exit Shutdown 40 µs
OS Pin Input Resistance 80 120 kΩ
Output Voltage Swing (Note 3) 0 V
DD
V
Voltage Output Slew Rate
SR 0.6 V/µs
CS Pulse Width High
t
CSW
150 ns
SCLK Rise to CS Fall Delay
t
CS0
10 ns
Output Settling Time 18 µsTo ±0.5LSB, from 10mV to full-scale
SCLK Fall to DOUT Valid
Propagation Delay
t
DO2
200 nsC
LOAD
= 200pF
CS Rise to SCLK Rise Hold Time
t
CS1
75 ns
SCLK Rise to DOUT Valid
Propagation Delay
t
DO1
200 nsC
LOAD
= 200pF
SDI Hold Time t
DH
0 ns
SDI Setup Time t
DS
60 ns
SCLK Rise to CS Rise Hold Time
t
CSH
0 ns
CSB Fall to SCLK Rise Setup
Time
t
CSS
60 ns
SCLK Pulse Width Low t
CL
CONDITIONS
75 ns
SCLK Pulse Width High t
CH
75 ns
SCLK Clock Period t
CP
150 ns
Shutdown Current (Note 4) 110µA
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
6 _______________________________________________________________________________________
Typical Operating Characteristics
(MAX5174: VDD= +5V, V
REF
= 2.5V; MAX5176: VDD= +3V, V
REF
= +1.25V; CL = 100pF, OS = AGND, code = FFF hex,
T
A
= +25°C, unless otherwise noted.)
230
260
250
240
280
270
320
310
300
290
330
4.4 4.6 4.8 5.0 5.2 5.4 5.6
NO-LOAD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5174/6 toc01
SUPPLY VOLTAGE (V)
NO-LOAD SUPPLY CURRENT (µA)
268
270
272
274
276
278
280
282
284
286
288
290
-50 -30 -10 10 30 50 70 90
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE
MAX5174/6toc02
TEMPERATURE (°C)
NO-LOAD SUPPLY CURRENT (µA)
0.8
1.0
0.9
1.2
1.1
1.3
1.4
-50 -10 10 30-30 50 70 90
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX5174/6toc03
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (µA)
4.0960
4.0962
4.0966
4.0964
4.0968
4.0970
-50 -10-30 10 30 50 70 90
OUTPUT VOLTAGE vs. TEMPERATURE
MAX5174/6toc04
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
2µs/div
DYNAMIC RESPONSE
V
CS
5V/div
V
OUT
1V/div
4.096V
0
5V
10mV
MAX5174/6 toc07
3.0
3.5
4.0
4.5
0
10 100 1k 10k 100k
OUTPUT VOLTAGE vs. LOAD RESISTANCE
0.5
1.5
2.5
MAX5174/6 toc05
RL (Ω)
OUTPUT VOLTAGE (V)
1.0
2.0
2µs/div
DYNAMIC RESPONSE
V
CS
5V/div
V
OUT
1V/div
4.096V
0
5V
10mV
MAX5174/6 toc06
10k 100k
-84
-83
-82
-81
-79
-80
-78
-77
-76
-75
10 100 1k
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
MAX5174/76 toc08
FREQUENCY (Hz)
THD + NOISE (dB)
V
OUT/VREF
12.5dB/div
20
0
10k
REFERENCE FEEDTHROUGH
MAX5174/76 toc9
FREQUENCY (Hz)
V
REF
= 1.8 VDC + 3.6Vp-p at f = 1kHz
MAX5174
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
_______________________________________________________________________________________
7
0
V
OUT/VREF
12.5dB/div
20 100k
FFT PLOT
MAX5174/76 toc10
FREQUENCY (Hz)
V
REF
= 1.25VDC + 1.13Vp-p at f = 10kHz
5µs/div
MAJOR-CARRY TRANSITION
V
OUT
100mV/div
MAX5174/6 toc11
V
CS
V/div
400ns/div
DIGITAL FEEDTHROUGH
V
SCLK
5V/div
MAX5174/6 toc12
V
OUT
2mV/div
AC-COUPLED
-25
-15
-20
-5
-10
0
5
0 1000 1500500 2000 2500 3000
REFERENCE INPUT FREQUENCY RESPONSE
MAX5174/6toc13
FREQUENCY (kHz)
GAIN (dB)
V
REF
= 0.67Vp-p + 1.5V
DC
5Oms/div
START-UP GLITCH
V
OUT
10mV/div
AC-COUPLED
MAX5174/6 toc14
V
DD
1V/div
Typical Operating Characteristics (continued)
(MAX5174: VDD= +5V, V
REF
= 2.5V; MAX5176: VDD= +3V, V
REF
= +1.25V; CL = 100pF, OS = AGND, code = FFF hex,
T
A
= +25°C, unless otherwise noted.)
MAX5174
MAX5176
250
260
255
270
265
280
275
285
295
290
300
2.5 2.7 2.8 2.92.6 3.0 3.1 3.2 3.43.3 3.5
NO-LOAD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5174/6toc15
SUPPLY VOLTAGE (V)
NO-LOAD SUPPLY CURRENT (µA)
260
270
265
280
275
290
285
295
-50 -10 10-30 30 50 70 90
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE
MAX5174/6toc16
TEMPERATURE (°C)
NO-LOAD SUPPLY CURRENT (µA)
0.44
0.48
0.46
0.52
0.50
0.58
0.56
0.54
0.60
-50 -10-30 10 30 50 70 90
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX5174/6 toc17
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (µA)
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(MAX5174: VDD= +5V, V
REF
= 2.5V; MAX5176: VDD= +3V, V
REF
= +1.25V; CL = 100pF, OS = AGND, code = FFF hex,
T
A
= +25°C, unless otherwise noted.)
2.5
-0.5
10 100 1k 10k 100k
OUTPUT VOLTAGE vs. LOAD RESISTANCE
0
1.0
2.0
MAX5170/72 toc19
RL (Ω)
OUTPUT VOLTAGE (V)
0.5
1.5
2.0480
2.0482
2.0484
2.0488
2.0486
2.0490
-50 -30 -10 10 30 50 70 90
OUTPUT VOLTAGE vs. TEMPERATURE
MAX5174/6 toc18
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
2µs/div
DYNAMIC RESPONSE
V
OUT
500mV/div
MAX5174/6 toc20
V
CS
3V/div
3V
0
2.048V
10mV
2µs/div
DYNAMIC RESPONSE
V
OUT
500mV/div
MAX5174/6 toc21
V
CS
3V/div
3V
0
2.048V
10mV
-78.0
10 100 1k 10k 100k
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
-81.0
-80.5
-80.0
-79.5
-79.0
-78.5
-81.5
-82.0
MAX5174/76 toc22
FREQUENCY (Hz)
THD + NOISE (dB)
CS
2V/div
OUT
100mV/div
5µs/div
MAJOR-CARRY TRANSITION
MAX5174/6 toc25
AC-COUPLED
V
OUT/VREF
12.5dB/div
20
0
10k
REFERENCE FEEDTHROUGH
MAX5174/76 toc23
FREQUENCY (Hz)
V
REF
= 0.8VDC + 1.6Vp-p at f = 1kHz
FFT PLOT
MAX5174/76 toc24
FREQUENCY (Hz)
V
OUT/VREF
12.5dB/div
20
0
100k
V
REF
= 0.9VDC + 0.424Vp-p at f = 10kHz
MAX5176
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
_______________________________________________________________________________________ 9
Typical Operating Characteristics (continued)
(MAX5174: VDD= +5V, V
REF
= 2.5V; MAX5176: VDD= +3V, V
REF
= +1.25V; CL = 100pF, OS = AGND, code = FFF hex,
T
A
= +25°C, unless otherwise noted.)
SCLK
2V/div
OUT
500µV/div
2µs/div
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5174/6 toc26
AC-COUPLED
-30
-15
-20
-25
-5
-10
0
5
0 1000 1500500 2000 2500 3000
REFERENCE INPUT
FREQUENCY RESPONSE
MAX5174/6toc27
FREQUENCY (kHz)
GAIN (dB)
V
REF
= 0.67Vp-p + 0.75V
DC
50ms/div
START-UP GLITCH
V
OUT
10mV/div
AC-COUPLED
MAX5174/6 toc28
V
DD
1V/div
MAX5176
Pin Description
Voltage Output. High impedance when in shutdown. The output voltage is limited to VDD.OUT2
Power-Down Lockout. (digital input). Connect to VDDto allow shutdown. Connect to DGND to disable
software and hardware shutdown.
PDL
4
Reset Mode Select (digital input). Connect to VDDto select midscale reset output voltage. Connect to
DGND to select 0 reset output voltage.
RS3
Chip-Select Input (digital input). DIN ignored when CS is high.CS
6
Serial Clock Input (digital input).SCLK8
Serial-Data Input (digital input). Data is clocked in on the rising edge of SCLK.DIN7
Clear DAC. (digital input) Clears the DAC to either zero or midscale as determined by RS.
CLR
5
Serial-Data OutputDOUT10
Shutdown (digital input). Pulling SHDN high when PDL = VDDplaces the chip in shutdown with a maximum
shutdown current of 10µA.
SHDN12
User-Programmable Output. State is set by the serial input.UPO11
Reference Input. Maximum V
REF
is VDD- 1.4V.REF14
PIN
Positive Supply. Bypass to AGND with a 4.7µF capacitor in parallel with a 0.1µF capacitor.V
DD
16
Offset Adjustment. Connect to AGND for no offset.OS1
FUNCTIONNAME
No Connection N.C.15
Analog GroundAGND13
Digital GroundDGND9
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
10 ______________________________________________________________________________________
Detailed Description
The MAX5174/MAX5176 12-bit, serial, voltage-output
DACs operate with a 3-wire serial interface. These
devices include a 16-bit shift register and a doublebuffered input composed of an input register and a
DAC register (see
Functional Diagram
). In addition,
these devices employ a rail-to-rail output amplifier and
internal trimmed resistors to provide a gain of
+1.638V/V, maximizing the output voltage swing. The
MAX5174/MAX5176’s offset adjust pin allows for a DC
shift in DAC outputs. The DACs are designed with an
inverted R-2R ladder network (Figure 1) that produces
a weighted voltage proportional to the reference voltage.
Reference Inputs
The reference input accepts both AC and DC values
with a voltage range extending from 0 to VDD- 1.4V.
The following equation represents the resulting output
voltage:
where N is the numeric value of the DAC’s binary input
code (0 to 4095), V
REF
is the reference voltage, and
Gain is the internally set voltage gain (1.638V/V if OS =
AGND). The maximum output voltage is VDD. The reference pin has a minimum impedance of 18kΩ and is
code dependent.
Output Amplifier
With OS connected to AGND, the output amplifier
employs an internal trimmed resistor-divider, setting the
gain to 1.638V/V and minimizing gain error. The output
amplifier has a typical slew rate of 0.6V/µs, and settles
to ±0.5LSB from a full-scale transition within 18µs when
loaded with 5kΩ in parallel with 100pF. Loads less than
2kΩ degrade performance. For alternative output
amplifier setups, refer to the
Applications Information
section.
Shutdown Mode
The MAX5174/MAX5176 feature a software- and hardware-programmable shutdown mode that reduces the
typical supply current to 1µA. Enter shutdown by writing
the appropriate input-control word as shown in Table 1
or by using the hardware shutdown. In shutdown mode,
the reference input and amplifier output both become
high impedance, and the serial interface remains
active. Data in the input register is saved, allowing the
MAX5174/MAX5176 to recall the prior output state
when returning to normal operation. Exit shutdown by
reloading the DAC register from the shift register, by
simultaneously loading the input and DAC registers, or
by toggling PDL. When returning from shutdown wait
40µs for the output to settle.
Power-Down Lockout
Power-down lockout disables the software/hardware
shutdown mode. A high-to-low transition on PDL brings
the device out of shutdown and returns the output to its
previous state.
Shutdown
Pulling SHDN high while PDL is high places the
MAX5174/MAX5176 in shutdown. Pulling SHDN low will
not return the device to normal operation. A high-to-low
transition on PDL or an appropriate command from the
serial data line (see Table 1 for commands) is required
to exit shutdown.
Serial-Interface
The MAX5174/MAX5176 3-wire serial interface is compatible with SPI and QSPI (Figure 2), and MICROWIRE
(Figure 3) interface standards. The 16-bit serial input
word consists of two control bits, 12 bits of data (MSB
to LSB), and two sub-bits.
The control bits determine the MAX5174/MAX5176’s
response as outlined in Table 1. The MAX5174/
MAX5176’s digital inputs are double buffered, which
allows any of the following:
• Loading the input register without updating the DAC
register.
• Updating the DAC register from the input register.
• Updating the input and DAC registers simultaneously.
V
V N Gain
OUT
REF
=
⋅⋅
4096
OUT_
OS_
R
R
SHOWN FOR ALL 1s ON DAC
D0 D9 D10
D11
2R
2R 2R 2R 2R
RRR
REF_
AGND
Figure 1. Simplified DAC Circuit Diagram
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
______________________________________________________________________________________ 11
The MAX5174/MAX5176 accepts one 16-bit packet or
two 8-bit packets sent while CS remains low. The
MAX5174/MAX5176 allow the following to be configured:
• Clock edge on which serial data output (DOUT) is
clocked.
• State of the user-programmable logic output.
• Configuration of the reset state.
Specific commands for setting these are shown in
Table 1.
The general timing diagram in Figure 4 illustrates how
the MAX5174/MAX5176 acquires data. CS must go low
at least t
CSS
before the rising edge of the serial clock
(SCLK). With CS low, data is clocked into the register
on the rising edge of SCLK. The maximum serial clock
frequency guaranteed for proper operation is 10MHz
for the MAX5174 and 6MHz for the MAX5176. See
Figure 5 for a detailed timing diagram of the serial interface.
Serial Data Output (DOUT)
The serial-data output (DOUT) is the internal shift register’s output and allows for daisy-chaining of multiple
devices as well as data readback (see
Applications
Information
). By default upon start-up, data shifts out of
DOUT on the serial clock’s rising edge (Mode 0) and
provides a lag of 16 clock cycles, thus maintaining SPI,
QSPI, and MICROWIRE compatibility. However, if the
device is programmed for Mode 1, then the output data
lags DIN by 16.5 clock cycles and is clocked out on the
serial clock’s rising edge. During shutdown, DOUT
retains its last digital state prior to shutdown.
Load input register; DAC registers are updated (start-up DAC with
new data).
10
Load input register; DAC registers are unchanged.00
12-bit DAC data
12-bit DAC data
D11..................D0C1
FUNCTION
C0
No operation (NOP).11 0 0 x x xxxx xxxx
xxxxxxxxxxxx
Update DAC register from input register (start-up DAC with data
previously stored in the input registers).
01
UPO goes low (default).11 1 0 0 x xxxx xxxx
0 1 x x xxxx xxxx
Mode 1, DOUT clocked out on SCLK’s rising edge.11 1 1 0 x xxxx xxxx
1 0 1 x xxxx xxxx UPO goes high.11
Shut down DAC (provided PDL = 1).
11
Mode 0, DOUT clocked out on SCLK’s falling edge (default).11 1 1 1 x xxxx xxxx
Figure 2. Connections for SPI and QSPI Standards
SCLK
DIN
CS
SK
SO
I/O
MICROWIRE
PORT
MAX5174
MAX5176
Figure 3. Connections for MICROWIRE
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
0 0
0 0
S1, S0
xx
xx
xx
xx
xx
xx
xx
DIN
MAX5174
MAX5176
SCLK
CS
MOSI
SCK
I/O
CPOL = 0, CPHA = 0
+5V
SS
SPI/QSPI
PORT
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
12 ______________________________________________________________________________________
User-Programmable Logic Output (UPO)
The user-programmable logic output (UPO) allows control of an external device through the serial interface,
thereby reducing the number of microcontroller I/O pins
required. During power-down, this output will retain its
digital state prior to shutdown. When CLR is pulled low,
UPO will reset to its programmed default state. See
Table 1 for specific commands to control the UPO.
Reset (RS) and Clear (
CLR
)
The MAX5174/MAX5176 offers a clear pin (CLR), which
resets the output voltage. If RS = DGND, then CLR
resets the output voltage to 0. If RS = VDD, then CLR
resets the output voltage to mid-scale. In either case,
CLR will reset UPO to its programmed default state.
Applications Information
Unipolar Output
Figure 6 shows the MAX5174/MAX5176 configured for
unipolar, rail-to-rail operation with a gain of 1.638V/V.
Table 2 lists the codes for unipolar output voltages. The
output voltage is limited to V
DD
. Use the OS pin to introduce an offset voltage as shown in Figure 7 and
described in the
Offset and Buffer Configurations
section.
Bipolar Output
Figure 8 shows the MAX5174/MAX5176 configured for
bipolar output operation. The output voltage is given by
the following equation (OS = AGND):
where N represents the numeric value of the DAC’s
binary input code and V
REF
is the voltage of the external reference. Table 3 shows digital codes and the corresponding output voltage for Figure 8’s circuit.
VV
N
OUT REF
=
⋅
−
2
4096
1
CS
SCLK
DIN
COMMAND
EXECUTED
9
8
16
1
C1
C2 S0
C0
D9
D8
D7
D6 D3 D2 D1 D0 S2 S1D5 D4
Figure 4. Serial-Interface Timing Diagram
CS
SCLK
DIN
DOUT
t
CSW
t
CS1
t
CSH
t
CSS
t
CSO
t
D02
t
CH
t
CL
t
CP
t
D01
t
DS
t
DH
Figure 5. Detailed Serial-Interface Timing Diagram
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
Offset and Buffer Configurations
The simple circuit of Figure 7 illustrates how to introduce an offset to the output voltage. The amount of offset introduced by a voltage at the OS pin is shown in
the following equation:
V
OFFSET
= VOS· (1- Gain)
where Gain = 1.638.
However, the total output voltage of the device cannot
exceed VDD, regardless of the voltage on the OS pin.
To set the gain of the output amplifier to 1, connect OS
to OUT.
Daisy-Chaining Devices
The serial-data output pin (DOUT) allows multiple
MAX5174/MAX5176s to be daisy-chained together as
shown in Figure 9. The advantage of this is that only two
lines are needed to control all the DACs. The disadvantage is that it takes ncommands to program the DACs.
Figure 10 shows several MAX5174/MAX5176s sharing
one common DIN signal line. In this configuration the
data bus is common to all devices; however, more I/O
lines are required because each device needs a dedicated CS line. The advantage of this configuration is
that only one command is needed to program any DAC.
DAC CONTENTS
MSB LSB
11 1111 1111 11 (00)
10 0000 0000 01 (00)
+V
REF
(2049/4096) · 1.638
+V
REF
(4095/4096) · 1.638
ANALOG OUTPUT
10 0000 0000 00 (00)
+V
REF
(2048/4096) · 1.638
01 1111 1111 11 (00)
+V
REF
(2047/4096) · 1.638
00 0000 0000 01 (00)
+V
REF
(1/4096) · 1.638
00 0000 0000 00 (00) 0
Table 2. Unipolar Code Table
(Circuit of Figure 6)
MAX5174
MAX5176
DAC
REF
OUT
OS
DGNDAGND
+5V/+3V
V
DD
Figure 6. Unipolar Output Circuit (Rail-to-Rail)
DAC CONTENTS
MSB LSB
11 1111 1111 11 (00)
10 0000 0000 01 (00) +V
REF
[(2 · 2049/4096) - 1]
+V
REF
[(2 · 4095/4096) - 1]
ANALOG OUTPUT
01 1111 1111 11 (00) +V
REF
[(2 · 2047/4096) - 1]
00 0000 0000 01 (00) +V
REF
[(2 · 1/4096) - 1]
10 0000 0000 00 (00) +V
REF
[(2 · 2048/4096) - 1]
00 0000 0000 00 00 -V
REF
Table 3. Bipolar Code Table
(Circuit of Figure 8)
Figure 7. Setting OS for Output Offset
MAX5174
MAX5176
DAC
AGND DGND
REF
OUT
OS
V
OS
+5V/+3V
V
DD
________________________________________________________________________________________13
TOLERANCES: 10kΩ ±0.1%
AGNDDGND
MAX5174
MAX5176
DAC
REF
OS
OUT
10k 10k
V-
V+
VDD
V
OUT
+5V/+3V
Figure 8. Bipolar Output Circuit
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
14 ______________________________________________________________________________________
TO OTHER
SERIAL DEVICES
MAX5174
MAX5176
DIN
SCLK
CS
MAX5174
MAX5176
MAX5174
MAX5176
DINDOUT DOUT DOUT
SCLK
CS
DIN
SCLK
CS
Figure 9. Daisy-Chaining MAX5174/MAX5175 Devices
TO OTHER
SERIAL DEVICES
MAX5174
MAX5176
DIN
SCLK
CS
MAX5174
MAX5176
DIN
SCLK
CS
MAX5174
MAX5176
DIN
SCLK
CS
DIN
SCLK
CS1
CS2
CS3
Figure 10. Multiple MAX5174/MAX5176s Sharing Common DIN and SCLK Lines
Using an AC Reference
The MAX5174/MAX5176 accept references with AC
components, as long as the reference voltage remains
between 0 and VDD- 1.4V. Figure 11 shows a technique for applying a sine-wave signal to the reference
input where the AC signal is offset before being applied
to REF. The reference voltage must remain above
AGND.
Power-Supply and Layout Considerations
Wire-wrap boards are not recommended. For optimum
system performance, use printed circuit boards with
separate analog and digital ground planes. Connect
the two ground planes together at the low-impedance
power-supply source. Connect DGND and AGND pins
together at the IC. The best ground connection is
achieved by connecting the DAC’s DGND and AGND
pins together and connecting that point to the system
analog ground plane. This is useful because if the
DAC’s DGND is connected to the system digital
ground, digital noise may infiltrate the DAC’s analog
portion.
Bypass the power supply with a 4.7µF capacitor in parallel with a 0.1µF capacitor to AGND. Minimize capacitor lead lengths to reduce inductance. If noise
becomes an issue, use shielding and/or ferrite beads to
increase isolation.
To maintain INL and DNL performance as well as gain
drift, it is extremely important to provide the lowest possible reference output impedance at the DAC reference
input pin. INL degrades if the series resistance on REF
pin exceeds 0.1Ω. The same consideration must be
made for the AGND pin.
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
______________________________________________________________________________________ 15
Figure 11. AC Reference Input Circuit
DAC
OUT
MAX5174
MAX5176
R
2
R
1
OS
REF
V
DD
GNDAGND
+5V/
+3V
AC
REFERENCE
INPUT
500mVp-p
MAX495
+5V/+3V
TRANSISTOR COUNT: 3457
Chip Information
SHDN
PDL
RS
CLR
SCLKDINCS
MAX5174
MAX5176
SERIAL
CONTROL
16-BIT
SHIFT REGISTER
DECODE
CONTROL
LOGIC
OUTPUT
INPUT
REGISTER
DAC
REGISTER
DAC
DOUT
UPO
OS
OUT
REF
DGNDAGND
V
DD
Functional Diagram
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
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© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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