Rainbow Electronics MAX5159 User Manual

Page 1

_______________General Description

The MAX5158/MAX5159 low-power, serial, voltageoutput, dual, 10-bit digital-to-analog converters (DACs) consume only 500µA from a single +5V (MAX5158) or +3V (MAX5159) supply. These devices feature Rail-toRail

output swing and are available in a space-saving 16-pin QSOP package. To maximize dynamic range, the DAC output amplifiers are configured with an internal gain of +2V/V.

The 3-wire serial interface is SPI™/QSPI™ and Microwire™ compatible. Each DAC has a doublebuffered input organized as an input register followed by a DAC register, which allows the input and DAC registers to be updated independently or simultaneously with a 16-bit serial word. Additional features include a 2µA programmable shutdown, hardware-shutdown lockout, a separate reference-voltage input for each DAC that accepts AC and DC signals, and an active-low clear input (

CL) that resets all registers and DACs to zero. The MAX5158/MAX5159 provide a programmable logic pin for added functionality and a serial-data output pin for daisy chaining.

________________________Applications

Digital Offset and Gain Adjustment µP-Controlled Systems Motion Control Remote Industrial Controls

____________________________Features

♦ 10-Bit Dual DAC with Internal Gain of +2V/V ♦ Rail-to-Rail Output Swing ♦ 8µs Settling Time ♦ Single-Supply Operation: +5V (MAX5158)

+3V (MAX5159)

♦ Low Quiescent Current: 500µA (normal operation)

2µA (shutdown mode)

♦ SPI/QSPI and Microwire Compatible ♦ Available in Space-Saving 16-Pin QSOP Package ♦

Power-On Reset Clears Registers and DACs to Zero

♦ Adjustable Output Offset

______________Ordering Information

Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. Microwire is a trademark of National Semiconductor Corp. SPI and QSPI are trademarks of Motorola, Inc.

Ordering Information continued at end of data sheet.

Contact factory for availability.

REFA

AGND

DGNDPDLCL

DOUT

16-BIT

SHIFT

CONTROL

INPUT REG A

INPUT REG B

SCLK

UPO REFB

DINCS

DAC B

DAC A

DAC

REG A

LOGIC

OUTPUT

DECODE

CONTROL

DAC

REG B

MAX5158 MAX5159

OUTB

OSB

OUTA

OSA

_________________________________________________________Functional Diagram

MAX5158/MAX5159

Low-Power, Dual, 10-Bit, Voltage-Output DACs

with Serial Interface

________________________________________________________________

Maxim Integrated Products

19-1315; Rev 1; 12/97

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 For small orders, phone 408-737-7600 ext. 3468.

PIN-PACKAGETEMP. RANGEPART

16 QSOP-40°C to +85°CMAX5158EEE

16 Plastic DIP

16 QSOP

16 Plastic DIP0°C to +70°C

0°C to +70°C

-40°C to +85°CMAX5158EPE

MAX5158CEE

MAX5158CPE

16 CERDIP*-55°C to +125°CMAX5158MJE

Page 2

MAX5158/MAX5159

Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS—MAX5158

(VDD= +5V ±10%, V

REFA

= V

REFB

= 2.048V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are

at T

= +25°C (OS_ tied to AGND for a gain of +2V/V).)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VDDto AGND............................................................-0.3V to +6V

to DGND ...........................................................-0.3V to +6V

AGND to DGND..................................................................±0.3V

OSA, OSB to AGND........................(AGND - 4V) to (V

+ 0.3V)

REF_, OUT_ to AGND.................................-0.3V to (V

+ 0.3V)

Digital Inputs (SCLK, DIN, CS, CL, PDL)

to DGND............................................................(-0.3V to +6V)

Digital Outputs (DOUT, UPO)

to DGND................................................-0.3V to (V

+ 0.3V)

Maximum Current into Any Pin.........................................±20mA

Continuous Power Dissipation (T

= +70°C)

Plastic DIP (derate 10.5mW/°C above +70°C) ...........842mW

QSOP (derate 8.30mW/°C above +70°C)...................667mW

CERDIP (derate 10.00mW/°C above +70°C)..............800mW

Operating Temperature Ranges

MAX515_ _C_ E .................................................0°C to +70°C

MAX515_ _E_ E ..............................................-40C° to +85°C

MAX515_ _MJE.............................................-55°C to +125°C

Storage Temperature Range.............................-65°C to +160°C

Lead Temperature (soldering, 10sec).............................+300°C

VIN= 0V to V

CL, PDL, CS, DIN, SCLK

Input code = 1FF8 hex, V

REF_

= 1Vp-p at 1.25VDC, f = 25kHz

Input code = 0000 hex, V

REF_

= (VDD- 1.4 Vp-p) at 1kHz

Input code = 1FF8 hex, V

REF_

= 0.67Vp-p at 0.75V

2.7V ≤

≤ 5.5V

Normalized to 2.048V

Guaranteed monotonic Code = 2 Normalized to 2.048V

Minimum with code 1558 hex

CONDITIONS

pF8C

Input Capacitance

µA0.001 ±1I

Input Leakage Current

mV200V

HYS

Input Hysteresis

V0.8V

Input Low Voltage

V3V

Input High Voltage

dB75SINAD

Signal-to-Noise plus Distortion Ratio

dB-82Reference Feedthrough

kHz300Reference 3dB Bandwidth

kΩ

18 25R

REF

Reference Input Resistance

LSB±1INLIntegral Nonlinearity

Bits10Resolution

V0 VDD- 1.4REFReference Input Range

µV/V20 260PSRR

VDDPower-Supply Rejection Ratio

ppm/°C4Gain-Error Tempco

LSB±1DNLDifferential Nonlinearity

mV±6V

OS_

Offset Error

ppm/°C4TCV

Offset Tempco

LSB-0.1 1Gain Error

UNITSMIN TYP MAXSYMBOLPARAMETER

(Note 1)

STATIC PERFORMANCE

REFERENCE INPUT

MULTIPLYING-MODE PERFORMANCE

DIGITAL INPUTS

Page 3

MAX5158/MAX5159

Low-Power, Dual, 10-Bit, Voltage-Output DACs

with Serial Interface

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS—MAX5158 (continued)

(VDD= +5V ±10%, V

REFA

= V

REFB

= 2.048V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are

at T

= +25°C (OS_ tied to AGND for a gain of +2V/V).)

Note 1: Accuracy is specified from code 2 to code 1023. Note 2: Accuracy is better than 1LSB for V

OUT

_ greater than 6mV and less than VDD- 50mV. Guaranteed by PSRR test at the

end points.

Note 3: Digital inputs are set to either V

or DGND, code = 0000 hex, RL= ∞.

Note 4: SCLK minimum clock period includes rise and fall times.

CS = VDD, f

DIN

= 100kHz, V

SCLK

= 5Vp-p

SOURCE

= 2mA

(Note 4)

(Note 3)

Rail-to-rail (Note 2)

To 1/2LSB of full-scale, V

STEP

= 4V

SINK

= 2mA

SCLK Pulse Width Low

CONDITIONS

ns40t

SCLK Pulse Width High

nV-s5Digital Crosstalk

nV-s5Digital Feedthrough

µs25Time Required to Exit Shutdown

kΩ24 34R

OS_

OSA or OSB Input Resistance

ns100t

SCLK Clock Period

µA0 ±1Reference Current in Shutdown

µA2 10I

DD(SHDN)

Power-Supply Current in Shutdown

mA0.5 0.65I

Power-Supply Current

V4.5 5.5V

Positive Supply Voltage

ns40t

SDI Setup Time

VVDD- 0.5V

Output High Voltage

CSH

SCLK Rise to CS Rise Hold Time

ns40t

CSS

CS Fall to SCLK Rise Setup Time

LOAD

= 200pF

V0 to V

Output Voltage Swing

µs8Output Settling Time

LOAD

= 200pF

ns80

V0.13 0.4V

Output Low Voltage

V/µs0.75SRVoltage Output Slew Rate

UNITSMIN TYP MAXSYMBOLPARAMETER

DO2

SCLK Fall to DOUT Valid Propagation Delay

ns80t

DO1

SCLK Rise to DOUT Valid Propagation Delay

ns0t

SDI Hold Time

ns100t

CSW

CS Pulse Width High

ns40t

CS1

CS Rise to SCLK Rise Hold

ns10t

CS0

SCLK Rise to CS Fall Delay

DIGITAL OUTPUTS (DOUT, UPO)

DYNAMIC PERFORMANCE

POWER SUPPLIES

TIMING CHARACTERISTICS

Page 4

MAX5158/MAX5159

Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS—MAX5159

(VDD= +2.7V to +3.6V, V

REFA

= V

REFB

= 1.25V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

= +25°C (OS_ pins tied to AGND for a gain of +2V/V).)

VIN= 0V to V

CL, PDL, CS, DIN, SCLK

Input code = 1FF8 hex, V

REF_

= 1Vp-p at 1VDC, f = 15kHz

Input code = 0000 hex, V

REF_

= (VDD- 1.4)Vp-p at 1kHz

Input code = 1FF8 hex, V

REF_

= 0.67Vp-p at 0.75V

2.7V ≤

VDD

≤ 3.6V

Normalized to 1.25V

Guaranteed monotonic Code = 3 Normalized to 1.25V

Minimum with code 1558 hex

CONDITIONS

pF8C

Input Capacitance

µA0 ±1I

Input Leakage Current

mV200V

HYS

Input Hysteresis

V0.8V

Input Low Voltage

V2.2V

Input High Voltage

dB73SINAD

Signal-to-Noise plus Distortion Ratio

dB-82Reference Feedthrough

kHz300Reference 3dB Bandwidth

kΩ

18 25R

REF

Reference Input Resistance

LSB±1INLIntegral Nonlinearity

Bits10Resolution

V0 VDD- 1.4REFReference Input Range

µV/V40 320PSRR

VDDPower-Supply Rejection Ratio

ppm/°C6.5Gain-Error Tempco

LSB±1DNLDifferential Nonlinearity

mV±6V

Offset Error

ppm/°C6.5TCV

Offset Tempco

LSB-0.1 ±1Gain Error

UNITSMIN TYP MAXSYMBOLPARAMETER

SOURCE

= 2mA VVDD- 0.5V

Output High Voltage

SINK

= 2mA V0.13 0.4V

Output Low Voltage

V/µs0.75SRVoltage Output Slew Rate

To 1/2LSB of full-scale, V

STEP

= 2.5V µs8Output Settling Time

Rail-to-rail (Note 6) V0 to V

Output Voltage Swing

kΩ

24 34R

OS_

OSA or OSB Input Resistance

µs25

Time Required for Valid Operation after Shutdown

CS = VDD, f

DIN

= 100kHz, V

SCLK

= 3Vp-p

nV-s5Digital Feedthrough nV-s5Digital Crosstalk

MULTIPLYING-MODE PERFORMANCE

STATIC PERFORMANCE

REFERENCE INPUT (VREF)

DIGITAL INPUTS

DIGITAL OUTPUTS

DYNAMIC PERFORMANCE (DOUT, UPO)

(Note 5)

Page 5

MAX5158/MAX5159

Low-Power, Dual, 10-Bit, Voltage-Output DACs

with Serial Interface

_______________________________________________________________________________________ 5

Note 5: Accuracy is specified from code 3 to code 1023. Note 6: Accuracy is better than 1LSB for V

OUT

greater than 6mV and less than VDD- 80mV. Guaranteed by PSRR test at the end

points.

Note 7: Digital inputs are set to either V

or DGND, code = 0000 hex, RL= ∞.

ELECTRICAL CHARACTERISTICS—MAX5159 (continued)

(VDD= +2.7V to +3.6V, V

REFA

= V

REFB

= 1.25V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

= +25°C (OS_ pins tied to AGND for a gain of +2V/V).)

(Note 4)

(Note 7)

ns40t

SCLK Pulse Width Low

CONDITIONS

ns40t

SCLK Pulse Width High

ns100t

SCLK Clock Period

µA±1

Reference Current in Shutdown

µA1 8I

DD(SHDN)

Power-Supply Current in Shutdown

mA0.5 0.6I

Power-Supply Current

V2.7 3.6V

Positive Supply Voltage

ns50t

SDI Setup Time

ns0t

CSH

SCLK Rise to CS Rise Hold Time

ns40t

CSS

CS Fall to SCLK Rise Setup Time

LOAD

= 200pF

LOAD

= 200pF

ns120

UNITSMIN TYP MAXSYMBOLPARAMETER

DO2

SCLK Fall to DOUT Valid Propagation Delay

ns120t

DO1

SCLK Rise to DOUT Valid Propagation Delay

ns0t

SDI Hold Time

ns100t

CSW

CS Pulse Width High

ns40t

CS1

CS Rise to SCLK Rise Hold

ns10t

CS0

SCLK Rise to CS Fall Delay

POWER SUPPLIES

TIMING CHARACTERISTICS

Page 6

MAX5158/MAX5159

Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface

6 _______________________________________________________________________________________

__________________________________________Typical Operating Characteristics

(VDD= +5V, RL= 10kΩ, CL= 100pF, OS_ pins tied to AGND, TA= +25°C, unless otherwise noted.)

-20

-16

-18

-12

-14

-8

-10

-6

-2

-4

1 370 740 1110 1480 1850

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

MAX5158/5159-01

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

REF

= 0.67Vp-p @ 2.5V

CODE = 1FF8 (HEX)

400

450

550

500

650

600

700

-55 5-15-35 4525 65 10585 125

SUPPLY CURRENT vs. TEMPERATURE

MAX5158/5159 toc02

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

REF

= 2.048V

= ∞

CODE = 1FF8 (HEX)

CODE = 0000 (HEX)

-30

-80 1 10 100

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

-70

MAX5158/5159 toc03

FREQUENCY (kHz)

THD + NOISE (dB)

-60

-50

-40

REF

= 1Vp-p @ 2.5V

CODE = 1FF8 (HEX)

0.1 1 10 100

FULL-SCALE ERROR vs. RESISTIVE LOAD

-0.75

-1.0

-0.5

-0.25

0.25

0.50

MAX5158/5159 toc04

RL (kΩ)

FULL-SCALE ERROR (LSB)

-100

-80

-90

-60

-70

-40

-50

0.5 1.6 2.7 3.8 4.9 6.0

-30

-10

-20

OUTPUT FFT PLOT

MAX5158/5159 toc07

REF

= 2.45Vp-p @ 1.225V

f = 1kHz CODE = 1FF8 (HEX)

NOTE: RELATIVE TO FULL-SCALE

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

-150

-130

-140

-110

-120

-90

-100

-80

-60

-70

-50

0.5 1.5 2.0 2.51.0 3.0 3.5 4.0 5.04.5 5.5

REFERENCE FEEDTHROUGH AT 1kHz

MAX5158/5159 toc05

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

REF

= 3.6Vp-p @ 1.88V

CODE = 0000 (HEX)

-55 5 25-15-35 45 65 85 105 125

SHUTDOWN CURRENT

vs. TEMPERATURE

MAX5158/5159 toc06

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

REF

= 1V

DYNAMIC RESPONSE RISE TIME

MAX5158/5159 toc08

2µs/div

OUT_ 1V/div

5V/div

REF

= 2.048V

2µs/div

DYNAMIC RESPONSE FALL TIME

MAX5158/5159 toc09

REF

= 2.048V

OUT_ 1V/div

5V/div

MAX5158

Page 7

MAX5158/MAX5159

Low-Power, Dual, 10-Bit, Voltage-Output DACs

with Serial Interface

_______________________________________________________________________________________ 7

____________________________Typical Operating Characteristics (continued)

(VDD= +3V, RL= 10kΩ, CL= 100pF, OS_ pins tied to AGND, TA= +25°C, unless otherwise noted.)

-20

-16

-18

-12

-14

-8

-10

-6

-2

-4

1 320 640 960 1280 1600

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

MAX5158/5159 toc10

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

REF

= 0.67Vp-p @ 0.75V

CODE = 1FF8

400

440 420

500 480 460

540 520

560

-55 5 25-35 -15 45 65 85 105 125

SUPPLY CURRENT vs. TEMPERATURE

MAX5158/5159 toc11

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

REF

= 1V

= ∞

CODE = 1FF8 (HEX)

CODE = 0000 (HEX)

-30

-80 1 10 100

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

-70

MAX5158/5159 toc12

FREQUENCY (kHz)

THD + NOISE (dB)

-60

-50

-40

REF

= 1Vp-p @ 1V

CODE = 1FF8 (HEX)

0.50

-1.00

0.1 1 10 100

FULL-SCALE ERROR vs. RESISTIVE LOAD

-0.25

-0.50

-0.75

0.25

MAX5158/5159 toc13

RL (kΩ)

FULL-SCALE ERROR (LSB)

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0.5 2.7 3.8 4.91.6 6.0

OUTPUT FFT PLOT

MAX5158/5159toc16

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

REF

= 1.4Vp-p @ 0.75V

f = 1kHz CODE = 1FF8 (HEX)

-150

-130

-140

-110

-120

-90

-100

-80

-60

-70

-50

0.5 1.5 2.0 2.51.0 3.0 3.5 4.0 5.04.5 5.5

REFERENCE FEEDTHROUGH AT 1kHz

MAX5158/5159 toc14

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

REF

= 1.6Vp-p @ 0.88V

CODE = 0000 (HEX)

1.2

1.0

1.6

1.4

2.0

1.8

2.2

2.4

2.8

2.6

3.0

-55 -15 5 25-35 45 65 85 105 125

SHUTDOWN CURRENT

vs. TEMPERATURE

MAX5158/5159 toc15

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

REF

= 1V

= ∞

DYNAMIC RESPONSE FALL TIME

MAX5158/5159 toc18

REF

= 1.25V

2µs/div

OUT_ 500mV/div

CS 2V/div

DYNAMIC RESPONSE RISE TIME

MAX5158/5159 toc17

2µs/div

REF =

1.25V

OUT_ 500mV/div

2V/div

MAX5159

Page 8

MAX5158/MAX5159

Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface

8 _______________________________________________________________________________________

_____________________________Typical Operating Characteristics (continued)

(VDD= +5V (MAX5158), VDD= +3V (MAX5159), RL= 10kΩ, CL= 100pF, OS_ pins tied to AGND, unless otherwise noted.)

0.40

0.45

0.50

0.55

0.60

4.50 4.75 5.00 5.25 5.50

MAX5158

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX5158/5159 TOC19

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

CODE = 0000 (HEX)

CODE = 1FF8 (HEX)

0.40

0.45

0.50

0.55

0.60

2.7 3.0 3.3 3.6

MAX5159

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX5158/5159 TOC19a

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

CODE = 0000 (HEX)

CODE = 1FF8 (HEX)

OUTB 200µV/div AC COUPLED

OUTA 5V/div

MAX5158

ANALOG CROSSTALK

MAX5158/5159 toc21

REF

= 2.048V, GAIN = +2V/V, CODE = 1FF8 HEX

250µs/div

MAX5158

DIGITAL FEEDTHROUGH

MAX5158/5159 toc22

OUTA 500µV/div AC COUPLED

SCLK 5V/div

2.5µs/div

5µs/div

MAX5158

MAJOR-CARRY TRANSITION

MAX5158/5159 toc20

TRANSITION FROM 1000 (HEX) TO 0FF8 (HEX)

OUT_ 50mV/div AC COUPLED

2V/div

MAX5158/MAX5159

Page 9

_______________Detailed Description

The MAX5158/MAX5159 dual, 10-bit, voltage-output DACs are easily configured with a 3-wire serial interface. These devices include a 16-bit data-in/data-out shift register, and each DAC has a double-buffered input composed of an input register and a DAC register (see

Functional Diagram

). In addition, trimmed internal resistors produce an internal gain of +2V/V that maximizes output voltage swing. The amplifier’s offset-adjust pin allows for a DC shift in the DAC’s output.

Both DACs use an inverted R-2R ladder network that produces a weighted voltage proportional to the input voltage value. Each DAC has its own reference input to facilitate independent full-scale values. Figure 1 depicts a simplified circuit diagram of one of the two DACs.

Reference Inputs

The reference inputs accept both AC and DC values with a voltage range extending from 0V to (VDD- 1.4V). Determine the output voltage using the following equation (OS_ = AGND):

OUT

= (V

REF

x NB / 1024) x 2

where NB is the numeric value of the DAC’s binary input code (0 to 1023) and V

REF

is the reference voltage.

The reference input impedance ranges from 18kΩ (1558 hex) to several giga ohms (with an input code of 0000 hex). The reference input capacitance is code dependent and typically ranges from 15pF with an input code of all zeros to 50pF with a full-scale input code.

Output Amplifier

The output amplifiers on the MAX5158/MAX5159 have internal resistors that provide for a gain of +2V/V when OS_ is connected to AGND. These resistors are trimmed to minimize gain error. The output amplifiers have a typical slew rate of 0.75V/µs and settle to 1/2LSB within 8µs, with a load of 10kΩ in parallel with 100pF. Loads less than 2kΩ degrade performance.

The OS_ pin can be used to produce an adjustable offset voltage at the output. For instance, to achieve a 1V offset, apply -1V to the OS_ pin to produce an output range from 1V to (1V + V

REF

x 2). Note that the DAC’s output range is still limited by the maximum output voltage specification.

Power-Down Mode

The MAX5158/MAX5159 feature a software-programmable shutdown mode that reduces the typical supply current to 2µA. The two DACs can be shutdown independently, or simultaneously using the appropriate programming command. Enter shutdown mode by writing the appropriate input-control word (Table 1). In shutdown mode, the reference inputs and amplifier out- puts become high impedance, and the serial interface

MAX5158/MAX5159

Low-Power, Dual, 10-Bit, Voltage-Output DACs

with Serial Interface

_______________________________________________________________________________________ 9

Digital GroundDGND9 Serial-Data OutputDOUT10 User-Programmable OutputUPO11

Power-Down Lockout. The device cannot be powered down when PDL is low.

PDL

Reference for DAC BREFB13

Active-Low Clear Input. Resets all registers to zero. DAC outputs go to 0V.

Chip-Select Input

Serial-Data Input DIN7 Serial Clock Input SCLK8

Reference for DAC A REFA4

DAC A Offset AdjustmentOSA3

DAC A Output Voltage OUTA2

Analog Ground AGND1

FUNCTIONNAME

14 OSB DAC B Offset Adjustment 15 OUTB DAC B Output Voltage 16 V

Positive Power Supply

Figure 1. Simplified DAC Circuit Diagram

_____________________Pin Description

OS_

R R R

2R 2R 2R 2R

D0 D7 D8

REF_

AGND

SHOWN FOR ALL 1s ON DAC

OUT_

Page 10

MAX5158/MAX5159

remains active. Data in the input registers is saved, allowing the MAX5158/MAX5159 to recall the output state prior to entering shutdown when returning to normal mode. Exit shutdown by recalling the previous condition or by updating the DAC with new information. When returning to normal operation (exiting shutdown), wait 20µs for output stabilization.

Serial Interface

The MAX5158/MAX5159 3-wire serial interface is compatible with both Microwire (Figure 2) and SPI/QSPI (Figure 3) serial-interface standards. The 16-bit serial input word consists of an address bit, two control bits, 10 bits of data (MSB to LSB), and 3 sub-bits as shown in Figure 4. The address and control bits determine the MAX5158/MAX5159’s response, as outlined in Table 1.

Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface

10 ______________________________________________________________________________________

FUNCTION

A0 C1 C0

D9..........................D0

(MSB) (LSB)

0 0 1 10-bit DAC data Load input register A; DAC registers are unchanged.

0 1 1 10-bit DAC data

Load all DAC registers from the shift register (start up both DACs with new data.).

1 1 0 10-bit DAC data Load input register B; all DAC registers are updated.

0 1 0 10-bit DAC data Load input register A; all DAC registers are updated.

1 0 1 10-bit DAC data Load input register B; DAC registers are unchanged.

0 0 0 1 1 0 x xxxxxx

Shut down DAC A (provided PDL = 1).

0 0 0 1 0 1 x xxxxxx

Update DAC register B from input register B (start up DAC B with data previously stored in input register B).

0 0 0 0 0 1 x xxxxxx

Update DAC register A from input register A (start up DAC A with data previously stored in input register A).

1 1 1 xxxxxxxxxx

Shut down both DACs (provided PDL = 1).

1 0 0 xxxxxxxxxx

Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers).

0 0 0 1 1 1 x xxxxxx

Shut down DAC B (provided PDL = 1). 0 0 0 0 1 0 x xxxxxx UPO goes low (default). 0 0 0 0 1 1 x xxxxxx UPO goes high. 0 0 0 1 0 0 1 xxxxxx Mode 1, DOUT clocked out on SCLK’s rising edge. 0 0 0 1 0 0 0 xxxxxx Mode 0, DOUT clocked out on SCLK’s falling edge (default). 0 0 0 0 0 0 x xxxxxx No operation (NOP).

Table 1. Serial-Interface Programming Command

x = Don’t care Note: When A0, C1, and C0 = 0, then D9, D8, D7, and D6 become control bits. S2–S0 are sub bits, always zero.

SCLK

DIN

I/O

MAX5158 MAX5159

MICROWIRE

PORT

Figure 2. Connections for Microwire

16-BIT SERIAL WORD

S2–S0

0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Page 11

The MAX5158/MAX5159’s digital inputs are double buffered, which allows any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC registers concurrently. The address and control bits allow the DACs to act independently.

Send the 16-bit data as one 16-bit word (QSPI) or two 8-bit packets (SPI, Microwire), with CS low during this period. The address and control bits determine which register will be updated and the state of the registers when exiting shutdown. The 3-bit address/control determines the following:

• registers to be updated

• clock edge on which data is to be clocked out via the serial-data output (DOUT)

• state of the user-programmable logic output

• configuration of the device after shutdown.

The general timing diagram of Figure 5 illustrates how data is acquired. Driving CS low enables the device to receive data. Otherwise, the interface control circuitry is disabled. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. As CS goes high, data is latched into the input and/or DAC registers, depending on the address and control bits. The maximum clock frequency guaranteed for proper operation is 10MHz. Figure 6 depicts a more detailed timing diagram of the serial interface.

MAX5158/MAX5159

Low-Power, Dual, 10-Bit, Voltage-Output DACs

with Serial Interface

DIN

SCLK

MOSI

SCK

I/O

SPI/QSPI

PORT

+5V

CPOL = 0, CPHA = 0

MAX5158 MAX5159

Figure 3. Connections for SPI/QSPI

Figure 5. Serial-Interface Timing Diagram

SCLK

DIN

COMMAND

EXECUTED

A0 S0

D6 D3 D2 D1 D0 S2 S1D5 D4

______________________________________________________________________________________ 11

Figure 4. Serial-Data Format

MSB..................................................................................LSB

16 Bits of Serial Data

Address Bits Control Bits MSB....DataBits...LSB Sub Bits

A0 C1, C0

D9.................. ......D0

S2–S0

1 Address/

2 Control Bits

10 Data Bits

000

Page 12

MAX5158/MAX5159

Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface

12 ______________________________________________________________________________________

SCLK

DIN

CSO

CSS

CSW

CS1

CSH

Figure 6. Detailed Serial-Interface Timing Diagram

TO OTHER SERIAL DEVICES

MAX5158 MAX5159

DIN

SCLK

MAX5158 MAX5159

DINDOUT DOUT DOUT

SCLK

DIN

SCLK

Figure 7. Daisy Chaining MAX5158/MAX5159s

Figure 8. Multiple MAX5158/MAX5159s Sharing a Common DIN Line

DIN

SCLK

CS1 CS2

CS3

MAX5158 MAX5159

SCLK

DIN

SCLK

DIN

MAX5158 MAX5159

SCLK

DIN

TO OTHER SERIAL DEVICES

Page 13

Serial-Data Output

The serial-data output, DOUT, is the internal shift register’s output. DOUT allows for daisy chaining of devices and data readback. The MAX5158/MAX5159 can be programmed to shift data out of DOUT on SCLK’s falling edge (Mode 0) or on the rising edge (Mode 1). Mode 0 provides a lag of 16 clock cycles, which maintains compatibility with SPI/QSPI and Microwire interfaces. In Mode 1, the output data lags 15.5 clock cycles. On power-up, the device defaults to Mode 0.

User-Programmable Logic Output (UPO)

UPO allows an external device to be controlled through the serial interface (Table 1), thereby reducing the number of microcontroller I/O pins required. On power-up, UPO is low.

Power-Down Lockout Input (

PPDDLL

)

The power-down lockout pin (PDL) disables software shutdown when low. When in shutdown, transitioning PDL from high to low wakes up the part with the output set to the state prior to shutdown. PDL can also be used to asynchronously wake up the device.

Daisy Chaining Devices

Any number of MAX5158/MAX5159s can be daisy chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain (Figure 7).

Since the MAX5158/MAX5159’s DOUT pin has an internal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive

load. Refer to the digital output V

and VOLspecifica-

tions in the

Electrical Characteristics

Figure 8 shows an alternate method of connecting several MAX5158/MAX5159s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC.

__________Applications Information

Unipolar Output

Figure 9 shows the MAX5158/MAX5159 configured for unipolar, rail-to-rail operation with a gain of +2V/V. The MAX5158 can produce a 0V to 4.096V output with a

2.048V reference (Figure 9), while the MAX5159 can

MAX5158/MAX5159

Low-Power, Dual, 10-Bit, Voltage-Output DACs

with Serial Interface

Table 2. Unipolar Code Table (Gain = +2)

MAX5158 MAX5159

DAC_

GAIN = +2V/V

REF_

OUT_

OS_

DGNDAGND

+5V/+3V

Figure 9. Unipolar Output Circuit (Rail-to-Rail)

MAX5158 MAX5159

DAC _

AGND DGND

REF_

OUT_

OS_

+5V/+3V

______________________________________________________________________________________ 13

ANALOG OUTPUT

11 1111 1111 (000)

10 0000 0001 (000)

DAC CONTENTS

MSB LSB

10 0000 0000 (000)

01 1111 1111 (000)

00 0000 0000 (000) 0V

00 0000 0001 (000)

Figure 10. Setting OS_ for Output Offset

Note: ( ) are for the sub bits.





1023



REF







REF





512



REF REF

1024







REF

 



REF



1024

513

1024

 



511

1024

x 2







x 2





x 2 V



x 2



 





Page 14

MAX5158/MAX5159

produce a range of 0V to 2.5V with a 1.25V reference. Table 2 lists the unipolar output codes. An offset to the output can be achieved by connecting a voltage to OS_, as shown in Figure 10. By applying VOS_ = -1V, the output values will range between 1V and (1V + V

REF

x 2).

Bipolar Output

The MAX5158/MAX5159 can be configured for a bipolar output, as shown in Figure 11. The output voltage is given by the equation (OS_ = AGND):

OUT

= V

REF

[((2 x NB) / 1024) - 1]

where NB represents the numeric value of the DAC’s binary input code. Table 3 shows digital codes and the corresponding output voltage for Figure 11’s circuit.

Using an AC Reference

In applications where the reference has an AC signal component, the MAX5158/MAX5159 have multiplying capabilities within the reference input voltage range specifications. Figure 12 shows a technique for applying a sinusoidal input to REF_, where the AC signal is offset before being applied to the reference input.

Harmonic Distortion and Noise

The total harmonic distortion plus noise (THD+N) is typically less than -78dB at full scale with a 1Vp-p input swing at 5kHz. The typical -3dB frequency is 300kHz for both devices, as shown in the

Typical Operating

Characteristics.

Low-Power, Dual, 10-Bit Voltage-Output DACs with Serial Interface

14 ______________________________________________________________________________________

Table 3. Bipolar Code Table

ANALOG OUTPUT

11 1111 1111 (000)

10 0000 0001 (000)

DAC CONTENTS

MSB LSB

10 0000 0000 (000) 0V

01 1111 1111 (000)

00 0000 0000 (000)

00 0000 0001 (000)

Figure 11. Bipolar Output Circuit

DAC_

OUT_

MAX5158 MAX5159

10k

26k

OS_

REF

DGNDAGND

+5V/

+3V

REFERENCE

INPUT

500mVp-p

MAX495

+5V/+3V

Figure 12. AC Reference Input Circuit

AGND

DIN

µP

DGND

MAX5158 MAX5159

DAC _

REF_

OS_

OUT_

V-

V+

PHOTODIODE

V+

VDD

OUT

PULLDOWN

+5V/+3V

Figure 13. Digital Calibration

Note: ( ) are for the sub bits.

REF

-V

REF

-V

REF



512

-V



REF REF

512



REF_

+5V/+3V

VDD

10k 10k

OS_

MAX5158 MAX5159

DAC _

AGNDDGND

10k

OUT_

10k

 



 



 

 





511

512

512 511

512

 



 

 









 





- V

V+

OUT

V-

Page 15

Digital Calibration and

Threshold Selection

Figure 13 shows the MAX5158/MAX5159 in a digital calibration application. With a bright light value applied to the photodiode (on), the DAC is digitally ramped until it trips the comparator. The microprocessor (µP) stores this “high” calibration value. Repeat the process with a dim light (off) to obtain the dark current calibration. The µP then programs the DAC to set an output voltage at the midpoint of the two calibrated values. Applications include tachometers, motion sensing, automatic readers, and liquid clarity analysis.

Digital Control of Gain and Offset

The two DACs can be used to control the offset and gain for curve-fitting nonlinear functions, such as transducer linearization or analog compression/expansion applications. The input signal is used as the reference for the gain-adjust DAC, whose output is summed with the output from the offset-adjust DAC. The relative weight of each DAC output is adjusted by R1, R2, R3, and R4 (Figure 14).

Power-Supply Considerations

On power-up, the input and DAC registers clear (set to zero code). For rated performance, V

REF_

should be at

least 1.4V below VDD. Bypass the power supply with a

4.7µF capacitor in parallel with a 0.1µF capacitor

to AGND. Minimize lead lengths to reduce lead inductance.

Grounding and Layout Considerations

Digital and AC transient signals on AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required.

MAX5158/MAX5159

Low-Power, Dual, 10-Bit, Voltage-Output DACs

with Serial Interface

______________________________________________________________________________________ 15

AGND DGND

MAX5158 MAX5159

DACA

VDD

REFA

REF

SCLK

DIN

REFB

OUTB

OSB

OUTA

OSA

OUT

DACB

INPUT REG A

INPUT REG B

DAC

REG A

DAC

REG B

– OFFSET

[ ]

OUT

GAIN

[ ]

2NA

1024

NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA. NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.

R1+R2R4R3

2NB

1024

R4 R3

(

)(

)

(

REF

)(

)

[ ] [ ]

SHIFT

Figure 14. Digital Control of Gain and Offset

Page 16

MAX5158/MAX5159

Low-Power, Dual, 13-Bit Voltage-Output DACs with Serial Interface

16 15 14 13 12 11 10

1 2 3 4 5 6 7 8

AGND V

OUTB OSB REFB PDL UPO DOUT DGND

TOP VIEW

MAX5158 MAX5159

DIP/QSOP

OUTA

OSA

REFA

DIN

SCLK

Contact factory for availability.

___________________Chip Information

TRANSISTOR COUNT: 3053 SUBSTRATE CONNECTED TO AGND

_Ordering Information (continued)__________________Pin Configuration

QSOP.EPS

________________________________________________________Package Information

PART TEMP. RANGE PIN-PACKAGE

MAX5159CPE

0°C to +70°C 16 Plastic DIP

MAX5159MJE -55°C to +125°C 16 CERDIP*

MAX5159CEE 0°C to +70°C 16 QSOP

MAX5159EEE -40°C to +85°C 16 QSOP

MAX5159EPE -40°C to +85°C 16 Plastic DIP

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600