Rainbow Electronics MAX5157 User Manual

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MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs

with Configurable Outputs

________________________________________________________________

Maxim Integrated Products

1

19-1317; Rev 1; 12/97

_______________General Description

The MAX5156/MAX5157 low-power, serial, voltage-out­put, dual 12-bit digital-to-analog converters (DACs)
consume only 500µA from a single +5V (MAX5156) or
+3V (MAX5157) supply. These devices feature Rail-to­Rail®output swing and are available in space-saving
16-pin QSOP and DIP packages. Access to the invert­ing input allows for specific gain configurations, remote
sensing, and high output current capability, making
these devices ideally suited for industrial process con­trols. These devices are also well suited for digitally
programmable (4–20mA) current loops.

The 3-wire serial interface is SPI™/QSPI™ and
Microwire™ compatible. Each DAC has a double­buffered input organized as an input register followed
by a DAC register, which allows the input and DAC reg­isters to be updated independently or simultaneously.
Additional features include a programmable shutdown
(2µA), hardware-shutdown lockout, a separate voltage
reference for each DAC, power-on reset, and an active­low clear input (CL) that resets all registers and DACs to
zero. The MAX5156/MAX5157 provide a programmable
logic output pin for added functionality, and a serial­data output pin for daisy chaining.

________________________Applications

Industrial Process Control Motion Control
Digital Offset and Gain Digitally Programmable

Adjustment 4–20mA Current Loops
Remote Industrial Controls Automatic Test Equipment

____________________________Features

♦ 12-Bit Dual DAC with Configurable Output

Amplifier

♦ Single-Supply Operation: +5V (MAX5156)

+3V (MAX5157)

♦ Rail-to-Rail Output Swing
♦ Low Quiescent Current: 500µA (normal operation)

2µA (shutdown mode)

♦ Power-On Reset Clears DAC Outputs to Zero
♦ SPI/QSPI and Microwire Compatible
♦ Space-Saving 16-Pin QSOP Package

_______________Ordering Information

Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corp.

Ordering Information continued at end of data sheet.

Pin Configuration appears at end of data sheet.

REFACLDOUT

16-BIT

SHIFT

REGISTER

SR

CONTROL

INPUT
REG A

SCLK

UPO

REFB

DINCS

DAC A

DAC B

FBA

FBB

OUTA

OUTB

DAC

REG A

INPUT
REG B

LOGIC

OUTPUT

DECODE

CONTROL

DAC

REG B

MAX5156
MAX5157

V

DD

AGND

DGNDPDL

_________________________________________________________Functional Diagram

INL

(LSB)

PIN-PACKAGETEMP. RANGEPART

±116 QSOP0°C to +70°CMAX5156BCEE

±1/2

±1

±1/2

16 QSOP

16 Plastic DIP

16 Plastic DIP0°C to +70°C
0°C to +70°C
0°C to +70°CMAX5156ACEE

MAX5156BCPE

MAX5156ACPE

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS—MAX5156

(VDD= +5V ±10%, V

REFA

= V

REFB

= 2.5V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

T

A

= +25°C, output buffer connected in unity-gain configuration (Figure 9).)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto AGND............................................................-0.3V to +6V

V

DD

to DGND ...........................................................-0.3V to +6V

AGND to DGND..................................................................±0.3V

FBA, FBB to AGND.....................................-0.3V to (V

DD

+ 0.3V)

REF_, OUT_ to AGND.................................-0.3V to (V

DD

+ 0.3V)

Digital Inputs (SCLK, DIN, CS, CL, PDL)

to DGND................................................................-0.3V to +6V

Digital Outputs (DOUT, UPO) to DGND.....-0.3V to (V

DD

+ 0.3V)

Maximum Current into Any Pin.........................................±20mA

Continuous Power Dissipation (TA= +70°C)

Plastic DIP (derate 10.5mW/°C above +70°C) .............593mW

QSOP (derate 8.30mW/°C above +70°C).....................667mW

CERDIP (derate 10.00mW/°C above +70°C)................800mW

Operating Temperature Ranges

MAX5152_C_E/MAX5153_C_E ...........................0°C to +70°C

MAX5152_E_E/MAX5153_E_E..........................-40°C to +85°C

MAX5152_MJE/MAX5153_MJE......................-55°C to +125°C

Storage Temperature Range.............................-65°C to +160°C

Lead Temperature (soldering, 10sec).............................+300°C

VIN= 0V to V

DD

CL, PDL, CS, DIN, SCLK

CL, PDL, CS, DIN, SCLK

Input code = 1FFE hex,
V

REF

= 1Vp-p at 2.5VDC, f = 25kHz

Input code = 0000 hex,
V

REF

= (VDD- 1.4Vp-p) at 1kHz

4.5V ≤ VDD≤ 5.5V

Input code = 1FFE hex,
V

REF

= 0.67Vp-p at 2.5V

DC

Normalized to 2.5V

(Note 1)
Guaranteed monotonic

Code = 10

Minimum with code 1554 hex

Normalized to 2.5V

CONDITIONS

pF8C

IN

Input Capacitance

µA0.001 ±1I

IN

Input Leakage Current

mV200V

HYS

Input Hysteresis

V0.8V

IL

Input Low Voltage

V3V

IH

Input High Voltage

dB82SINAD

Signal-to-Noise plus
Distortion Ratio

dB-85Reference Feedthrough

kHz600Reference 3dB Bandwidth

kΩ14 20R

REF

Reference Input Resistance

V0 VDD- 1.4REFReference Input Range

±1/2

Bits12NResolution

µV/V20 200PSRRVDDPower-Supply Rejection Ratio

ppm/°C3Gain-Error Tempco

LSB-0.5 ±3Gain Error

LSB

±1

INLIntegral Nonlinearity

LSB±1DNLDifferential Nonlinearity

mV±6V

OS

Offset Error

ppm/°C3TCV

OS

Offset Tempco

UNITSMIN TYP MAXSYMBOLPARAMETER

MAX5156A
MAX5156B

STATIC PERFORMANCE

REFERENCE INPUT

MULTIPLYING-MODE PERFORMANCE

DIGITAL INPUTS

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs

with Configurable Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS—MAX5156 (continued)

(VDD= +5V ±10%, V

REFA

= V

REFB

= 2.5V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

T

A

= +25°C, output buffer connected in unity-gain configuration (Figure 9).)

Note 1: Accuracy is specified from code 10 to code 4095.
Note 2: Accuracy is better than 1LSB for V

OUT

greater than 6mV and less than VDD- 50mV. Guaranteed by PSRR test at the end points.

Note 3: Digital inputs are set to either V

DD

or DGND, code = 0000 hex, RL= ∞.

Note 4: SCLK minimum clock period includes rise and fall times.

CS = VDD, f

DIN

= 100kHz, V

SCLK

= 5Vp-p

I

SOURCE

= 2mA

Rail-to-rail (Note 2)

To 1/2LSB of full-scale, V

STEP

= 2.5V

I

SINK

= 2mA

CONDITIONS

nV-s5Digital Crosstalk

nV-s5Digital Feedthrough

µs25Time Required to Exit Shutdown

µA0 ±0.1I

FB

Current into FBA or FBB

VVDD- 0.5V

OH

Output High Voltage

V0 to V

DD

Output Voltage Swing

µs15Output Settling Time

V0.13 0.40V

OL

Output Low Voltage

V/µs0.75SRVoltage Output Slew Rate

UNITSMIN TYP MAXSYMBOLPARAMETER

(Note 4)

(Note 3)

(Note 3)

ns40t

CL

SCLK Pulse Width Low

ns40t

CH

SCLK Pulse Width High

ns100t

CP

SCLK Clock Period

µA0 ±1Reference Current in Shutdown

µA2 10I

DD(SHDN)

Power-Supply Current in
Shutdown

mA0.5 0.65I

DD

Power-Supply Current

V4.5 5.5V

DD

Positive Supply Voltage

ns40t

DS

DIN Setup Time

ns0t

CHS

SCLK Rise to CS Rise Hold Time

ns40t

CSS

CS Fall to SCLK Rise Setup Time

C

LOAD

= 200pF

C

LOAD

= 200pF

ns80t

DO2

SCLK Fall to DOUT Valid
Propagation Delay

ns80t

DO1

SCLK Rise to DOUT Valid
Propagation Delay

ns0t

DH

DIN Hold Time

ns100t

CSW

CS Pulse Width High

ns40t

CS1

CS Rise to SCLK Rise Hold

ns10t

CS0

SCLK Rise to CS Fall Delay

DIGITAL OUTPUTS (DOUT, UPO)

DYNAMIC PERFORMANCE

POWER SUPPLIES

TIMING CHARACTERISTICS

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS—MAX5157

(VDD= +2.7V to +3.6V, V

REFA

= V

REFB

= 1.25V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

A

= +25°C, output buffer connected in unity-gain configuration (Figure 9).)

VIN= 0V to V

DD

CL, PDL, CS, DIN, SCLK

CL, PDL, CS, DIN, SCLK

Input code = 1FFE hex,
V

REF

= 1Vp-p at 1.25VDC, f = 15kHz

Input code = 0000 hex,
V

REF

= (VDD- 1.4V) at 1kHz

2.7V ≤ VDD≤ 3.6V

Input code = 1FFE hex,
V

REF(AC)

= 0.67Vp-p at 1.25V

DC

Normalized to 1.25V

(Note 5)
Guaranteed monotonic

Code = 20

Minimum with code 1554 hex

Normalized to 1.25V

CONDITIONS

pF8C

IN

Input Capacitance

µA0 ±0.1I

IN

Input Leakage Current

mV200V

HYS

Input Hysteresis

V0.8V

IL

Input Low Voltage

V2.2V

IH

Input High Voltage

dB73SINAD

Signal-to-Noise plus Distortion
Ratio

dB-92Reference Feedthrough

kHz600Reference 3dB Bandwidth

kΩ14 20R

REF

Reference Input Resistance

V0 VDD- 1.4REFReference Input Range

±1

Bits12NResolution

µV/V20 320PSRRVDDPower-Supply Rejection Ratio

ppm/°C6Gain-Error Tempco

LSB-0.5 ±4Gain Error

LSB

±2

INLIntegral Nonlinearity

LSB±1DNLDifferential Nonlinearity

mV±6V

OS

Offset Error

ppm/°C6TCV

OS

Offset Tempco

UNITSMIN TYP MAXSYMBOLPARAMETER

MAX5157A
MAX5157B

I

SINK

= 2mA

I

SOURCE

= 2mA

V0.13 0.4V

OL

Output Low Voltage

VVDD- 0.5V

OH

Output High Voltage

V/µs0.75SRVoltage Output Slew Rate

Rail-to-rail (Note 6)

To 1/2LSB of full-scale, V

STEP

= 1.25V

V0 to V

DD

Output Voltage Swing

µs18Output Settling Time

µs25Time Required to Exit Shutdown

µA0 ±0.1I

FB

Current into FBA or FBB

CS = VDD, f

DIN

= 100kHz, V

SCLK

= 3Vp-p

nV-s5Digital Feedthrough
nV-s5Digital Crosstalk

STATIC PERFORMANCE

REFERENCE INPUT (V

REF

)

MULTIPLYING-MODE PERFORMANCE

DIGITAL INPUTS

DIGITAL OUTPUTS (DOUT, UPO)

DYNAMIC PERFORMANCE

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs

with Configurable Outputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS—MAX5157 (continued)

(VDD= +2.7V to +3.6V, V

REFA

= V

REFB

= 1.25V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

A

= +25°C, output buffer connected in unity-gain configuration (Figure 9).)

(Note 4)

(Note 7)

(Note 7)

ns40t

CL

SCLK Pulse Width Low

CONDITIONS

ns40t

CH

SCLK Pulse Width High

ns100t

CP

SCLK Clock Period

µA±1

Reference Current in
Shutdown

µA1 8I

DD(SHDN)

Power-Supply Current in
Shutdown

mA0.5 0.6I

DD

Power-Supply Current

V2.7 3.6V

DD

Positive Supply Voltage

ns50t

DS

DIN Setup Time

ns0t

CHS

SCLK Rise to CS Rise Hold
Time

ns40t

CSS

CS Fall to SCLK Rise Setup
Time

C

LOAD

= 200pF

C

LOAD

= 200pF

ns120

UNITSMIN TYP MAXSYMBOLPARAMETER

t

DO2

SCLK Fall to DOUT Valid
Propagation Delay

ns120t

DO1

SCLK Rise to DOUT Valid
Propagation Delay

ns0t

DH

DIN Hold Time

ns100t

CSW

CS Pulse Width High

ns40t

CS1

CS Rise to SCLK Rise Hold

ns10t

CS0

SCLK Rise to CS Fall Delay

Note 5: Accuracy is specified from code 20 to code 4095.
Note 6: Accuracy is better than 1LSB for V

OUT

greater than 6mV and less than VDD- 100mV. Guaranteed by PSRR test at the end

points.

Note 7: Digital inputs are set to either V

DD

or DGND, code = 0000 hex, RL= ∞.

POWER SUPPLIES

TIMING CHARACTERISTICS

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs

6 _______________________________________________________________________________________

__________________________________________Typical Operating Characteristics

(VDD= +5V, RL= 10kΩ, CL= 100pF, FB_ connected to OUT_, TA= +25°C, unless otherwise noted.)

-20

-16

-18

-12

-14

-8

-10

-6

-2

-4

0

0 600 1200 1800 2400 3000

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

MAX5156 TOC01

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

V

REF

= 0.67Vp-p @ 2.5V

DC

CODE = 1FFE (HEX)

0.40

0.50

0.45

0.55

0.60

-60 20 60-20 100 140

SUPPLY CURRENT

vs. TEMPERATURE

MAX5156 TOC02

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

CODE = 1FFE (HEX)

CODE = 0000 (HEX)

RL =

∞

-30

-90
0 10 100

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

-70

-50

-60

-80

-40

MAX5156 TOC03

FREQUENCY (kHz)

THD + NOISE (dB)

V

REF

= 1Vp-p @ 2.5V

DC

CODE = 1FFE (HEX)

0

-0.5

0.1 1 10 100 1000

FULL-SCALE ERROR vs. RESISTIVE LOAD

-0.4

MAX5156 TOC04

RL (kΩ)

FULL-SCALE ERROR (LSB)

-0.3

-0.2

-0.1

V

REF

= 2.5V

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0.5 1.5 2.0 2.51.0 3.0 3.5 4.0 5.04.5 5.5

OUTPUT FFT PLOT

MAX5156-TOC07

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

V

REF

= 3.6Vp-p @ 1.8V

DC

f = 1kHz
CODE = 1FFE (HEX)
NOTE: RELATIVE TO FULL SCALE

-150

-130

-140

-110

-120

-90

-100

-80

-60

-70

-50

0.5 1.5 2.0 2.51.0 3.0 3.5 4.0 5.04.5 5.5

REFERENCE FEEDTHROUGH AT 1kHz

MAX5156-TOC05

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

V

REF

= 3.6Vp-p @ 1.88V

DC

CODE = 0000 (HEX)

0

1.5

1.0

0.5

2.0

2.5

3.0

-55 255-35 -15 45 65 85 105 125

POWER-DOWN CURRENT

vs. TEMPERATURE

MAX5156 TOC06

TEMPERATURE (°C)

POWER-DOWN CURRENT (µA)

CS
5V/div
AC COUPLED

OUT_
500mV/div

DYNAMIC-RESPONSE RISE TIME

MAX5156 TOC08

2µs/div

CS
5V/div
AC COUPLED

OUT_
500mV/div

DYNAMIC-RESPONSE FALL TIME

MAX5156 TOC09

2µs/div

MAX5156

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs

with Configurable Outputs

_______________________________________________________________________________________

7

-20

-16

-18

-12

-14

-8

-10

-6

-2

-4

0

0 500 1000 1500 2000 2500

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

MAX5156 TOC10

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

V

REF

= 0.67Vp-p @ 1.25V

DC

CODE = 1FFE (HEX)

0.40

0.50

0.45

0.55

0.60

-60 20 60-20 100 140

SUPPLY CURRENT

vs. TEMPERATURE

MAX5156 TOC11

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

CODE = 1FFE (HEX)

CODE = 0000 (HEX)

RL =

∞

-30

-90
0 10 100

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

-70

-50

-60

-80

-40

MAX5156 TOC12

FREQUENCY (kHz)

THD + NOISE (dB)

V

REF

= 1Vp-p @ 1V

DC

CODE = 1FFE (HEX)

0

-0.6

0.1 1 10 100 1000

FULL-SCALE ERROR vs. RESISTIVE LOAD

-0.4

MAX5156 TOC13

RL (kΩ)

FULL-SCALE ERROR (LSB)

-0.5

-0.3

-0.2

-0.1

V

REF

= 1.25V

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0.5 1.5 2.0 2.51.0 3.0 3.5 4.0 5.04.5 5.5

OUTPUT FFT PLOT

MAX5156-TOC16

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

V

REF

= 1.6Vp-p @ 0.88V

DC

f = 1kHz
CODE = 1FFE (HEX)
NOTE: RELATIVE TO FULL SCALE

-150

-130

-140

-110

-120

-90

-100

-80

-60

-70

-50

0.5 1.5 2.0 2.51.0 3.0 3.5 4.0 5.04.5 5.5

REFERENCE FEEDTHROUGH AT 1kHz

MAX5156-TOC14

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

V

REF

= 1.6Vp-p @ 0.88V

DC

CODE = 0000 (HEX)

0

1.5

1.0

0.5

2.0

2.5

3.0

-55 255-35 -15 45 65 85 105 125

POWER-DOWN CURRENT

vs. TEMPERATURE

MAX5156 TOC15

TEMPERATURE (°C)

POWER-DOWN CURRENT (µA)

OUT_
500mV/div

DYNAMIC-RESPONSE RISE TIME

MAX5156 TOC17

2µs/div

CS
2V/div

OUT_
500mV/div

DYNAMIC-RESPONSE FALL TIME

MAX5156 TOC18

2µs/div

CS
2V/div

____________________________Typical Operating Characteristics (continued)

(VDD= +3V, RL= 10kΩ, CL= 100pF, FB_ connected to OUT_, TA= +25°C, unless otherwise noted.)

MAX5157

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs

8 _______________________________________________________________________________________

____________________________Typical Operating Characteristics (continued)

(VDD= +5V (MAX5156), VDD= +3V (MAX5157), RL= 10kΩ, CL= 100pF, FB_ connected to OUT_, TA= T

MIN

to T

MAX

, unless

otherwise noted.)

0.30

0.45

0.40

0.35

0.55

0.50

0.60

4.50 4.75 5.00 5.25 5.50

MAX5156

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX5156 TOC19

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

CODE = 1FFE (HEX)

CODE = 0000 (HEX)

0.30

0.45

0.40

0.35

0.55

0.50

2.7 3.0 3.3 3.6

MAX5157

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX5156 TOC19a

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

CODE = 1FFE (HEX)

CODE = 0000 (HEX)

CS
2V/div

OUT_
10mV/div
AC COUPLED

MAX5156

MAJOR-CARRY TRANSITION

MAX5156 TOC20

2µs/div

TRANSITION FROM 1000 (HEX) TO 0FFE (HEX)

OUTA
1V/div

OUTB
200µV/div
AC COUPLED

MAX5156

ANALOG CROSSTALK

MAX5156 TOC21

200µs/div

SCLK
5V/div

OUTA
500µV/div
AC COUPLED

MAX5156

DIGITAL FEEDTHROUGH

MAX5156 TOC22

1µs/div

MAX5156/MAX5157

_______________Detailed Description

The MAX5156/MAX5157 dual, 12-bit, voltage-output
DACs are easily configured with a 3-wire serial inter­face. These devices include a 16-bit data-in/data-out
shift register, and each DAC has a double-buffered
input comprised of an input register and a DAC register
(see

Functional Diagram

). Both DACs use an inverted
R-2R ladder network that produces a weighted voltage
proportional to the input voltage value. Each DAC has
its own reference input to facilitate independent full­scale values. Figure 1 depicts a simplified circuit dia­gram of one of the two DACs.

Reference Inputs

The reference inputs accept both AC and DC values
with a voltage range extending from 0V to (VDD- 1.4V).
Determine the output voltage using the following equa­tion:

V

OUT

= V

REF

x NB / 4096

where NB is the numeric value of the DAC’s binary input
code (0 to 4095) and V

REF

is the reference voltage.

The reference input impedance ranges from 14kΩ (1554
hex) to several giga ohms (with an input code of 0000
hex). This reference input capacitance is code depen­dent and typically ranges from 15pF with an input code
of all zeros to 50pF with a full-scale input code.

Output Amplifier

The output amplifier’s inverting input is available to the
user, allowing force and sense capability for remote
sensing and specific gain configurations. The inverting
input can be connected to the output to provide a unity­gain buffered output. The output amplifiers have a typi­cal slew rate of 0.75V/µs and settle to 1/2LSB within
15µs, with a load of 10kΩ in parallel to 100pF. Loads
less than 2kΩ degrade performance.

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs

with Configurable Outputs

_______________________________________________________________________________________ 9

______________________________________________________________Pin Description

PIN

Analog GroundAGND1

FUNCTIONNAME

DAC A Output VoltageOUTA2

Reference for DAC AREFA4

DAC A Output Amplifier Feedback Input. Inverting input of the output amplifier.FBA3

Chip-Select Input

CS

6

Serial Clock Input SCLK8

Serial Data InputDIN7

Active-Low Clear Input. Resets all registers to zero. DAC outputs go to 0V.

CL

5

Serial Data OutputDOUT10

Power-Down Lockout. The device cannot be powered down when PDL is low.PDL

12

User-Programmable OutputUPO11

DAC B Output Amplifier Feedback Input. Inverting input of the output amplifier.FBB14

Positive Power SupplyV

DD

16

DAC B Output VoltageOUTB15

Reference Input for DAC BREFB13

Digital GroundDGND9

Figure 1. Simplified DAC Circuit Diagram

2R

REF_

AGND

R R R

2R 2R 2R 2R

D0 D9 D10

D11

FB_

OUT_

SHOWN FOR ALL 1s ON DAC

MAX5156/MAX5157

Power-Down Mode

The MAX5156/MAX5157 feature a software-program­mable shutdown mode that reduces the typical supply
current to 2µA. The two DACs can be shut down inde­pendently or simultaneously by using the appropriate
programming word. For instance, enter shutdown mode
(for both DACs) by writing an input control word of
111XXXXXXXXXXXX0 (Table 1). In shutdown mode, the
reference inputs and amplifier outputs become high
impedance, and the serial interface remains active.
Data in the input registers is saved, allowing the
MAX5156/MAX5157 to recall the output state prior to
entering shutdown when returning to normal mode. Exit
shutdown by recalling the previous condition or by

updating the DAC with new information. When returning
to normal operation (exiting shutdown), wait 20µs for
output stabilization.

Serial Interface

The MAX5156/MAX5157 3-wire serial interface is com­patible with both Microwire (Figure 2) and SPI/QSPI
(Figure 3) serial-interface standards. The 16-bit serial
input word consists of an address bit, two control bits,
12 bits of data (MSB to LSB), and one sub bit as shown
in Figure 4. The address and control bits determine the
response of the MAX5156/MAX5157, as outlined in
Table 1.

Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs

10 ______________________________________________________________________________________

D11................D0

MSB LSB

FUNCTION

A0 C1 C0

0 0 1 12 bits of DAC data Load input register A; DAC register is unchanged.

0 1 1 12 bits of DAC data

Load all DAC registers from the shift register (start up both DACs
with new data).

1 1 0 12 bits of DAC data Load input register B; all DAC registers are updated.

0 1 0 12 bits of DAC data Load input register A; all DAC registers are updated.

1 0 1 12 bits of DAC data Load input register B; DAC register is unchanged.

0 0 0 1 1 0 x xxxxxxxx

Shut down DAC A when PDL = 1.

0 0 0 1 0 1 x xxxxxxxx

Update DAC register B from input register B (start up DAC B with
data previously stored in input register B).

0 0 0 0 0 1 x xxxxxxxx

Update DAC register A from input register A (start up DAC A with
data previously stored in input register A).

1 1 1 xxxxxxxxxxxx

Shut down both DACs if PDL = 1.

1 0 0 xxxxxxxxxxxx

Update both DAC registers from their respective input registers
(start up both DACs with data previously stored in the input
registers).

0 0 0 1 1 1 x xxxxxxxx

Shut down DAC B when PDL = 1.
0 0 0 0 1 0 x xxxxxxxx UPO goes low (default).
0 0 0 0 1 1 x xxxxxxxx UPO goes high.
0 0 0 1 0 0 1 xxxxxxxx Mode 1, DOUT clocked out on SCLK’s rising edge.
0 0 0 1 0 0 0 xxxxxxxx Mode 0, DOUT clocked out on SCLK’s falling edge (default).
0 0 0 0 0 0 x xxxxxxxx No operation (NOP).

Table 1. Serial-Interface Programming Commands

“x” = don’t care

Note: D11, D10, D9, and D8 become control bits when A0, C1, and C0 = 0. S0 is a sub bit, always zero.

S0

0

0

0

0

0

0

0

0

0

0

0
0
0
0
0
0

16-BIT SERIAL WORD

The MAX5156/MAX5157’s digital inputs are double
buffered, which allows any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow the DACs to act
independently.

Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, Microwire), with CS low during this
period. The address and control bits determine which
register will be updated, and the state of the registers
when exiting shutdown. The 3-bit address/control
determines the following:

• registers to be updated

• clock edge on which data is clocked out via the seri-

al data output (DOUT)

• state of the user-programmable logic output

• configuration of the device after shutdown

The general timing diagram in Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers
depending on the address and control bits. The maxi­mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia­gram of the serial interface.

Serial Data Output (DOUT)

DOUT is the internal shift register’s output. It allows for
daisy-chaining and data readback. The MAX5156/
MAX5157 can be programmed to shift data out of
DOUT on SCLK’s falling edge (Mode 0) or rising edge
(Mode 1). Mode 0 provides a lag of 16 clock cycles,
which maintains compatibility with SPI/QSPI and
Microwire interfaces. In Mode 1, the output data lags

15.5 clock cycles. On power-up, the device defaults to
Mode 0.

User-Programmable Logic Output (UPO)

UPO allows an external device to be controlled through
the MAX5156/MAX5157 serial interface (Table 1), there­by reducing the number of microcontroller I/O pins
required. On power-up, UPO is low.

Power-Down Lockout Input (PDL)

PDL disables software shutdown when low. When in
shutdown, transitioning PDL from high to low wakes up
the part with the output set to the state prior to shut­down. PDL can also be used to asynchronously wake
up the device.

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs

with Configurable Outputs

______________________________________________________________________________________ 11

SCLK

DIN

CS

SK

SO

I/O

MAX5156
MAX5157

MICROWIRE

PORT

Figure 2. Connections for Microwire

DIN

SCLK

CS

MOSI

SCK

I/O

SPI/QSPI

PORT

SS

V

CC

CPOL = 0, CPHA = 0

MAX5156
MAX5157

Figure 3. Connections for SPI/QSPI

Figure 4. Serial-Data Format

1 Address/2 Control Bits

A0

0

Address Bits

C1, C0

Control Bits

S0

12 Data Bits

D11.......................D0

MSB...DataBits...LSB

Sub

Bit

16 Bits of Serial Data

MSB...................................................................................LSB

MAX5156/MAX5157

Daisy Chaining Devices

Any number of MAX5156/MAX5157s can be daisy
chained by connecting the DOUT pin of one device to the
DIN pin of the following device in the chain (Figure 7).

Since the MAX5156/MAX5157’s DOUT has an internal
active pull-up, the DOUT sink/source capability deter­mines the time required to discharge/charge a capaci-

tive load. Refer to the digital output V

OH

and VOLspeci-

fications in the

Electrical Characteristics

.

Figure 8 shows an alternative method of connecting
several MAX5156/MAX5157s. In this configuration, the
data bus is common to all devices; data is not shifted
through a daisy-chain. More I/O lines are required in
this configuration because a dedicated chip-select
input (CS) is required for each IC.

Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs

12 ______________________________________________________________________________________

CS

SCLK

DIN

COMMAND

EXECUTED

9

8

16

1

C1

A0 S0

C0

D11

D10

D9

D8 D5 D4 D3 D2 D1 D0D7 D6

Figure 5. Serial-Interface Timing Diagram

SCLK

DIN

t

CSO

t

CSS

t

CL

t

CH

t

CP

t

CSW

t

CS1

t

CSH

t

DS

t

DH

CS

Figure 6. Detailed Serial-Interface Timing Diagram

TO OTHER
SERIAL DEVICES

MAX5156
MAX5157

DIN

SCLK

CS

MAX5156
MAX5157

MAX5156
MAX5157

DINDOUT DOUT DOUT

SCLK

CS

DIN

SCLK

CS

Figure 7. Daisy Chaining MAX5156/MAX5157s

__________Applications Information

Unipolar Output

Figure 9 depicts the MAX5156/MAX5157 configured for
unity-gain, unipolar operation. Table 2 lists the unipolar
output codes. To increase dynamic range, specific
gain configurations can be used as shown in Figure 10.

Bipolar Output

The MAX5156/MAX5157 can be configured for a bipo­lar output, as shown in Figure 11. The output voltage is
given by the equation:

V

OUT

= V

REF

[((2 x NB) / 4096) - 1]

where NB represents the numeric value of the DAC’s
binary input code. Table 3 shows digital codes and the
corresponding output voltage for Figure 11’s circuit.

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs

with Configurable Outputs

______________________________________________________________________________________ 13

TO OTHER
SERIAL DEVICES

MAX5156
MAX5157

DIN

SCLK

CS

MAX5156
MAX5157

DIN

SCLK

CS

MAX5156
MAX5157

DIN

SCLK

CS

DIN

SCLK

CS1
CS2

CS3

Figure 8. Multiple MAX5156/MAX5157s Sharing a Common DIN Line

MAX5156
MAX5157

DAC

REF_

OUT_

FB_

DGND

AGND

+5V/+3V

V

DD

Figure 9. Unipolar Output Circuit

Table 2. Unipolar Code Table (Gain = +1)

0000 0000 0001(0)

0V0000 0000 0000(0)

0111 1111 1111(0)

1000 0000 0000(0)

DAC CONTENTS

MSB LSB

1000 0000 0001(0)

1111 1111 1111(0)

ANALOG OUTPUT

Note: ( ) are for the sub bit.



REF

REF

REF

REF



2048



4096



4095



4096





2049



4096





2047



4096






4096








1

+V

+V

+V

REF

+V

+V











=










V

REF

2

MAX5156/MAX5157

Using an AC Reference

In applications where the reference has an AC signal
component, the MAX5156/MAX5157 have multiplying
capabilities within the reference input voltage range
specifications. Figure 12 shows a technique for apply­ing a sinusoidal input REF_, where the AC signal is off­set before being applied to the reference input.

Harmonic Distortion and Noise

The total harmonic distortion plus noise (THD+N) is typ­ically less than -80dB at full scale with a 1Vp-p input
swing at 5kHz. The typical -3dB frequency is 600kHz
for both devices, as shown in the

Typical Operating

Characteristics

.

Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs

14 ______________________________________________________________________________________

MAX5156
MAX5157

DAC

V

OUT

=

(

1

+ R1

) (

N

)(

V

REF_

)

R2 4096

REF_

V

OUT

FB_

OUT_

AGNDDGND

+5V/+3V

V

DD

R1

R2

Figure 10. Configurable Output Gain

AGNDDGND

MAX5156
MAX5157

DAC _

REF_

OUT_

FB_

10k 10k

V-

V+

VDD

V

OUT

+5V/+3V

Figure 11. Bipolar Output Circuit

DAC_

OUT_

FB_

MAX5156
MAX5157

10k

26k

REF_

V

DD

DGND AGND

+5V/

+3V

AC

REFERENCE

INPUT

500mVp-p

MAX495

+5V/+3V

Figure 12. AC Reference Input Circuit

Table 3. Bipolar Code Table

0000 0000 0001(0)

0000 0000 0000(0)

0111 1111 1111(0)

0V1000 0000 0000(0)

DAC CONTENTS

MSB LSB

1000 0000 0001(0)

1111 1111 1111(0)

ANALOG OUTPUT

Note: ( ) are for the sub bit.

-V





2047

+V



















2048

1

2048

1

2048

2047
2048






=



















- V

REF

+V

REF

-V

REF

-V

REF



2048



REF REF

2098



Digital Calibration and

Threshold Selection

Figure 13 shows the MAX5156/MAX5157 in a digital
calibration application. With a bright value applied to
the photodiode (on), the DAC is digitally ramped up
until it trips the comparator. The microprocessor stores
this high calibration value. Repeat the process with a
dim light (off) to obtain the dark current calibration. The
microprocessor then programs the DAC to set an out­put voltage that is the midpoint of the two calibration
values. Applications include tachometers, motion sens­ing, automatic readers, and liquid clarity analysis.

Digital Control of Gain and Offset

The two DACs can be used to control the offset and
gain for curve-fitting nonlinear functions, such as trans­ducer linearization or analog compression/expansion
applications. The input signal is used as the reference
for the gain-adjust DAC, whose output is summed with
the output from the offset-adjust DAC. The relative
weight of each DAC output is adjusted by R1, R2, R3,
and R4 (Figure 14).

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs

with Configurable Outputs

______________________________________________________________________________________ 15

AGND

DIN

µP

DGND

MAX5156
MAX5157

DAC _

REF_

OUT_

R

FB_

V+

V-

PHOTODIODE

V+

VDD

V

OUT

+5V/+3V

Figure 13. Digital Calibration

AGNDDGND

REFA

CONTROL/

SHIFT REGISTER

REFB

MAX5156
MAX5157

DACA

+5V/+3V

V

DD

V

IN

CS

DIN

SCLK

CL

V

REF

R1

R3

R4

R2

OUT_B

FBB

FBA

OUT_A

V

OUT

DACB

=

NA

4096

NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA.
NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.

R2

R1+R2R4R3

NB

4096

R4
R3

(

V

IN

)(

)(

1+

)

(

V

REF

)(

)

V

OUT

= [GAIN

] - [

OFFSET

]

[ ] [ ]

Figure 14. Digital Control of Gain and Offset

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Digitally Programmable Current Source

Figure 15 depicts a digitally programmable, unidirec­tional current source that can be used in industrial con­trol applications. The output current is:

I

OUT

= (V

REF

/ R) (NB / 4096)

where NB is the DAC code and R is the sense resistor.

Power-Supply Considerations

On power-up, the input and DAC registers clear (resets
to zero code). For rated performance, V

REF_

should be
at least 1.4V below VDD. Bypass the power supply with
a 4.7µF capacitor in parallel with a 0.1µF capacitor to
GND. Minimize lead lengths to reduce lead inductance.

Grounding and Layout Considerations

Digital and AC transient signals on AGND can create
noise at the output. Connect AGND to the highest quali­ty ground available. Use proper grounding techniques,
such as a multilayer board with a low-inductance
ground plane. Carefully lay out the traces between
channels to reduce AC cross-coupling and crosstalk.
Wire-wrapped boards and sockets are not recommend­ed. If noise becomes an issue, shielding may be
required.

MAX5156
MAX5157

DAC_

REF_

2N3904

R

V

L

I

OUT

AGND

FB_

OUT_

+5V/+3V

V

DD

DGND

Figure 15. Digitally Programmable Current Source

___________________Chip Information

TRANSISTOR COUNT: 3053
SUBSTRATE CONNECTED TO AGND

__________________Pin Configuration _Ordering Information (continued)

16
15
14
13
12
11
10

9

1
2

3
4
5

6

7
8

AGND V

DD

OUTB
FBB
REFB
PDL
UPO
DOUT
DGND

TOP VIEW

MAX5156
MAX5157

DIP/QSOP

OUTA

FBA

CS

REFA

CL

DIN

SCLK

*

Contact factory for availability.

INL

(LSB)

PIN-PACKAGETEMP. RANGEPART

±1

±1

±1/2

±1

±1/2

±2

±2

16 CERDIP*-55°C to +125°CMAX5156BMJE

16 QSOP-40°C to +85°CMAX5156BEEE

16 QSOP-40°C to +85°CMAX5156AEEE

16 Plastic DIP-40°C to +85°CMAX5156BEPE

16 Plastic DIP-40°C to +85°CMAX5156AEPE

±1

±2

±1

±2

±1

16 QSOP0°C to +70°CMAX5157BCEE

±216 Plastic DIP0°C to +70°CMAX5157BCPE
±116 QSOP0°C to +70°CMAX5157ACEE

16 CERDIP*-55°C to +125°CMAX5157BMJE

16 QSOP-40°C to +85°CMAX5157BEEE

16 QSOP-40°C to +85°CMAX5157AEEE

16 Plastic DIP-40°C to +85°CMAX5157BEPE

16 Plastic DIP-40°C to +85°CMAX5157AEPE

16 Plastic DIP0°C to +70°C

MAX5157ACPE