General Description
The MAX5138/MAX5139 are a family of single-channel
pin-compatible and software-compatible 16-bit and 12bit DACs. The MAX5138/MAX5139 are low-power, 16bit/12-bit, buffered voltage-output, high-linearity DACs.
They use a precision internal reference or a precision
external reference for rail-to-rail operation. The
MAX5138/MAX5139 accept a wide +2.7V to +5.25V supply-voltage range to accommodate most low-power and
low-voltage applications. These devices accept a 3-wire
SPI
TM
-/QSPITM-/MICROWIRETM-/DSP-compatible serial
interface to save board space and reduce the complexity of optically isolated and transformer-isolated applications. The digital interface’s double-buffered hardware
and software LDAC provide simultaneous output update.
The serial interface features a READY output for easy
daisy-chaining of several MAX5138/MAX5139 devices
and/or other compatible devices. The MAX5138/MAX5139
include a hardware input to reset the DAC outputs to
zero or midscale upon power-up or reset, providing
additional safety for applications that drive valves or
other transducers that need to be off during power-up.
The high linearity of the DACs makes these devices ideal
for precision control and instrumentation applications.
The MAX5138/MAX5139 are available in an ultra-small
(3mm x 3mm), 16-pin TQFN package and are specified
over the -40°C to +105°C extended industrial temperature range.
Applications
Automatic Test Equipment
Automatic Tuning
Communication Systems
Data Acquisition
Gain and Offset Adjustment
Portable Instrumentation
Power-Amplifier Control
Process Control and Servo Loops
Programmable Voltage and Current Sources
Features
o 16-/12-Bit Resolution in a 3mm x 3mm, 16-Pin
TQFN Package
o Hardware-Selectable on Power-Up or Reset-to-
Zero/Midscale DAC Output
o Double-Buffered Input Registers
o LDAC Asynchronously Updates DAC Output
o READY Facilitates Daisy Chaining
o High-Performance 10ppm/°C Internal Reference
o Guaranteed Monotonic Over All Operating
Conditions
o Wide +2.7V to +5.25V Supply Range
o Rail-to-Rail Buffered Output Operation
o Low Gain Error (Less Than ±0.5% FS) and Offset
(Less Than ±10mV)
o 30MHz 3-Wire SPI-/QSPI-/MICROWIRE-/
DSP-Compatible Serial Interface
o CMOS-Compatible Inputs with Hysteresis
o Low Power Consumption (I
SHDN
= 2µA max)
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
________________________________________________________________
Maxim Integrated Products
1
Pin Configuration
19-4428; Rev 1; 4/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Functional Diagram and Typical Operating Circuit appear
at end of data sheet.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
Note: All devices are specified over the -40°C to +105°C operating
temperature range.
PART PIN-PACKAGE
RESOLUTION
(BITS)
MAX5138BGTE+ 16 TQFN-EP* 16
MAX5139GTE+ 16 TQFN-EP* 12
TOP VIEW
AVDD
REFI
REFO
AGND
*EXPOSED PAD
OUT
12 10 9
13
14
15
16
+
13
N.C.
3mm x 3mm
11
MAX5138
MAX5139
2
M/Z DVDD
TQFN
READY
*EP
LDAC
N.C.
AGND
8
DIN
7
CS
6
SCLK
5
4
N.C.
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
AVDD
= 2.7V to 5.25V, V
DVDD
= 2.7V to 5.25V, V
AVDD
≥ V
DVDD
, V
A
GND
= 0, V
REFI
= V
AVDD
- 0.25V, C
OUT
= 200pF, R
OUT
= 10kΩ,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND ........................................................-0.3V to +6V
DVDD to AGND ........................................................-0.3V to +6V
OUT to AGND...............................................-0.3V to the lower of
(AVDD + 0.3V) and +6V
REFI, REFO, M/Z to AGND...........................-0.3V to the lower of
(AVDD + 0.3V) and +6V
SCLK, DIN, CS to AGND..............................-0.3V to the lower of
(DVDD + 0.3V) and +6V
LDAC, READY to AGND...............................-0.3V to the lower of
(DVDD + 0.3V) and +6V
Continuous Power Dissipation (T
A
= +70°C)
16-Pin TQFN (derate at 14.7mW/°C above +70°C) ..1176.5mW
Maximum Current into Any Input or Output
with the Exception of M/Z Pin .......................................±50mA
Maximum Current into M/Z Pin ...........................................±5mA
Operating Temperature Range .........................-40°C to +105°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
STATIC ACCURACY (Notes 1, 2)
Resolution N
MAX5138 Integral Nonlinearity INL
MAX5139 Integral Nonlinearity INL V
Differential Nonlinearity DNL Guaranteed monotonic -1.0 +1.0 LSB
Offset Error OE (Note 4) -10 ±1 +10 mV
Offset-Error Drift ±4 µV/°C
Gain Error GE (Note 4) -0.5 ±0.2 +0.5 % of FS
Gain Temperature Coefficient ±2
REFERENCE INPUT
Reference-Input Voltage Range V
Reference Input Impedance 113 kΩ
INTERNAL REFERENCE
Reference Voltage V
Refer ence Tem p er atur e C oeffi ci ent (Note 5) 10 25 ppm/°C
Reference Output Impedance 1 Ω
Line Regulation 100 ppm/V
Maximum Capacitive Load C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFI
REFO
R
MAX5138 16
MAX5139 12
V
= 5V,
REFI
AVDD = 5.25V
= 5V, AVDD = 5.25V -1 ±0.25 +1 LSB
REFI
AVDD = 3V to 5.25V 2 AVDD
AVDD = 2.7V to 3V 2
T
+25°C 2.437 2.440 2.443 V
A =
( N ote 3) -9 ±2 +11
= +25°C ±6
T
A
AVDD -
0.1 nF
0.2
Bits
LSB
ppm
FS/°C
V
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 2.7V to 5.25V, V
DVDD
= 2.7V to 5.25V, V
AVDD
≥ V
DVDD
, V
A
GND
= 0, V
REFI
= V
AVDD
- 0.25V, C
OUT
= 200pF, R
OUT
= 10kΩ,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
DAC OUTPUT VOLTAGE (Note 2)
Output Voltage Range No load 0.02
DC Output Impedance 0.1 Ω
Maximum Capacitive Load
(Note 5)
Resistive Load R
Short-Circuit Current I
Power-Up Time From power-down mode 25 µs
DIGITAL INPUTS (SCLK, DIN, CS, LDAC) (Note 6)
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
Input Capacitance C
DIGITAL OUTPUTS (READY)
Output High Voltage V
Output Low Voltage V
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate SR Positive and negative 1.25 V/µs
Voltage-Output Settling Time t
Digital Feedthrough Code 0, all digital inputs from 0 to DVDD 0.5 nV•s
Major Code Transition Analog
Glitch Impulse
Output Noise 10kHz 120 nV/√Hz
Integrated Output Noise 1Hz to 10kHz 18 µV
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
C
SC
IN
OH
OL
Series resistance = 0Ω 0.2 nF
L
Series resistance = 500Ω 15 µF
L
AVDD = 5.25V ±35
AVDD = 2.7V -40 ±20 +40
IH
IL
VIN = 0 or DVDD -1 ±0.1 +1 µA
IN
I
SOURCE
I
= 2mA 0.4 V
SINK
1/4 scale to 3/4 scale V
S
settle to ±2 LSB (Note 5)
= 3mA
= AVDD = 5V
REFI
2kΩ
0.7 x
DVDD
DVDD
- 0.5
5µs
25 nV•s
AVDD
- 0.02
0.3 x
DVDD
10 pF
V
mA
V
V
V
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 2.7V to 5.25V, V
DVDD
= 2.7V to 5.25V, V
AVDD
≥ V
DVDD
, V
A
GND
= 0, V
REFI
= V
AVDD
- 0.25V, C
OUT
= 200pF, R
OUT
= 10kΩ,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Note 1: Static accuracy tested without load.
Note 2: Linearity is tested within 20mV of AGND and AVDD
,
allowing for gain and offset error.
Note 3: Codes above 2047 are guaranteed to be within ±9 LSB
.
Note 4: Gain and offset tested within 100mV of AGND and AVDD
.
Note 5: Guaranteed by design.
Note 6: Device draws current in excess of the specified supply current when a digital input is driven with a voltage of VI < DVDD - 0.6V
or VI > 0.5V. At VI = 2.2V with DVDD = 5.25V, this current can be as high as 2mA. The SPI inputs are CMOS-input-level compatible. The 30MHz clock frequency cannot be guaranteed for a minimum signal swing.
Note 7: Excess current from AVDD is 10mA when powered without DVDD. Excess current from DVDD is 1mA when powered without
AVDD.
Note 8: All timing specifications are with respect to the digital input and output thresholds.
Note 9: Maximum daisy-chain clock frequency is limited to 25MHz.
C7
C6
C5 D2
D1
D0
X
COMMAND EXECUTED ON
24th FALLING EDGE OF SCLK
CS
SCLK
DIN
X = DON'T CARE.
t
CH
t
CL
t
CSS
t
DH
t
CSH
t
DS
t
SRL
READY
X
t
CSW
D3
Figure 1. Serial-Interface Timing Diagram
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS (Note 7)
Analog Supply Voltage Range AVDD 2.7 5.25 V
Digital Supply Voltage Range DVDD 2.7 AVDD V
Supply Current
Power-Down Supply Current
I
AVDD
I
DVDD
I
AVPD
I
DVPD
No load, all digital inputs at 0 or DVDD
No load, all digital inputs at 0 or DVDD
1 1.6 mA
110µA
0.2 2
0.1 2
TIMING CHARACTERISTICS (Note 8) (Figure 1)
Serial-Clock Frequency f
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall-to-SCLK Fall Setup Time t
SCLK Fall-to CS-Rise Hold Time t
DIN-to-SCLK Fall Setup Time t
DIN-to-SCLK Fall Hold Time t
SCLK Fall to READY Transition t
CS Pulse-Width High t
LDAC Pulse Width t
LDACPWL
SCLK
CH
CL
CSS
CSH
DS
DH
SRL
CSW
(Note 9) 30 ns
0 30 MHz
13 ns
13 ns
8ns
5ns
10 ns
2ns
33 ns
33 ns
µA
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX5138 INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
9
6
3
0
INL (LSB)
-3
-6
-9
0 65,536
DIGITAL INPUT CODE (LSB)
49,15232,76816,384
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
0 65,536
DIGITAL INPUT CODE (LSB)
49,5232,76816,384
MAX5138 toc01
MAX5138 toc04
9
7
5
3
1
-1
INL (LSB)
-3
-5
-7
-9
2.7 3.2
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
2.7
INTEGRAL NONLINEARITY
vs. ANALOG SUPPLY VOLTAGE
4.73.7 4.2 5.2
SUPPLY VOLTAGE (V)
DIFFERENTIAL NONLINEARITY
vs. ANALOG SUPPLY VOLTAGE
4.73.2 3.7 4.2 5.2
SUPPLY VOLTAGE (V)
MAX5138 toc02
MAX5138 toc05
9
7
5
3
1
-1
INL (LSB)
-3
-5
-7
-9
-40
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
-40
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX5138 toc03
1008040 60020-20
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
MAX5138 toc06
1008040 60020-20
TEMPERATURE (°C)
vs. ANALOG SUPPLY VOLTAGE
10
8
6
4
2
0
-2
OFFSET ERROR (mV)
-4
-6
-8
-10
2.7
OFFSET ERROR
SUPPLY VOLTAGE (V)
4.73.2 3.7 4.2 5.2
MAX5138 toc07
12-BIT DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
0.10
0.08
0.06
0.04
0.02
0
DNL (LSB)
-0.02
-0.04
-0.06
-0.08
-0.10
04096
DIGITAL INPUT CODE (LSB)
307220481024
MAX5138 toc08
INL (LSB)
12-BIT INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
0 4096
DIGITAL INPUT CODE (LSB)
307220481024
MAX5138 toc09
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
OFFSET ERROR
vs. TEMPERATURE
0.8
0.6
0.4
0.2
0
-0.2
-0.4
OFFSET ERROR (mV)
-0.6
-0.8
-1.0
-40
V
V
AVDD
REF
V
AVDD
= 5V
V
REF
= 2.7V
= 2.5V
TEMPERATURE (°C)
= 5.25V
MAX5138 toc10
GAIN ERROR (%FS)
1008040 60020-20
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
1.00
V
= 2.7V
DVDD
0.98
0.96
V
= V
0.94
0.92
0.90
0.88
0.86
ANALOG SUPPLY CURRENT (mA)
0.84
0.82
0.80
2.7 5.2
ANALOG SUPPLY VOLTAGE (V)
OUT
V
OUT
REFO
= 0
4.74.23.73.2
MAX5138 toc13
ANALOG SUPPLY CURRENT (mA)
GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
2.7
SUPPLY VOLTAGE (V)
4.7 5.23.73.2 4.2
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40 100
I
AVDD
I
DVDD
TEMPERATURE (°C)
GAIN ERROR
vs. TEMPERATURE
0.036
0.032
MAX5138 toc11
0.028
0.024
0.020
GAIN ERROR (%FS)
0.016
0.012
0.008
-40
V
= 5.25V
AVDD
= 5V
V
REF
TEMPERATURE (°C)
V
V
AVDD
REF
= 2.7V
= 2.5V
MAX5138 toc12
100806040200-20
ANALOG SUPPLY CURRENT vs. SUPPLY
VOLTAGE (POWER-DOWN MODE)
0.8
MAX5138 toc14
806020 400-20
0.7
0.6
TA = -40°C
0.5
0.4
0.3
0.2
ANALOG SUPPLY CURRENT (μA)
0.1
0
2.7 5.2
TA = +105°C
TA = +25°C
SUPPLY VOLTAGE (V)
MAX5138 toc15
4.74.23.2 3.7
EXITING/ENTERING
POWER-DOWN MODE
V
OUT
4μs/div
MAX5138 toc16
500mV/div
MAJOR CODE TRANSITION
1μs/div
MAX5138 toc17
20mV/div
SETTLING TIME UP
MAX5138 toc18
500mV/div
400ns/div
MAX5138/MAX5139
SETTLING TIME DOWN
MAX5138 toc19
400ns/div
500mV/div
DIGITAL FEEDTHROUGH
MAX5138 toc20
40ns/div
V
OUT
SCLK
5V/div
50mV/div
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
_______________________________________________________________________________________ 7
)
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
0.50
V
= 5.25V
AVDD
0.45
0.40
0.35
0.30
0.25
0.20
0.15
DIGITAL SUPPLY CURRENT (μA)
0.10
0.05
= 1MHz
f
SCLK
0
2.7 5.2
DIGITAL SUPPLY VOLTAGE (V)
4.74.23.73.2
MAX5138 toc21
REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
2.4390
2.4385
2.4380
2.4375
(V)
2.4370
REFO
2.4365
V
2.4360
2.4355
2.4350
2.4345
2.7 5.2
TA = +25°C
TA = +105°C
TA = -40°C
SUPPLY VOLTAGE (V)
2.4385
2.4380
MAX5138 toc22
2.4375
2.4370
(V)
2.4365
REFO
V
2.4360
2.4355
2.4350
4.74.23.73.2
2.4345
-40 100
REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
MAX5138 toc23
8060-20 0 20 40
DIGITAL SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE
2500
V
= V
AVDD
2000
1500
1000
DIGITAL SUPPLY CURRENT (μA)
500
0
06
= 5.25V
DVDD
DIGITAL INPUT VOLTAGE (V
UP
DOWN
4123 5
2.51
2.50
MAX5138 toc24
2.49
2.48
2.47
2.46
OUTPUT VOLTAGE (V)
2.45
2.44
2.43
-40 100
FULL-SCALE OUTPUT
vs. TEMPERATURE
EXTERNAL REF = 2.5V
INTERNAL REF
TEMPERATURE (°C)
OUTPUT VOLTAGE
vs. SUPPLY CURRENT
2.45
V
= 5V
MAX5138 toc25
2.44
V
= 3.3V
2.43
2.42
OUTPUT VOLTAGE (V)
2.41
2.40
8060-20 0 20 40
AVDD
030
OUTPUT CURRENT (mA)
AVDD
2010
MAX5138 toc26
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
FULL-SCALE REFERENCE FEEDTHROUGH
V
OUT
V
REF
20μs/div
REFERENCE INPUT RESPONSE
0
-5
-10
-15
-20
ATTENUATION (dB)
-25
vs. FREQUENCY
MAX5138 toc29
V
MAX5138 toc27
500mV/div
500mV/div
0 V
OUT
0 V
REF
POWER-UP GLITCH, ZERO-SCALE,
EXTERNAL REFERENCE
AVDD
ZERO-SCALE REFERENCE FEEDTHROUGH
V
REF
V
OUT
20μs/div
POWER-UP GLITCH, ZERO-SCALE,
MAX5138 toc30
2V/div
V
AVDD
INTERNAL REFERENCE
MAX5138 toc28
500mV/div
20mV/div
MAX5138 toc31
2V/div
-30
-35
1 10,000
INPUT FREQUENCY (kHz)
100010010
POWER-UP GLITCH, MIDSCALE,
EXTERNAL REFERENCE
V
AVDD
V
OUT
4μs/div
MAX5138 toc32
2V/div
1V/div
V
V
OUT
POWER-UP GLITCH, MIDSCALE,
INTERNAL REFERENCE
AVDD
V
OUT
4μs/div
MAX5138 toc33
4μs/div
1V/div
2V/div
1V/div
V
OUT
DC NOISE SPECTRUM, FFT PLOT
BUFFERED OUTPUT
RESOLUTION BANDWIDTH = 1Hz
50Ω LOAD
4μs/div
2.5kHz/div
MAX5138 toc34
1V/div
-40dBm
10dB/div
25kHz/div
Detailed Description
The MAX5138/MAX5139 are a family of single-channel,
pin-compatible and software-compatible, 16-bit and 12bit DACs. The parts are low-power, buffered voltageoutput, high-linearity DACs. The MAX5138/MAX5139
minimize the digital noise feedthrough from input to output by powering down the SCLK and DIN input buffers
after completion of each 24-bit serial input. On powerup, the MAX5138/MAX5139 reset the DAC output to zero
or midscale, depending on the state of the M/Z input,
providing additional safety for applications that drive
valves or other transducers that need to be off on powerup. The MAX5138/MAX5139 contain a segmented resistor string-type DAC, a serial-in parallel-out shift register,
a DAC register, power-on reset (POR) circuit, and control logic. On the falling edge of the clock (SCLK) pulse,
the serial input (DIN) data is shifted into the device, MSB
first. During power-down, an internal 80kΩ resistor pulls
DAC outputs to AGND.
Output Amplifier (OUT)
The MAX5138/MAX5139 include an internal buffer for the
DAC output. The internal buffer provides improved load
regulation and transition glitch suppression for the DAC
output. The output buffer slews at 1.25V/µs and drives up
to 2kΩ in parallel with 200pF. The analog supply voltage
(AVDD) determines the maximum output voltage range
of the device as AVDD powers the output buffer.
DAC Reference
Internal Reference
The MAX5138/MAX5139 feature an internal reference
with a nominal +2.44V output. Connect REFO to REFI
when using the internal reference. Bypass REFO to
AGND with a 47pF (maximum 100pF) capacitor.
Alternatively, if heavier decoupling is required, add a
1kΩ resistor in series with a 1µF capacitor in parallel
with the existing 100pF capacitor. REFO can deliver up
to 100µA of current with no degradation in performance. Configure other reference voltages by applying
a resistive potential divider with a total resistance
greater than 33kΩ from REFO to AGND.
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1, 4, 9 N.C. No Connection. Not internally connected.
2M/Z
3 LDAC Load DAC. Active-low hardware load DAC input.
5 SCLK Serial-Clock Input
6 CS Active-Low Chip-Select Input
7 DIN Data In
8 AGND Analog Ground. Internally connected to AGND. Connect AGND to AGND externally.
10 READY Data Output
11 DVDD Digital Power Supply. Bypass DVDD with a 0.1µF capacitor to AGND.
12 OUT Buffered DAC Output
13 AVDD Analog Power Supply. Bypass AVDD with a 0.1µF capacitor to AGND.
14 REFI Reference Voltage Input. Bypass REFI with a 0.1µF capacitor to AGND.
15 REFO Reference Voltage Output
16 AGND DAC Ground. Internally connected to AGND. Connect AGND to AGND externally.
—EP
Power-Up Reset Select. Connect M/Z low to AGND to power up the DAC output. Connect M/Z
high to power up the DAC output to midscale.
Exposed Pad. Not internally connected. Connect to a ground or leave unconnected. Not intended
as an electrical connection point.
MAX5138/MAX5139
External Reference
The external reference input features a typical input
impedance of 113kΩ and accepts an input voltage
from +2V to AVDD. Connect an external voltage
supply between REFI and AGND to apply an external reference. Leave REFO unconnected. Visit
www.maxim-ic.com/products/references for a list of
available external voltage-reference devices.
AVDD as Reference
Connect AVDD to REFI to use AVDD as the reference
voltage. Leave REFO unconnected.
Serial Interface
The MAX5138/MAX5139 3-wire serial interface is compatible with MICROWIRE, SPI, QSPI, and DSPs (Figures
2, 3). The interface provides three inputs, SCLK, CS,
and DIN and one output, READY. Use READY to verify
communication or to daisy-chain multiple devices (see
the
READY
section). READY is capable of driving a
20pF load with a 30ns (max) delay from the falling edge
of SCLK. The chip-select input (CS) frames the serial
data loading at DIN. Following a chip-select input’s
high-to-low transition, the data is shifted synchronously
and latched into the input register on each falling edge
of the serial-clock input (SCLK). Each serial word is 24
bits. The first 8 bits are the control word followed by 16
data bits (MSB first), as shown in Table 1. The serial
input register transfers its contents to the input registers
after loading 24 bits of data. To initiate a new data
transfer, drive CS high and keep CS high for a minimum
of 33ns before the next write sequence. The SCLK can
be either high or low between CS write pulses. Figure 1
shows the timing diagram for the complete 3-wire serialinterface transmission.
The MAX5138/MAX5139 digital input is double buffered.
Depending on the command issued through the serial
interface, the input register can be loaded without affecting the DAC register using the write command. To update
the DAC register, either pulse the LDAC input low, or use
the software LDAC command. Use the writethrough commands (see Table 1) to update the DAC output immediately after the data is received. Only use the writethrough
command to update the DAC output immediately.
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
10 ______________________________________________________________________________________
Table 1. Operating Mode Truth Table
*
For the MAX5139, D3–D0 are X = don’t-care bits.
24-BIT WORD
CONTROL BITS DATA BITS
MSB LSB
C7 C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6–D0
0 0 0 0 0 0 0 0 X X X X X X X X X X NOP No operation.
0 0 0 0 0 0 0 1 X X X X X X X DAC X X LDAC
0 0 0 0 0 0 1 0 X X X X X X X X X X CLR Software clear.
0 0 0 0 0 0 1 1 X X X X X X X DAC READY_EN X
0 0 0 0 0 1 0 1 0 0 0 0 0 0 LIN 0 0 0 Linearity Optimize DAC linearity.
0 0 0 1 X X X DAC D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 Write
0 0 1 1 X X X DAC D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
0 0 1 0 0 0 0 0 X X X X X X X X X X NOP No operation.
DESC FUNCTION
Set DAC = 1 to move
contents of input to DAC
register.
Set DAC = 1 to power
Power
Control
Write-
through
down DAC. Set
READY_EN = 1 to
enable READY.
Write to selected input
registers (DAC output
not affected).
Write to selected input
and DAC register,
DAC output updated
(writethrough).
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
______________________________________________________________________________________ 11
Figure 2. Connections for MICROWIRE
The MAX5138’s DAC code is unipolar binary with V
OUT
= (code/65536) x V
REF
. See Table 1 for the serial inter-
face commands.
The MAX5139’s DAC code is unipolar with V
OUT
=
(code/4096) x V
REF
. See Table 1 for the serial interface
commands.
Connect the MAX5138/MAX5139 DVDD supply to the
supply of the host DSP or microprocessor. The AVDD
supply may be set to any voltage within the 2.7V to
5.25V operating range, but must be greater than or
equal to the DVDD supply.
Writing to the MAX5138/MAX5139
Write to the MAX5138/MAX5139 using the following
sequence:
1) Drive CS low, enabling the shift register.
2) Clock 24 bits of data into DIN (C7 first and D0 last),
observing the specified setup and hold times. Bits
D15–D0 are the data bits that are written to the
internal register.
3) After clocking in the last data bit, drive CS high. CS
must remain high for 33ns before the next transmission is started.
Figure 1 shows a write operation for the transmission of
24 bits. If CS is driven high at any point prior to receiving
24 bits, the transmission is discarded.
READY
Connect READY to a microcontroller (µC) input to monitor the serial interface for valid communications. The
READY pulse appears 24 clock cycles after the negative edge of CS (Figure 4). Since the MAX5138/
MAX5139 look at the first 24 bits of the transmission following the falling edge of CS, it is possible to daisy
chain devices with different command word lengths.
READY goes high 16ns after CS is driven high.
READY*
DIN
SCLK
CS
SCK
SS
I/O
MOSI
+5V
MISO*
SPI/QSPI
PORT
*THE READY-TO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX5138/MAX5139 BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
MAX5138
MAX5139
Figure 3. Connections for SPI/QSPI
CS
DIN
SCLK
READY 1
READY 3
READY 2
12324222120432 1 23 2422215432 1 23 2422215432
SLAVE 1 DATA SLAVE 2 DATA SLAVE 3 DATA
Figure 4. READY Timing
SCLK
SK
MAX5138
MAX5139
*THE READY-TO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
*MAX5138/MAX5139 BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
DIN
READY*
CS
SO
MICROWIRE
PORT
SI*
I/O
MAX5138/MAX5139
Daisy chain multiple MAX5138/MAX5139 devices by
connecting the first device conventionally, then connect
its READY output to the CS of the following device.
Repeat for any other devices in the chain, and drive the
SCLK and DIN lines in parallel (Figure 5). When sending
commands to daisy-chained MAX5138/MAX5139s, the
devices are accessed serially starting with the first
device in the chain. The first 24 data bits are read by the
first device, the second 24 data bits are read by the second device and so on (Figure 4). Figure 6 shows the
configuration when CS is not driven by the µC. These
devices can be daisy chained with other compatible
devices, such as the MAX5510 and the MAX5511.
To perform a daisy-chain write operation, drive CS low
and output the data serially to DIN. The propagation of
the READY signal then controls how the data is read by
each device. As the data propagates through the daisy
chain, each individual command in the chain is executed on the 24th falling clock edge following the falling
edge of the respective CS input. To update just one
device in a daisy chain, send the no-op command to
the other devices in the chain.
If READY is not required, write command 0x03 (power
control) and set READY_EN = 0 (see Table 1) to disable the READY output.
Clear Command
The MAX5138/MAX5139 feature a software clear command (0x02). The software clear command acts as a
software POR, erasing the contents of all registers. The
output returns to the state determined by the M/Z input.
Power-Down Mode
The MAX5138/MAX5139 feature a software-controlled
power-down mode. The internal reference and biasing
circuits power down to conserve power when powered
down. In power-down, the output disconnects from the
buffer and is grounded with an internal 80kΩ resistor.
The DAC register holds the retained code so that the
output is restored when powered up. The serial interface remains active in power-down mode.
Load DAC (
LDAC
) Input
The MAX5138/MAX5139 feature an active-low LDAC
logic input that updates the output. Keep LDAC high
during normal operation (when the device is controlled
only through the serial interface). Drive LDAC low to
update the DAC output with data from the input register.
Figure 7 shows the LDAC timing with respect to OUT.
Holding LDAC low causes the input register to become
transparent and data written to the DAC register to
immediately update the DAC output. A software command can also activate the LDAC operation. To activate
LDAC by software, set control word 0x01 to load the
DAC, and all other data bits to don’t care. See Table 1
for the data format. This operation updates the DAC output if it is flagged with a 1. If the DAC output is flagged
with a 0 it remains unchanged.
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
12 ______________________________________________________________________________________
Figure 5. Daisy-Chain Configuration
μC
MOSI
SCK
SLAVE 1
DIN
SCLK
I/O
READY
CS
DIN
SCLK
CS
SLAVE 2
READY
DIN
SCLK
CS
SLAVE 3
READY
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
______________________________________________________________________________________ 13
μC
Figure 6. Daisy Chain (CS Not Used)
LDAC
OUT
±2 LSB
t
S
t
LDACPWL
Figure 7. Output Timing
CSm
CS1
SCLK
DWRITE
DREAD
INT
TO OTHER CHIPS/CHAINS
SLAVE 1
CS
CS
SCLK
DIN
READY
CS
SCLK
DIN
MAX5138
MAX5139
SLAVE 2
MAX5138
MAX5139
READY
CS
SCLK
DIN
DOUT
ERROR
READY
SLAVE N
MAX5138
MAX5139
MAX5138/MAX5139
Applications Information
Power-On Reset (POR)
On power-up, the input register is set to zero, and the
DAC output powers up to zero or midscale, depending
on the configuration of M/Z. Connect M/Z to AGND to
power the output to AGND. Connect M/Z to AVDD to
power the output to midscale.
To guarantee DAC linearity, wait until the supplies have
settled. Set the LIN bit in the DAC linearity register; wait
10ms, and clear the LIN bit.
Unipolar Output
The MAX5138/MAX5139 unipolar output voltage range is
0 to V
REFI
. The output buffer drives a 2kΩ load in parallel
with 200pF.
Bipolar Output
Use the MAX5138/MAX5139 in bipolar applications with
additional external components (see the
Typical
Operating Circuit
).
Power Supplies and
Bypassing Considerations
For best performance, use a separate supply for the
MAX5138/MAX5139. Bypass both DVDD and AVDD
with high-quality ceramic capacitors to a low-impedance ground as close as possible to the device.
Minimize lead lengths to reduce lead inductance.
Connect both MAX5138/MAX5139 AGND inputs to the
analog ground plane.
Layout Considerations
Digital and AC transient signals on AGND inputs can
create noise at the outputs. Connect both AGND inputs
to form the star ground for the DAC system. Refer
remote DAC loads to this system ground for the best
possible performance. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return
paths back to the MAX5138/MAX5139 AGND. Do not
use wire-wrapped boards and sockets. Use shielding
to improve noise immunity. Do not run analog and digital signals parallel to one another (especially clock signals) and avoid routing digital lines underneath the
MAX5138/MAX5139 package.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a best fit straight line drawn between two codes.
This best fit line for the MAX5138 is a line drawn
between codes 3072 and 64,512 of the transfer function and the best fit line for the MAX5139 is a line drawn
between codes 192 and 4032 of the transfer function,
once offset and gain errors have been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height
and the ideal value of 1 LSB. If the magnitude of the
DNL is greater than -1 LSB, the DAC guarantees no
missing codes and is monotonic.
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
14 ______________________________________________________________________________________
Table 2. MAX5138 Input Code vs. Output
Voltage
Table 3. MAX5139 Input Code vs. Output
Voltage
DAC LATCH CONTENTS
MSB LSB
1111 1111 1111 1111 V
1000 0000 0000 0000 V
0000 0000 0000 0001 V
0000 0000 0000 0000 0
ANALOG OUTPUT, V
x (65,535/65,536)
REF
x (32,768/65,536) = 1/2 V
REF
x (1/65,536)
REF
OUT
REF
DAC LATCH CONTENTS
MSB LSB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
XXX
XXX
XXX
XXX
ANALOG OUTPUT, V
V
x (4095/4096)
REF
V
x (2048/4096)
REF
V
x (1/4096)
REF
0
OUT
Offset Error
Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point.
Typically, the point at which the offset error is specified is
at or near the zero-scale point of the transfer function.
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines
are toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB
changes from high to low and all other bits change from
low to high. The duration of the magnitude of the
switching glitch during a major carry transition is
referred to as the digital-to-analog glitch impulse.
Digital-to-Analog Power-Up Glitch Impulse
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
Chip Information
PROCESS: BiCMOS
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
______________________________________________________________________________________ 15
Functional Diagram
M/Z
SCLK
DIN
AVDD DVDD
MAX5138
MAX5139
CS
SERIAL-TO-
PARALLEL
CONVERTER
READY
POR
CONTROL LOGIC
INPUT
REGISTER
POWER-DOWN
CONTROL
DAC
REGISTER
LDAC
AGND
REFI
12-/16-BIT
DAC
AGND
REFO
REFERENCE
INTERNAL
BIAS CKT
BUFFER
OUT
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
16 ______________________________________________________________________________________
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
16 TQFN-EP T1633-5
21-0136
DAC
CS
SCLK
DIN
R1
R2
DVDD AVDD
OUT
REFO
AGND
100nF
M/Z
LDAC
DIGITAL POWER
SUPPLY
ANALOG POWER
SUPPLY
100nF
READY
REFI
47pF
100nF
*SHOWN IN BIPOLAR CONFIGURATION
MAX5138
MAX5139
Typical Operating Circuit
MAX5138/MAX5139
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
17
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
0 3/09 Initial release —
1 4/09 Removed future product reference for MAX5139 1
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
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