Rainbow Electronics MAX5104 User Manual

General Description

The MAX5104 low-power, serial, voltage-output, dual
12-bit digital-to-analog converter (DAC) consumes only
500µA from a single +5V supply. This device features
Rail-to-Rail®output swing and is available in a space­saving 16-pin QSOP package. To maximize the dynamic
range, the DAC output amplifiers are configured with an
internal gain of +2V/V.

The 3-wire serial interface is SPI™/QSPI™/MICROWIRE™
compatible. Each DAC has a double-buffered input
organized as an input register followed by a DAC register,
which allows the input and DAC registers to be updated
independently or simultaneously with a 16-bit serial
word. Additional features include programmable power­down (2µA), hardware power-down lockout (PDL), a
separate reference voltage input for each DAC that
accepts AC and DC signals, and an active-low clear
input (CL) that resets all registers and DACs to zero.
These devices provide a programmable logic pin for
added functionality, and a serial-data output pin for
daisy chaining.

________________________Applications

Industrial Process Control
Remote Industrial Controls
Digital Offset and Gain Adjustment
Microprocessor-Controlled Systems
Motion Control
Automatic Test Equipment (ATE)

____________________________Features

♦ 12-Bit Dual DAC with Internal Gain of +2V/V
♦ Rail-to-Rail Output Swing
♦ 12µs Settling Time
♦ +5V Single-Supply Operation
♦ Low Quiescent Current

500µA (normal operation)
2µA (power-down mode)

♦ SPI/QSPI/MICROWIRE Compatible
♦ Space-Saving 16-Pin QSOP Package
♦ Power-On Reset Clears Registers and DACs to Zero
♦ Adjustable Output Offset

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC

with Serial Interface

________________________________________________________________

Maxim Integrated Products

1

19-1587; Rev 0; 11/99

Ordering Information

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone].
For small orders, phone [phone].

Functional Diagram

Pin Configuration appears at end of data sheet.

PIN-

PACKAGE

TEMP. RANGEPART

16 QSOP

16 QSOP0°C to +70°C

-40°C to +85°CMAX5104EEE

MAX5104CEE

INL

(LSB)

±4

±4

DOUT

REGISTER

CONTROL

16-BIT
SHIFT

SR

DECODE

CONTROL

LOGIC

OUTPUT

DGNDPDLCL

INPUT
REG A

INPUT
REG B

AGND

DAC

REG A

DAC

REG B

V

DD

REFA

DAC A

MAX5104

DAC B

R

R

R

R

OSA

OUTA
OSB

OUTB

UPOH REFB

SCLK

DINCS

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= +5V ±10%, V

REFA

= V

REFB

= +2.048V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

A

= +25°C (OS_ connected to AGND for a gain of +2V/V).)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto AGND............................................................-0.3V to +6V

V

DD

to DGND ...........................................................-0.3V to +6V

AGND to DGND..................................................................±0.3V

OSA, OSB to AGND.......................(V

AGND

- 4V) to (VDD+ 0.3V)

REF_, OUT_ to AGND.................................-0.3V to (V

DD

+ 0.3V)

Digital Inputs (SCLK, DIN, CS,

CL, PDL) to DGND...........................................(-0.3V to +6V)

Digital Outputs (DOUT, UPO) to DGND.....-0.3V to (V

DD

+ 0.3V)

Maximum Current into Any Pin.........................................±20mA

Continuous Power Dissipation (TA= +70°C)

16-Pin QSOP (derate 8.30mW/°C above +70°C).......667mW

Operating Temperature Ranges

MAX5104CEE ...................................................0°C to +70°C

MAX5104EEE.................................................-40C° to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

REFERENCE INPUT

DIGITAL INPUTS

Input Hysteresis V

HYS

200 mV

Input Capacitance C

IN

8 pF

Input Leakage Current I

IN

0.001 ±1 µAVIN= 0 to V

DD

Input Low Voltage V

IL

0.8 V

CL, PDL, CS, DIN, SCLK

Signal-to-Noise plus
Distortion Ratio

SINAD 75 dB

Input code = 1FFE hex,
V

REF_

= 1Vp-p at 1.25VDC, f = 25kHz

PARAMETER

SYMBOL MIN TYP MAX

UNITS

CONDITIONS

Gain Error -0.2 ±8 LSB

Offset Tempco TCV

OS

4 ppm/°C

Offset Error V

OS

±10 mV

Differential Nonlinearity DNL ±1 LSB

Gain-Error Tempco 4 ppm/°C

20 600 µV/V

VDDPower-Supply
Rejection Ratio

PSRR

Integral Nonlinearity

Resolution

12

Bits

INL ±4 LSB

Reference Input Resistance

R

REF

14 20

kΩ

Reference 3dB Bandwidth

300

kHz

Reference Feedthrough

-82 dB

Normalized to 2.048V

Code = 10

Guaranteed monotonic

Normalized to 2.048V

Minimum with code 1554 hex

4.5V ≤ VDD≤ 5.5V

Input code = 1FFE hex,
V

REF_

= 0.67Vp-p at 2.5V

DC

Input code = 0000 hex,
V

REF_

= (VDD- 1.4Vp-p), f = 1kHz

(Note 1)

STATIC PERFORMANCE

Reference Input Range

0V

DD

- 1.4

V

REF

MULTIPLYING-MODE PERFORMANCE

Input High Voltage

V

IH

3 V

CL, PDL, CS, DIN, SCLK

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC

with Serial Interface

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±10%, V

REFA

= V

REFB

= +2.048V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

A

= +25°C (OS_ connected to AGND for a gain of +2V/V).)

Note 1: Accuracy is specified from code 6 to code 4095.
Note 2: Accuracy is better than 1LSB for V

OUT_

greater than 6mV and less than VDD- 50mV. Guaranteed by PSRR test at the

end points.

Note 3: Digital inputs are set to either V

DD

or DGND, code = 0000 hex, RL= ∞.

Note 4: SCLK minimum clock period includes the rise and fall times.

CS = VDD, SCLK = 100kHz, V

SCLK

= 5Vp-p

I

SOURCE

= 2mA

(Note 4)

(Note 3)

(Note 3)

ns

Rail-to-rail (Note 2)

To 1/2LSB of full-scale, V

STEP

= 4V

40

I

SINK

= 2mA

t

CL

SCLK Pulse Width Low

CONDITIONS

ns40t

CH

SCLK Pulse Width High

nVs5Digital Crosstalk

nVs5Digital Feedthrough

µs25Time Required to Exit Shutdown

kΩ24 34R

OS_

OSA or OSB Input Resistance

ns100t

CP

SCLK Clock Period

µA0±1Reference Current in Shutdown

µA210I

DD(SHDN)

Power-Supply Current
in Shutdown

mA0.5 0.65I

DD

Power-Supply Current

V4.5 5.5V

DD

Positive Supply Voltage

ns40t

DS

SDI Setup Time

ns

VVDD- 0.5V

OH

Output High Voltage

0t

CSH

SCLK Rise to CS Rise
Hold Time

ns40t

CSS

CS Fall to SCLK Rise
Setup Time

C

LOAD

= 200pF

V0 to V

DD

Output Voltage Swing

µs15Output Settling Time

C

LOAD

= 200pF

ns80

V0.13 0.40V

OL

Output Low Voltage

V/µs0.75SRVoltage Output Slew Rate

UNITSMIN TYP MAXSYMBOLPARAMETER

t

DO2

SCLK Fall to DOUT
Valid Propagation Delay

ns80t

DO1

SCLK Rise to DOUT
Valid Propagation Delay

ns0t

DH

SDI Hold Time

ns100t

CSW

CS Pulse Width High

ns40t

CS1

CS Rise to SCLK Rise Hold

ns10t

CS0

SCLK Rise to CS Fall Delay

DIGITAL OUTPUTS (DOUT, UPO)

DYNAMIC PERFORMANCE

POWER SUPPLIES

TIMING CHARACTERISTICS

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface

4 _______________________________________________________________________________________

__________________________________________Typical Operating Characteristics

(VDD= +5V, RL= 10kΩ, CL= 100pF, OS_ pins connected to AGND, TA= +25°C, unless otherwise noted.)

-20

-16

-18

-12

-14

-8

-10

-6

-2

-4

0

1 370 740 1110 1480 1850

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

MAX5104 toc01

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

V

REF

= +0.67Vp-p AT 2.5V

DC

CODE = 1FFE (HEX)

400

450

550

500

650

600

700

-55 5-15-35 4525 65 10585 125

SUPPLY CURRENT vs. TEMPERATURE

MAX5104 toc02

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

V

REF

= +2.048V

R

L

= ∞

CODE = 1FFE (HEX)

CODE = 0000 (HEX)

-30

-80
1 10 100

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

-70

MAX5104 toc03

FREQUENCY (kHz)

THD + N (dB)

-60

-50

-40

V

REF

= +1Vp-p AT 2.5V

DC

CODE = 1FFE (HEX)

0

0.1 1 10 100

FULL-SCALE ERROR vs. RESISTIVE LOAD

-1.25

-1.00

-1.50

-0.75

-0.50

-0.25

0.25

0.50

MAX5104 toc04

RL (kΩ)

FULL-SCALE ERROR (LSB)

V

REF

= +2.048V

-100

-80

-90

-60

-70

-40

-50

0.5 1.6 2.7 3.8 4.9 6.0

-30

-10

-20

0

OUTPUT FFT PLOT

MAX5104 toc07

V

REF

= +2.45Vp-p AT 1.225V

DC

f = 1kHz
CODE = 1FFE (HEX)

NOTE: RELATIVE TO FULL SCALE

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

-150

-130

-140

-110

-120

-90

-100

-80

-60

-70

-50

0.5 1.5 2.0 2.51.0 3.0 3.5 4.0 5.04.5 5.5

REFERENCE FEEDTHROUGH AT 1kHz

MAX5104 toc05

FREQUENCY (kHz)

RELATIVE OUTPUT (dB)

V

REF

= +3.6Vp-p AT 1.88V

DC

CODE = 0000 (HEX)

0

1

2

3

4

5

6

-55 5 25-15-35 45 65 85 105 125

SHUTDOWN CURRENT

vs. TEMPERATURE

MAX5104 toc06

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

V

REF

= +1V

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC

with Serial Interface

_______________________________________________________________________________________ 5

_____________________________Typical Operating Characteristics (continued)

(VDD= +5V, RL= 10kΩ, CL= 100pF, OS_ pins connected to AGND, TA= +25°C, unless otherwise noted.)

0.40

0.45

0.50

0.55

0.60

4.50 4.75 5.00 5.25 5.50

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX51504 toc10

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

CODE = 1FFE (HEX)

CODE = OOOO (HEX)

OUTB
200µV/div
AC-COUPLED

OUTA
5V/div

ANALOG CROSSTALK

MAX5104 toc12

V

REF

= +2.048V, GAIN = +2V/V, CODE = 1FFE HEX

250µs/div

DIGITAL FEEDTHROUGH

MAX5104 toc13

OUTA
500µV/div
AC-COUPLED

SCLK
5V/div

2.5µs/div

5µs/div

MAJOR-CARRY TRANSITION

MAX5104 toc11

TRANSITION FROM 1000 (HEX) TO 0FFE (HEX)

OUT_
50mV/div
AC-COUPLED

2V/div

CS

DYNAMIC RESPONSE RISE TIME

MAX5104 toc08

2µs/div

OUT_
1V/div

5V/div

CS

V

REF

= +2.048V

2µs/div

DYNAMIC RESPONSE FALL TIME

MAX5104 toc09

OUT_
1V/div

5V/div

CS

V

REF

= +2.048V

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface

6 _______________________________________________________________________________________

_______________Detailed Description

The MAX5104 dual, 12-bit, voltage-output DAC is easily
configured with a 3-wire serial interface. The device
includes a 16-bit data-in/data-out shift register, and
each DAC has a double-buffered input composed of an
input register and a DAC register (see

Functional

Diagram

). In addition, trimmed internal resistors produce
an internal gain of +2V/V that maximizes output voltage
swing. The amplifier’s offset-adjust pin allows for a DC
shift in the DAC’s output.

Both DACs use an inverted R-2R ladder network that
produces a weighted voltage proportional to the input
voltage value. Each DAC has its own reference input to
facilitate independent full-scale values. Figure 1 depicts
a simplified circuit diagram of one of the two DACs.

Reference Inputs

The reference inputs accept both AC and DC values
with a voltage range extending from 0 to (VDD- 1.4V).

Determine the output voltage using the following equa­tion (OS_ = AGND):

V

OUT

= (V

REF

· NB / 4096) · 2

where NB is the numeric value of the DAC’s binary input
code (0 to 4095) and V

REF

is the reference voltage.

The reference input impedance ranges from 14kΩ (1554
hex) to several gigohms (with an input code of 0000
hex). The reference input capacitance is code depen­dent and typically ranges from 15pF with an input code
of all zeros to 50pF with a full-scale input code.

Output Amplifier

The MAX5104’s output amplifiers have internal resistors
that provide for a gain of +2V/V when OS_ is connected
to AGND. These resistors are trimmed to minimize gain
error. The output amplifiers have a typical slew rate of

0.75V/µs and settle to 1/2LSB within 15µs, with a load
of 10kΩ in parallel with 100pF. Loads less than 2kΩ
degrade performance.

The OS_ pin can be used to produce an adjustable off­set voltage at the output. For instance, to achieve a 1V
offset, apply -1V to the OS_ pin to produce an output
range from 1V to (1V + V

REF

· 2). Note that the DAC’s
output range is still limited by the maximum output voltage
specification.

Power-Down Mode

The MAX5104 features a software-programmable shut­down mode that reduces the typical supply current to
2µA. The two DACs can be powered down indepen­dently, or simultaneously using the appropriate pro­gramming command. Enter power-down mode by
writing the appropriate input-control word (Table 1). In
power-down mode, the reference inputs and amplifier
outputs become high impedance, and the serial inter­face remains active. Data in the input registers is saved,

Digital GroundDGND9
Serial-Data OutputDOUT10
User-Programmable OutputUPO11
Power-Down Lockout. The device can-

not be powered down when PDL is low.

PDL

12

Reference for DAC BREFB13

Active-Low Clear Input. Resets all reg­isters to zero. DAC outputs go to 0V.

CL

5

Chip-Select Input

CS

6

Serial-Data Input DIN7
Serial-Clock Input SCLK8

Reference for DAC A REFA4

DAC A Offset AdjustmentOSA3

PIN

DAC A Output Voltage OUTA2

Analog Ground AGND1

FUNCTIONNAME

14 OSB DAC B Offset Adjustment
15 OUTB DAC B Output Voltage
16 V

DD

Positive Power Supply

OUT_

OS_

R

R

D0 D10 D11

D12

2R

2R 2R 2R 2R

RRR

REF_

AGND

Figure 1. Simplified DAC Circuit Diagram

_____________________Pin Description

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC

with Serial Interface

_______________________________________________________________________________________ 7

allowing the MAX5104 to recall the output state prior to
entering power-down when returning to normal mode.
Exit power-down by recalling the previous condition or
by updating the DAC with new information. When
returning to normal operation (exiting power-down),
wait 20µs for output stabilization.

Serial Interface

The MAX5104’s 3-wire serial interface is compatible
with both MICROWIRE (Figure 2) and SPI/QSPI (Figure 3)
serial-interface standards. The 16-bit serial input word
consists of 1 address bit, 2 control bits, 12 bits of data
(MSB to LSB), and 1 sub-bit as shown in Figure 4. The
address and control bits determine the MAX5104’s
response, as outlined in Table 1.

FUNCTION

A0 C1 C0

D11.......................D0

(MSB) (LSB)

0 0 1 12-bit DAC data Load input register A; DAC registers are unchanged.

0 1 1 12-bit DAC data

Load all DAC registers from the shift register
(start up both DACs with new data).

1 1 0 12-bit DAC data Load input register B; all DAC registers are updated.

0 1 0 12-bit DAC data Load input register A; all DAC registers are updated.

1 0 1 12-bit DAC data Load input register B; DAC registers are unchanged.

0 0 0 1 1 0 X XXXXXXXX

Power Down DAC A (provided PDL = 1).

0 0 0 1 0 1 X XXXXXXXX

Update DAC register B from input register B
(start up DAC B with data previously stored in input register B).

0 0 0 0 0 1 X XXXXXXXX

Update DAC register A from input register A
(start up DAC A with data previously stored in input register A).

1 1 1 XXXXXXXXXXXX

Shut down both DACs (provided PDL = 1).

1 0 0 XXXXXXXXXXXX

Update both DAC registers from their respective input registers
(start up both DACs with data previously stored in the input registers).

0 0 0 1 1 1 X XXXXXXXX

Power Down DAC B (provided PDL = 1).
0 0 0 0 1 0 X XXXXXXXX UPO goes low (default).
0 0 0 0 1 1 X XXXXXXXX UPO goes high.
0 0 0 1 0 0 1 XXXXXXXX Mode 1, DOUT clocked out on SCLK’s rising edge.
0 0 0 1 0 0 0 XXXXXXXX Mode 0, DOUT clocked out on SCLK’s falling edge (default).
0 0 0 0 0 0 X XXXXXXXX No operation (NOP).

Table 1. Serial-Interface Programming Commands

X = Don’t care
Note: D11, D10, D9, and D8 become control bits when A0, C1, and C0 = 0. S0 is a sub-bit, always zero.

Figure 2. Connections for MICROWIRE

16-BIT SERIAL WORD

S0

0

0

0

0

0

0

0

0

0

0

0
0
0
0
0
0

MAX5104

SCLK

DIN

CS

SK

MICROWIRE

PORT

SO

I/O

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface

8 _______________________________________________________________________________________

The MAX5104’s digital inputs are double buffered,
which allows any of the following: loading the input reg­ister(s) without updating the DAC register(s), updating
the DAC register(s) from the input register(s), or updating
the input and DAC registers concurrently. The address
and control bits allow the DACs to act independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, MICROWIRE), with CS low during
this period. The address and control bits determine
which register will be updated, and the state of the reg­isters when exiting power-down. The 3-bit address/con­trol determines the following:

• Registers to be updated

• Clock edge on which data is to be clocked out via the
serial-data output (DOUT)

• State of the user-programmable logic output

• Configuration of the device after power-down

The general timing diagram of Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data; otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the address and control bits. The maximum
clock frequency guaranteed for proper operation is
10MHz. Figure 6 shows a more detailed timing diagram
of the serial interface.

+5V

Figure 3. Connections for SPI/QSPI

Figure 5. Serial-Interface Timing Diagram

Figure 4. Serial-Data Format

1 Address/2 Control Bits

A0

Address Bits

C1, C0

Control Bits

12 Data Bits

D11.......................D0

MSB...Data Bits...LSB

0

S0

Sub

Bit

16 Bits of Serial Data

MSB...................................................................................LSB

SS

DIN

MAX5104

SCLK

CS

CS

SCLK

1

MOSI

SPI/QSPI

PORT

SCK

I/O

CPOL = 0, CPHA = 0

8

9

16

COMMAND

EXECUTED

C1

DIN

A0 S0

C0

D11

D10

D9

D8 D5 D4 D3 D2 D1 D0D7 D6

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC

with Serial Interface

_______________________________________________________________________________________ 9

t

Figure 6. Detailed Serial-Interface Timing Diagram

Figure 7. Daisy Chaining MAX5104s

Figure 8. Multiple MAX5104s Sharing a Common DIN Line

CS

t

CSS

t

SCLK

DIN

CSO

t

DS

t

DH

t

CH

t

CL

t

CP

t

CSH

CSW

t

CS1

SCLK

DIN

SCLK

CS1
CS2

CS3

MAX5104

DIN

CS

CS

SCLK

MAX5104

SCLK

SCLK

MAX5104 MAX5104

DINDOUT DOUT DOUT

CS

CS

MAX5104

SCLK

DIN

CS

CS

MAX5104

SCLK

TO OTHER
SERIAL DEVICES

TO OTHER
SERIAL DEVICES

DIN

DIN

DIN

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface

10 ______________________________________________________________________________________

Serial-Data Output

The serial-data output, DOUT, is the internal shift register’s
output. DOUT allows for daisy chaining of devices and
data readback. The MAX5104 can be programmed to
shift data out of DOUT on SCLK’s falling edge (Mode 0)
or on the rising edge (Mode 1). Mode 0 provides a lag
of 16 clock cycles, which maintains compatibility with
SPI/QSPI and MICROWIRE interfaces. In Mode 1, the
output data lags 15.5 clock cycles. On power-up, the
device defaults to Mode 0.

User-Programmable Logic Output

User-programmable logic output (UPO) allows an external
device to be controlled through the serial interface
(Table 1), thereby reducing the number of microcontroller
I/O pins required. On power-up, UPO is low.

Power-Down Lockout Input

The power-down lockout (PDL) pin disables software
shutdown when low. When in power-down, transitioning
PDL from high to low wakes up the part with the output
set to the state prior to power-down. PDL can also be
used to asynchronously wake up the device.

Daisy-Chaining Devices

Any number of MAX5104s can be daisy-chained by
connecting the DOUT pin of one device to the DIN pin
of the following device in the chain (Figure 7).

Since the MAX5104’s DOUT pin has an internal active
pull-up, the DOUT sink/source capability determines the
time required to discharge/charge a capacitive load.
See the digital output VOHand VOLspecifications i n the

Electrical Characteristics

.

Figure 8 shows an alternate method of connecting several
MAX5104s. In this configuration, the data bus is common
to all devices; data is not shifted through a daisy chain.
More I/O lines are required in this configuration because
a dedicated chip-select input (CS) is required for each IC.

__________Applications Information

Unipolar Output

Figure 9 shows the MAX5104 configured for unipolar,
rail-to-rail operation with a gain of +2V/V. The MAX5104
can produce a 0 to 4.096V output with a 2.048V reference
(Figure 9). Table 2 lists the unipolar output codes. An
offset to the output can be achieved by connecting a
voltage to OS_, as shown in Figure 10. By applying
V

OS_

= -1V, the output values will range between 1V

and (1V + V

REF

· 2).

Bipolar Output

The MAX5104 can be configured for a bipolar output
(Figure 11). The output voltage is given by the equation
(OS_ = AGND):

Table 2. Unipolar Code Table (Gain = +2)

REF_

Figure 9. Unipolar Output Circuit (Rail-to-Rail)

ANALOG OUTPUT

1111 1111 1111 (0)

1000 0000 0001 (0)

DAC CONTENTS

MSB LSB

1000 0000 0000 (0)

0111 1111 1111 (0)

0000 0000 0000 (0) 0V

0000 0000 0001 (0)

Figure 10. Setting OS_ for Output Offset

Note: ( ) are for the sub-bit.

GAIN = +2V/V

MAX5104

DAC_

REF_

MAX5104

DAC _

AGND DGND

+5V/+3V

V

DD

R

R

DGNDAGND

+5V/+3V

V

DD

R

R

+V

REF

+V

REF



2048

+V

REF REF



4096



+V

REF

+V

REF



4095



4096




2049



4096





2047



4096






4096



OS_






OS_

OUT_

V

OS

OUT_



⋅

2







⋅ 2





⋅ 2

=

V



⋅ 2






1

⋅ 2





MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC

with Serial Interface

______________________________________________________________________________________ 11

MAX5104

V

OUT

= V

REF

[((2 · NB) / 4096) - 1]

where NB represents the numeric value of the DAC’s
binary input code. Table 3 shows digital codes and the
corresponding output voltage for Figure 11’s circuit.

Using an AC Reference

In applications where the reference has an AC signal
component, the MAX5104 has multiplying capabilities
within the reference input voltage range specifications.
Figure 12 shows a technique for applying a sinusoidal
input to REF_, where the AC signal is offset before
being applied to the reference input.

Harmonic Distortion and Noise

The total harmonic distortion plus noise (THD+N) is typ­ically less than -78dB at full scale with a 1Vp-p input
swing at 5kHz.

Digital Calibration and

Threshold Selection

Figure 13 shows the MAX5104 in a digital calibration
application. With a bright-light value applied to the pho­todiode (on), the DAC is digitally ramped until it trips
the comparator. The microprocessor (µP) stores this
“high” calibration value. Repeat the process with a dim
light (off) to obtain the dark current calibration.

Table 3. Bipolar Code Table

ANALOG OUTPUT

1111 1111 1 111 (0)

1000 0000 0 001 (0)

DAC CONTENTS

MSB LSB

1000 0000 0 000 (0) 0V

0111 1111 1 111 (0)

0000 0000 0 000 (0)

0000 0000 0 001 (0)

Figure 11. Bipolar Output Circuit

Figure 12. AC Reference Input Circuit

Figure 13. Digital Calibration

Note: ( ) are for the sub-bit.

+V

REF

+V

REF

-V

REF

+V

REF



2048

-V



REF REF

2048







2047





2048









1





2048









1





2048









2047

⋅ 2





4096







=

-V





+5V/

+3V

AC

REFERENCE

INPUT

500mVp-p

26k

+5V/+3V

MAX495

10k

REF

DAC_

MAX5104

V

DD

R

OS_

R

DGNDAGND

OUT_

REF_

MAX5104

DAC _

+5V/+3V

VDD

V+

10k 10k

OS_

R

R

AGNDDGND

10k

OUT_

V+

V

OUT

10k

V-

REF_

µP

DAC _

DIN

AGND

MAX5104

+5V/+3V

VDD

DGND

R

R

OUT_

OS_

PHOTODIODE

V+

V-

R

PULLDOWN

V

OUT

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

12

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface

The µP then programs the DAC to set an output voltage
at the midpoint of the two calibrated values. Applications
include tachometers, motion sensing, automatic readers,
and liquid-clarity analysis.

Digital Control of Gain and Offset

The two DACs can be used to control the offset and gain
for curve-fitting nonlinear functions, such as transducer
linearization or analog compression/expansion applica­tions. The input signal is used as the reference for the
gain-adjust DAC, whose output is summed with the output
from the offset-adjust DAC. The relative weight of each
DAC output is adjusted by R1, R2, R3, and R4 (Figure 14).

Power-Supply Considerations

On power-up, the input and DAC registers clear (set to
zero code). For rated performance, V

REF_

should be at

least 1.4V below VDD. Bypass the power supply with a

4.7µF capacitor in parallel with a 0.1µF capacitor to
AGND. Minimize lead lengths to reduce lead inductance.

Grounding and Layout Considerations

Digital and AC transient signals on AGND can create
noise at the output. Connect AGND to the highest quality
ground available. Use proper grounding techniques,
such as a multilayer board with a low-inductance ground
plane. Carefully lay out the traces between channels to
reduce AC cross-coupling and crosstalk. Wire-wrapped
boards and sockets are not recommended. If noise
becomes an issue, shielding may be required.

Chip Information

TRANSISTOR COUNT: 3053
SUBSTRATE CONNECTED TO AGND

VDD

Figure 14. Digital Control of Gain and Offset

16
15
14
13
12
11
10

9

1
2
3
4
5
6
7
8

AGND V

DD

OUTB
OSB
REFB
PDL
UPO
DOUT
DGND

TOP VIEW

MAX5104

QSOP

OUTA

OSA

CS

REFA

CL

DIN

SCLK

Pin Configuration

Package Information

Package information is available on Maxim’s website:
www.maxim-ic.com.

OSA

REFA

V

IN

SCLK

DIN

REFB

V

REF

MAX5104

CS

SHIFT

REGISTER

INPUT
REG A

INPUT
REG B

DAC

REG A

DAC

REG B

DACA

DACB

AGND DGND

R

R

OUTA

OUTB

R

R

OSB

R1

R2

R3

=

GAIN

V

OUT

– OFFSET

[ ]

[ ]

2NA

V

=

IN

)(

(

[ ] [ ]

4096

NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA.
NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.

R4

R2

1+

)

)(

R1+R2R4R3

V

OUT

V

(

2NB

REF

4096R4R3

)(

)