Rainbow Electronics MAX5101 User Manual

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General Description

The MAX5101 parallel-input, voltage-output, triple 8-bit
digital-to-analog converter (DAC) operates from a sin­gle +2.7V to +5.5V supply and comes in a space-sav­ing 16-pin TSSOP package. Internal precision buffers
swing Rail-to-Rail®. For all three DACs, the internal ref­erence voltage is tied to VDD.

The MAX5101 has separate input latches for each of its
three DACs. Data is transferred to the input latches
from a common 8-bit input port. The DACs are individu­ally selected through address inputs A0 and A1 and
are updated by bringing WR low.

The MAX5101 features a 1µA software shutdown mode,
as well as a power-on reset mode that resets all regis­ters to code 00 hex on power-up.

Applications

Digital Gain and Offset Adjustment

Programmable Attenuators

Portable Instruments

Power-Amp Bias Control

Features

♦ +2.7V to +5.5V Single-Supply Operation

♦ Ultra-Low Supply Current

0.3mA while Operating
1µA in Software Shutdown Mode

♦ Ultra-Small 16-Pin TSSOP Package

♦ Output Buffer Amplifiers Swing Rail-to-Rail

♦ Power-On Reset Sets All Registers to Zero

MAX5101

+2.7V to +5.5V, Low-Power, Triple, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

________________________________________________________________ Maxim Integrated Products 1

19-1560; Rev 0; 10/99

PART

MAX5101AEUE

MAX5101BEUE -40°C to +85°C

-40°C to +85°C

TEMP. RANGE

PIN-

PACKAGE

16 TSSOP

16 TSSOP

Pin Configuration

Ordering Information

INL

(LSB)

±1

±2

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

Functional Diagram

OUTB

OUTC

DAC B

DAC C

INPUT

LATCH B

CONTROL

LOGIC

A0

D0–D7

WR

OUTA

DAC A

INPUT

LATCH A

A1

INPUT

LATCH C

MAX5101

TOP VIEW

1

OUTB OUTC

OUTA

2

V

3

DD

4

WR

D7

5

D6

6

D5

7

D4

8

16

15

GND

14

A0

MAX5101

TSSOP

13

A1

12

D0

D1

11

10

D2

9

D3

MAX5101

+2.7V to +5.5V, Low-Power, Triple, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= +2.7V to +5.5V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at VDD= +3V and

T

A

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND..............................................................-0.3V to +6V

D_, A_, WR to GND ..................................................-0.3V to +6V

OUT_ to GND ...........................................................-0.3V to V

DD

Maximum Current into Any Pin .........................................±50mA

Continuous Power Dissipation (T

A

= +70°C)

16-Pin TSSOP (derate 5.7mW/°C above +70°C) ..........457mW

Operating Temperature Range

MAX5101_EUE .................................................-40°C to +85°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

Code 00 to code FF hex

MAX5101A

Code 00 to code FF hex

To 1/2LSB, from code 10 to code F0 hex

From code 00 to code F0 hex

VIN= VDDor GND

Code = F0 hex

VDD= 2.7V to 3.6V

Code = F0 hex

Code = 00 hex

MAX5101B

Guaranteed monotonic

Code = 00 hex

Code = 00 hex, VDD= 2.7V to 5.5V

RL= ∞

CONDITIONS

nVs0.5Digital Feedthrough (Note 5)

nVs500

Channel-to-Channel Isolation
(Note 4)

µs6Output Settling Time (Note 3)

V/µs0.6Output Voltage Slew Rate

pF10C

IN

Input Capacitance

µA±1.0I

IN

Input Current

V0.8V

IL

Input Low Voltage

V

2

V

IH

Input High Voltage

V0V

DD

Output Voltage Range

LSB

±2

INLIntegral Nonlinearity (Note 1)

Bits8Resolution

LSB/°C±0.001

Gain-Error Temperature
Coefficient

%±1Gain Error (Note 2)

µV/°C±10

Zero-Code Temperature
Coefficient

LSB±1DNLDifferential Nonlinearity (Note 1)

mV±20ZCEZero-Code Error

mV10

Zero-Code-Error Supply
Rejection

UNITSMIN TYP MAXSYMBOLPARAMETER

±1

VDD= 3.6V to 5.5V 3

STATIC ACCURACY

DAC OUTPUTS

DIGITAL INPUTS

DYNAMIC PERFORMANCE

MAX5101

+2.7V to +5.5V, Low-Power, Triple, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +2.7V to +5.5V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at VDD= +3V and

T

A

= +25°C.)

Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded.
Note 2: Gain error is: [100 (V

F0,meas

- ZCE - V

F0,ideal

) / VDD]. Where V

F0,meas

is the DAC output voltage with input code F0 hex, and

V

F0,ideal

is the ideal DAC output voltage with input code F0 hex (i.e., VDD· 240 / 256).

Note 3: Output settling time is measured from the 50% point of the falling edge of WR to ±1/2LSB of V

OUT

’s final value.

Note 4: Channel-to-Channel Isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any

other DAC output. The measured channel has a fixed code of 80 hex.

Note 5: Digital Feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight

data inputs with WR at V

DD

.

Note 6: R

L

= ∞ , digital inputs at GND or VDD.

Note 7: Timing measurement reference level is (V

IH

+ VIL) / 2.

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

Digital-to-Analog Glitch Impulse Code 80 hex to code 7F hex 90 nVs

Wideband Amplifier Noise 60 µV

RMS

Shutdown Recovery Time t

SDR

To ±1/2LSB of final value of V

OUT

13 µs

Time to Shutdown t

SDN

IDD< 5µA 20 µs

Power-Supply Voltage V

DD

2.7 5.5 V

Supply Current (Note 6) I

DD

280 520 µA

Shutdown Current 13µA

Address to WR Setup

t

AS

5 ns

Address to WR Hold

t

AH

0 ns

Data to WR Setup

t

DS

25 ns

WR Pulse Width

t

WR

20 ns

Data to WR Hold

t

DH

0 ns

POWER SUPPLIES

DIGITAL TIMING (Figure 1) (Note 7)

MAX5101

+2.7V to +5.5V, Low-Power, Triple, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs

4 _______________________________________________________________________________________

__________________________________________Typical Operating Characteristics

(VDD= +3V, RL= 10kΩ, CL= 100pF, code = FF hex, TA = +25°C, unless otherwise noted.)

0

0.4

0.2

0.8

0.6

1.0

1.2

0426810

DAC ZERO-CODE OUTPUT VOLTAGE

vs. SINK CURRENT

MAX5101-01

SINK CURRENT (mA)

V

OUT

(V)

VDD = 3V

VDD = 5V

0

2

6

4

8

10

0426810

DAC FULL-SCALE OUTPUT VOLTAGE

vs. SOURCE CURRENT

MAX5101-02

SOURCE CURRENT (mA)

V

OUT

(V)

VDD = 3V

VDD = 5V

140

160

200

180

240

220

260

-40 0-20 20 40 60 80 100

SUPPLY CURRENT vs. TEMPERATURE

MAX5101-03

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

1 DAC AT CODE 00 OR F0
2 DACs AT CODE 00 (R

L

= ∞)

VDD = 5V; CODE = F0 HEX

VDD = 3V; CODE = F0 HEX

VDD = 5V; CODE = 00 HEX

VDD = 3V; CODE = 00 HEX

WORST-CASE 1LSB DIGITAL STEP

CHANGE (NEGATIVE)

MAX5101-04

2µs/div

CH2

CH1

CH1 = WR, 2V/div
CH2 = V

OUTA

, 50mV/div, AC-COUPLED

DAC CODE FROM 80 TO 7F HEX

WORST-CASE 1LSB DIGITAL STEP

CHANGE (POSITIVE)

MAX5101-05

2µs/div

CH2

CH1

CH1 = WR, 2V/div
CH2 = V

OUTA

, 50mV/div, AC-COUPLED

DAC CODE FROM 7F TO 80 HEX

Figure 1. Timing Diagram

SEE NOTE 7, ELECTRICAL CHARACTERISTICS

ADDRESS

WR

DATA

t

AS

ADDRESS VALID

t

WR

t

DS-

DATA VALID

t

AH-

t

DH-

MAX5101

+2.7V to +5.5V, Low-Power, Triple, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

_______________________________________________________________________________________ 5

Typical Operating Characteristics (continued)

(VDD= +3V, RL= 10kΩ, CL= 100pF, code = FF hex, TA = +25°C, unless otherwise noted.)

DIGITAL FEEDTHROUGH GLITCH IMPULSE

(0 TO 1 DIGITAL TRANSMISSION)

MAX5101-06

200ns/div

CH2

CH1

CH1 = D7, 2V/div
CH2 = V

OUTA

, 1mV/div, AC-COUPLED

0 TO 1 DIGITAL TRANSITION ON
ALL DATA BITS (WITH WR HIGH)

DIGITAL FEEDTHROUGH GLITCH IMPULSE

(1 TO 0 DIGITAL TRANSMISSION)

MAX5101-07

200ns/div

CH2

CH1

CH1 = D7, 2V/div
CH2 = V

OUTB

, 1mV/div, AC-COUPLED

1 TO 0 DIGITAL TRANSITION ON
ALL DATA BITS (WITH WR HIGH)

INTEGRAL AND DIFFERENTIAL NONLINEARITY

vs. DIGITAL CODE

0.5
RL = ∞

0.4

0.3

0.2

0.1

0

-0.1

INL/DNL (LSB)

-0.2

-0.3

-0.4

-0.5
0 32 64 96 128 160 192 224 256

DNL

DIGITAL CODE

CH1

CH2

CH1 = WR, 2V/div
CH2 = V

NEGATIVE SETTLING TIME

DAC CODE FROM F0 TO 10 HEX

1µs/div

, 2V/div

OUTA

MAX5101-09

CH1

CH2

CH1 = WR, 2V/div
CH2 = V

INL

POSITIVE SETTLING TIME

DAC CODE FROM 10 TO F0 HEX

1µs/div

, 2V/div

OUTA

MAX5101-10

MAX5101-08

MAX5101

+2.7V to +5.5V, Low-Power, Triple, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs

6 _______________________________________________________________________________________

Detailed Description

Digital-to-Analog Section

The MAX5101 uses a matrix decoding architecture for the
digital-to-analog converters (DACs). The internal refer­ence voltage is connected to VDDand divided down by a
resistor string placed in a matrix fashion. Row and col­umn decoders select the appropriate tab from the resistor
string to provide the needed analog voltages. The resistor
network converts the 8-bit digital input into an equivalent
analog output voltage in proportion to the supply voltage
(VDD). The resistor string presents a code-independent
input impedance to the supply and guarantees a monoto­nic output.

The voltages are buffered by rail-to-rail op amps con­nected in a follower configuration to provide a rail-to-rail
output (see Functional Diagram).

Output Buffer Amplifiers

The DAC outputs are internally buffered by a precision
amplifier with a typical slew rate of 0.6V/µs. The typical
settling time to ±1/2LSB at the output is 6µs when
loaded with 10kΩ in parallel with 100pF.

DAC Reference Voltage

The MAX5101’s reference is internally tied to VDD. The
output voltage (V

OUT

) for any DAC is represented by a

digitally programmable voltage source as follows:

V

OUT

= (NB· VDD) / 256

where N

B

is the numeric value of the DAC binary input

code.

Digital Inputs and Interface Logic

In the MAX5101, address lines A0 and A1 select the DAC
that receives data from D0–D7, as shown in Table 1.
When WR is low, the addressed DAC’s input latch is
transparent. Data is latched when WR is high. The DAC
outputs (OUTA, OUTB) represent the data held in the
three 8-bit input latches. To avoid output glitches in the
MAX5101, ensure that data is valid before WR goes low.

Low-Power Shutdown Mode

The MAX5101 features a software shutdown mode. A
write performed to address A1 = H and A0 = H causes
the device to shut down. A subsequent write to any of
the other three addresses disables shutdown and turns
the analog circuitry on. As the MAX5101 comes out of
shutdown, all registers retain their digital values prior to
shutdown. However, when the device powers up (i.e.,
VDDramps up), all latches are internally preset with
code 00 hex. In shutdown, the output amplifiers enter a
high-impedance state. When bringing the device out of
shutdown, allow 13µs for the output to stabilize.

Power-Supply Bypassing and

Ground Management

Digital or AC transient signals on GND can create noise
at the analog output. Return GND to the highest-quality
ground available. Bypass VDDwith a 0.1µF capacitor,
located as close to VDDand GND as possible.

Careful PC board ground layout minimizes crosstalk
between the DAC outputs and digital inputs.

NAME FUNCTION

1 OUTB DAC B Voltage Output

2 OUTA DAC A Voltage Output

PIN

3 V

DD

Positive Supply Voltage. Bypass VDDto GND using a 0.1µF capacitor.

4

WR Write Input (active low). Use WR to load data into the DAC input latch selected by A0 and A1.

15 GND Ground

14 A0 DAC Address Select Bit (LSB)

13 A1 DAC Address Select Bit (MSB)

5–12 D7–D0 Data Inputs 7–0

16 OUTC DAC C Voltage Output

Pin Description

MAX5101

+2.7V to +5.5V, Low-Power, Triple, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

_______________________________________________________________________________________ 7

Table 1. MAX5101 Addressing Table (partial)

H = high state, L = low state, X = don’t care

Chip Information

TRANSISTOR COUNT: 6848

X

A0

Input data latched

OPERATION

L DAC A input latch transparentLL

H DAC A input latch transparent

L DAC A input latch transparentH

XH

L

LL

H Enter shutdown modeHL

WR

A1

MAX5101

+2.7V to +5.5V, Low-Power, Triple, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information

TSSOP.EPS