Rainbow Electronics MAX5100 User Manual

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General Description

The MAX5100 parallel-input, voltage-output, quad 8-bit
digital-to-analog converter (DAC) operates from a sin­gle +2.7V to +5.5V supply and comes in a space-sav­ing 20-pin TSSOP package. Internal precision buffers
swing Rail-to-Rail®, and the reference input range
includes both ground and the positive rail. All four
DACs share a common reference input.

The MAX5100 provides double-buffered logic inputs:
four 8-bit buffer registers followed by four 8-bit DAC
registers. This keeps the DAC outputs from changing
during the write operation. An asynchronous control
pin, LDAC, allows for simultaneous updating of the
DAC registers.

The MAX5100 features a shutdown mode that reduces
current to 1nA, as well as a power-on reset mode that
resets all registers to code 00 hex on power-up.

Applications

Digital Gain and Offset Adjustments

Programmable Attenuators

Portable Instruments

Power-Amp Bias Control

Features

♦ +2.7V to +5.5V Single-Supply Operation

♦ Ultra-Low Supply Current

0.4mA while Operating
1nA in Shutdown Mode

♦ Ultra-Small 20-Pin TSSOP Package

♦ Ground to V

DD

Reference Input Range

♦ Output Buffer Amplifiers Swing Rail-to-Rail

♦ Double-Buffered Registers for Synchronous

Updating

♦ Power-On Reset Sets All Registers to Zero

MAX5100

+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

________________________________________________________________ Maxim Integrated Products 1

19-1557; Rev 0; 10/99

PART

MAX5100AEUP

MAX5100BEUP -40°C to +85°C

-40°C to +85°C

TEMP. RANGE PIN-PACKAGE

20 TSSOP

20 TSSOP

Pin Configuration

Ordering Information

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

INL

(LSB)

±1

±2

TOP VIEW

OUTB

OUTA

V

SHDN

WR

1

2

3

DD

4

MAX5100

5

6

D7

7

8

9

D5

10

TSSOP

20

OUTC

19

OUTD

18

GND

17

A0REF

A1

16

LDAC

15

14

D0

D1D6

13

12

D2

11

D3D4

MAX5100

+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= V

REF

= +2.7V to +5.5V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at VDD= V

REF

= +3V and TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND..............................................................-0.3V to +6V

D_, A_, WR, SHDN, LDAC to GND...........................-0.3V to +6V

REF to GND................................................-0.3V to (V

DD

+ 0.3V)

OUT_ to GND ...........................................................-0.3V to V

DD

Maximum Current into Any Pin .........................................±50mA

Continuous Power Dissipation (T

A

= +70°C)

20-Pin TSSOP (derate 7.0mW/°C above +70°C) .......559mW

Operating Temperature Range

MAX5100_EUP ..............................................-40°C to +85°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

V

DD

= 4.5V to 5.5V,

V

REF

= 4.096V

VDD= 2.7V to 3.6V,
V

REF

= 2.5V

VIN= VDDor GND

MAX5100A

VDD= 3.6V to 5.5V

VDD= 2.7V to 3.6V

RL= ∞

Code = F0 hex

Code = F0 hex

Code = 00 hex

MAX5100B

Guaranteed monotonic

Code = 00 hex

Code = 00 hex, VDD= 2.7V to 5.5V

CONDITIONS

µA

±1.0

I

IN

Input Current

V

0.8

V

IL

Input Low Voltage

3

V

2

V

IH

Input High Voltage

V

0V

REF

Output Voltage Range

pF

15

Input Capacitance

kΩ

320 460 600

Input Resistance

V

0V

DD

Input Voltage Range

1

LSB

±1

INLIntegral Nonlinearity (Note 1)

Bits

8

Resolution

LSB

1

Power-Supply Rejection

LSB/°C

±0.001

Gain-Error Temperature
Coefficient

%

±1

Gain Error (Note 2)

µV/°C

±10

Zero-Code Temperature
Coefficient

±2

LSB

±1

DNLDifferential Nonlinearity (Note 1)

mV

±20

ZCEZero-Code Error

mV

10

Zero-Code-Error Supply
Rejection

UNITSMIN TYP MAXSYMBOLPARAMETER

pF

10

C

IN

Input Capacitance

Code = FF hex

STATIC ACCURACY

REFERENCE INPUT

DAC OUTPUTS

DIGITAL INPUTS

MAX5100

+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

_______________________________________________________________________________________ 3

Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded.
Note 2: Gain error is: [100 (V

F0,meas

- ZCE - V

F0,ideal

) / V

REF

]. Where V

F0,meas

is the DAC output voltage with input code F0 hex,

and V

F0,ideal

is the ideal DAC output voltage with input code F0 hex (i.e., V

REF

· 240 / 256).

Note 3: Output settling time is measured from the 50% point of the falling edge of WR to ±1/2LSB of V

OUT

’s final value.

Note 4: Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any

other DAC output. The measured channel has a fixed code of 80 hex.

Note 5: Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight

data inputs with WR at V

DD

.

Note 6: R

L

= ∞, digital inputs at GND or VDD.

Note 7: Timing measurement reference level is (V

IH

+ VIL) / 2.

Note 8: If LDAC is activated prior to WR’s rising edge, it must stay low for t

LD

(or longer) after WR goes high.

ELECTRICAL CHARACTERISTICS (continued)

(VDD= V

REF

= +2.7V to +5.5V, RL= 10kΩ, CL= 100pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at VDD= V

REF

= +3V and TA= +25°C.)

V

REF(DC)

= 1.5V,
VDD= 3V,
code = FF hex

LDAC Pulse Width (Note 8)

t

LD

20

ns

Digital-to-Analog Glitch Impulse

90

nVs

Digital Feedthrough (Note 5)

0.5

nVs

Channel-to-Channel Isolation
(Note 4)

500

nVs

Output Settling Time (Note 3)

6

µs

Signal-to-Noise plus Distortion
Ratio

SINAD

70

dB

60

Multiplying Bandwidth

650

kHz

Wideband Amplifier Noise

60

µV

RMS

Output Voltage Slew Rate

0.6

V/µs

Shutdown Recovery Time t

SDR

13

µs

Time to Shutdown t

SDN

20

µs

Power-Supply Voltage V

DD

2.7 5.5

V

Supply Current (Note 6) I

DD

370 700

µA

Shutdown Current

0.001 1

µA

Address to WR Setup

t

AS

5

ns

Address to WR Hold

t

AH

0

ns

Data to WR Setup

t

DS

25

ns

Data to WR Hold

t

DH

0

ns

WR Pulse Width

t

WR

20

ns

To ±1/2LSB of final value of V

OUT

Code 80 hex to code 7F hex

IDD< 5µA

Code 00 to code FF hex

Code 00 to code FF hex

To 1/2LSB, from code 10 to code F0 hex

REF = 0.5Vp-p, V

REF(DC)

= 1.5V,

V

DD

= 3V, -3dB bandwidth

From code 00 to code F0 hex

PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS

REF = 2.5Vp-p at
1kHz

REF = 2.5Vp-p at
10kHz

DYNAMIC PERFORMANCE

POWER SUPPLIES

DIGITAL TIMING (Figure 1) (Note 7)