Rainbow Electronics MAX510 User Manual

19-0155; Rev 2; 1/96

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

_______________General Description

The MAX509/MAX510 are quad, serial-input, 8-bit volt­age-output digital-to-analog converters (DACs). They
operate with a single +5V supply or dual ±5V supplies.
Internal, precision buffers swing rail-to-rail. The refer­ence input range includes both supply rails.

The MAX509 has four separate reference inputs, allow­ing each DAC's full-scale range to be set independently.
20-pin DIP, SSOP, and SO packages are available. The
MAX510 is identical to the MAX509 except it has two ref­erence inputs, each shared by two DACs. The MAX510
is housed in space-saving 16-pin DIP and SO packages.

The serial interface is double-buffered: A 12-bit input
shift register is followed by four 8-bit buffer registers and
four 8-bit DAC registers. A 12-bit serial word is used to

____________________________Features

♦ Single +5V or Dual ±5V Supply Operation
♦ Output Buffer Amplifiers Swing Rail-to-Rail
♦ Reference Input Range Includes Both Supply Rails
♦ Calibrated Offset, Gain, and Linearity (1LSB TUE)
♦ 10MHz Serial Interface, Compatible with SPI, QSPI

(CPOL = CPHA = 0) and Microwire

♦ Double-Buffered Registers for Synchronous

Updating

♦ Serial Data Output for Daisy-Chaining
♦ Power-On Reset Clears Serial Interface and Sets

All Registers to Zero

______________Ordering Information

load data into each register. Both input and DAC regis­ters can be updated independently or simultaneously
with single software commands. Two additional asyn­chronous control pins provide simultaneous updating
(LDAC) or clearing (CLR) of input and DAC registers.

The interface is compatible with MicrowireTMand SPI/
QSPITM. All digital inputs and outputs are TTL/CMOS
compatible. A buffered data output provides for read­back or daisy-chaining of serial devices.

_______________Functional Diagrams

CLR

DOUT

LDAC

12-BIT
SHIFT

REGISTER

SR

CONTROL

CS DIN

Functional Diagrams continued at end of data sheet.

Microwire is a trademark of National Semiconductor. SPI and QSPI are trademarks of Motorola.

DGND

INPUT
REG A

INPUT
REG B

INPUT
REG C

INPUT
REG D

V

SS

MAX509

V

DD

DAC

REG A

DAC

REG B

DAC

REG C

DAC

REG D

AGND

DECODE

CONTROL

SCLK REFC

REFAREFB

OUTA

DAC A

OUTB

DAC B

OUTC

DAC C

OUTD

DAC D

REFD

PART TEMP. RANGE PIN-PACKAGE

MAX509ACPP

0°C to +70°C 20 Plastic DIP
MAX509BCPP 0°C to +70°C 20 Plastic DIP
MAX509ACWP 0°C to +70°C 20 Wide SO
MAX509BCWP 20 Wide SO ±1 1/2

0°C to +70°C
MAX509ACAP 0°C to +70°C 20 SSOP ±1
MAX509BCAP 0°C to +70°C 20 SSOP ±1 1/2
MAX509BC/D 0°C to +70°C Dice* ±1 1/2

Ordering Information continued on last page.

* Dice are specified at +25°C, DC parameters only.

**Contact factory for availability and processing to MIL-STD-883.

_________________Pin Configurations

TOP VIEW

OUTB

1

OUTA

2

V

SS

3

REFB

4

REFA

5

AGND

6

N.C.

7

DGND

8

LDAC

9

DOUT

10

Pin Configurations continued at end of data sheet.

DIP/SO/SSOP

MAX509

MAX509/MAX510

TUE

(LSB)

±1
±1 1/2
±1

OUTC

20

OUTD

19

V

18

DD

REFC

17

REFD

16

CS

15

N.C.

14

SCLK

13

DIN

12

CLR

11

________________________________________________________________

Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone]

Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

ABSOLUTE MAXIMUM RATINGS

VDDto DGND ..............................................................-0.3V, +6V

to AGND...............................................................-0.3V, +6V

V

DD

to DGND...............................................................-6V, +0.3V

V

SS

to AGND...............................................................-6V, +0.3V

V

SS

to VSS.................................................................-0.3V, +12V

V

DD

Digital Input Voltage to DGND ......................-0.3V, (V

REF_....................................................(V

OUT_..............................................................................V

Maximum Current into Any Pin............................................50mA

Continuous Power Dissipation (T

16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW

16-Pin Wide SO (derate 9.52mW/°C above +70°C).........762mW

16-Pin CERDIP (derate 10.00mW/°C above +70°C) ........800mW

Note: The outputs may be shorted to VDD, VSS, or AGND if the package power dissipation is not exceeded. Typical short-circuitcurrent

MAX509/MAX510

to AGND is 50mA. Do not bias AGND more than +1V above DGND, or more than 2.5V below DGND.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

A

- 0.3V), (VDD+ 0.3V)

SS

= +70°C)

DD

+ 0.3V)

, V

DD

SS

ELECTRICAL CHARACTERISTICS

(VDD= +5V ±10%, VSS= 0V to -5.5V, V
unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

STATIC ACCURACY

Resolution 8 Bits

Total Unadjusted Error

Differential Nonlinearity ±1 LSBGuaranteed monotonic

Zero-Code Error

Zero-Code-Error Supply Rejection 12mV
Zero-Code

Temperature Coefficient
Full-Scale Error ±14 mVCode = FF hex

Full-Scale-Error Supply Rejection

Full-Scale-Error
Temperature Coefficient

= 4V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= T

REF

SYMBOL

VREF = +4V,

TUE

DNL

ZCE

VSS= 0V or -5V ±10%
VREF = -4V,

VSS= -5V ±10%

Code = 00 hex,
VSS= 0V

Code = 00 hex,
VSS= -5V ±10%

Code = 00 hex, VDD= 5V ±10%,

= 0V or -5V ±10%

V

SS

Code = FF hex,
VDD= +5V ±10%,
VSS= 0V or -5V ±10%

20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW

20-Pin Wide SO (derate 10.00mW/°C above +70°C).......800mW

20-Pin SSOP (derate 10.00mW/°C above +70°C)............800mW

20-Pin CERDIP (derate 11.11mW/°C above +70°C) ........889mW

Operating Temperature Ranges:

MAX5_ _ _C_ _.....................................................0°C to +70°C

MAX5_ _ _E_ _..................................................-40°C to +85°C

MAX5_ _ _MJ_ ................................................-55°C to +125°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

to T

MAX

±1.5

±1.5

±1MAX5_ _A

±1MAX5_ _A

14MAX5_ _C
16MAX5_ _E

20MAX5_ _M
±14MAX5_ _C
±16MAX5_ _E
±20

,

LSB

MAX5_ _B

MAX5_ _B

MAX5_ _M

MAX5_ _M

MIN

±10 µV/°CCode = 00 hex

14MAX5_ _C
18MAX5_ _E
112

±10 µV/°CCode = FF hex

mV

mV

2 _______________________________________________________________________________________

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±10%, VSS= 0V to -5.5V, V
unless otherwise noted.)

PARAMETER

REFERENCE INPUTS

Input Voltage Range
Input Resistance (Note 1)

Input Capacitance (Note 2)

DAC OUTPUTS

Full-Scale Output Voltage V

Resistive Load

DIGITAL INPUTS

Input High Voltage 2.4 VV
Input Low Voltage 0.8 VV
Input Current 1.0 µAI

DIGITAL OUTPUTS

DYNAMIC PERFORMANCE

Voltage-Output Slew Rate

Digital Feedthrough 5 nV-s
Digital-to-Analog Glitch Impulse

Signal-to-Noise + Distortion Ratio

Wideband Amplifier Noise 60

= 4V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= T

REF

SYMBOL

IH
IL

IN

IN

OH
OL

(Note 3)Channel-to-Channel Isolation -60 dB
(Note 4)AC Feedthrough -70 dB

VREF = 4V, load regulation ≤ 1/4LSB 2
VREF = -4V, V

load regulation ≤ 1/4LSB
VREF = VDDMAX5_ _C/E,

load regulation ≤ 1LSB
VREF = VDDMAX5_ _M,

load regulation ≤ 2LSB

VIN= 0V or V
(Note 5)Input Capacitance 10 pFC

I

SOURCE

I

SINK

To 1/2LSB, 10kΩ II 100pF loadOutput Settling Time (Note 6) 6 µs
Code = 00 hex, all digital inputs

from 0V to V
Code 128➝127

VREF = 4V
code = FF hex

VREF = 4V

CONDITIONS MIN TYP MAX UNITS

MAX509 16 24
MAX510
MAX509 15
MAX510

= -5V ±10%,

SS

DD

= 0.2mAOutput High Voltage VDD- 0.5 VV

= 1.6mAOutput Low Voltage 0.4 VV

MAX5_ _C 1.0
MAX5_ _E 0.7
MAX5_ _M

DD

at 1kHz, VDD= 5V,

p-p

at 20kHz, VSS= -5V ±10% 74

p-p

, 3dB bandwidthMultiplying Bandwidth 1

p-p

to T

MIN

V

SS

812

30

SS

2

10

10

0.5

12 nV-s
87

MAX

V

V

,

DD

DD

µV

MAX509/MAX510

V

kΩCode = 55 hex

pFCode = 00 hex

V

kΩ

V/µsPositive and negative

dBSINAD

MHzVREF = 0.5V

RMS

_______________________________________________________________________________________ 3

Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±10%, VSS= 0V to -5.5V, V
unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

POWER SUPPLIES

Positive Supply Voltage
Negative Supply Voltage -5.5 0 VFor specified performanceV

Positive Supply Current

Negative Supply Current mAI

Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex.
Note 3: VREF = 4V

MAX509/MAX510

code of all other DACs to 00 hex.

Note 4: VREF = 4V
Note 5: Guaranteed by design.
Note 6: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.

, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the

p-p

, 10kHz. DAC code = 00 hex.

p-p

TIMING CHARACTERISTICS

(VDD= +5V ±10%, VSS= 0V to -5V, V

PARAMETER

LDAC Pulse Width Low
CS Rise to LDAC Fall Setup Time
CLR Pulse Width Low

SERIAL INTERFACE TIMING

CS Fall to SCLK Setup Time
SCLK Fall to CS Rise Hold Time

SCLK Rise to CS Rise Hold Time
SCLK Fall to CS Fall Hold Time

DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time 0 nst
SCLK Clock Frequency

SCLK Pulse Width High

SCLK Pulse Width Low

SCLK to DOUT Valid

Note 7: Guaranteed by design.
Note 8: If LDAC is activated prior to CS's rising edge, it must stay low for t
Note 9: Minimum delay from 12th clock cycle to CS rise.

= 4V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= T

REF

SYMBOL

DD

SS

DD

SS

REF

SYMBOL

t

LDW

t

CLL

t

CLW

t

CSS

CSH2
CSH1
CSH0

t

DS

DH

f

CLK

t

CH

CL

t

DO

Outputs unloaded, all
digital inputs = 0V or V

VSS= -5V ±10%, outputs
unloaded, all digital
inputs = 0V or V

= 4V, AGND = DGND = 0V, CL= 50pF, TA= T

MAX5_ _C/E 40 20
MAX5_ _M 50 25
(Notes 7, 8) 0 ns
MAX5_ _C/E 40 20
MAX5_ _M

MAX5_ _M

(Note 9) 40 nst

MAX5_ _M

MAX5_ _M

MAX5_ _M
MAX5_ _C/E 40
MAX5_ _M 50

MAX5_ _M

DD

CONDITIONS MIN TYP MAX UNITS

MAX5_ _C/E

DD

MAX5_ _M
MAX5_ _C/E

or longer after CS goes high.

LDW

4.5 5.5 VFor specified performanceV

to T

MIN

MAX

50 25

40MAX5_ _C/E
50

0 nst

0 ns(Note 7)t
40MAX5_ _C/E
50

40MAX5_ _C/E
50

10 100MAX5_ _C/E
10 100

to T

MAX

,

mAI

MHz

MIN

510
512

510
512MAX5_ _M

, unless otherwise noted.)

20 12.5MAX5_ _C/E
20 10

ns

ns

ns

ns

ns

nst

ns

4 _______________________________________________________________________________________

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

__________________________________________Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

OUTPUT SINK CURRENT

12

10

8

(mA)

6

OUT

I

4

2

0

0 1.2

0.2 0.6 1.0

vs. REFERENCE VOLTAGE

6

5

VSS = -5V

4

(mA)

3

DD

I

2

VDD = +5V

1

ALL LOGIC
INPUTS = +5V

0

-4 -2 2

-5 5

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

- VSS)

vs. (V

OUT

VDD = VREF = +5V

= GND = 0V

V

SS

ALL DIGITAL INPUTS = 00 HEX

0.4
V

- VSS (V)

OUT

SUPPLY CURRENT

0

VREF VOLTAGE (V)

0.8

VSS = 0V

431-1-3

MAX509-FG01

MAX509-FG03

THD + NOISE (dB)

OUTPUT SOURCE CURRENT

vs. OUTPUT VOLTAGE

VDD = VREF = +5V

= GND

V

SS

DIGITAL INPUT = FF HEX

3.6 4.6

3.8 4.0

THD + NOISE AT DAC OUTPUT

vs. REFERENCE AMPLITUDE

VDD = +5V

= -5V

V

SS

INPUT CODE = FF HEX

FREQ = 20kHz

02 6 10

REFERENCE AMPLITUDE (Vp-p)

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

4.4

4.2
V

(V)

OUT

FREQ = 1kHz

48

(mA)

OUT

I

-40

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

-25

-20

-15

-10

-5

0

4.8

MAX509-FG10

5.0

1%

MAX509-FG04

0.1%

THD + NOISE (%)

0.01%

7
6

5

4

3

2

SUPPLY CURRENT (mA)

1

0

-60 -20 40 100

-20

-30

-40

-50

-60

THD + NOISE (dB)

-70

-80

-90

SUPPLY CURRENT

vs. TEMPERATURE

I

DD

I

SS

VDD = +5.5V

= -5.5V

V

SS

VREF = -4.75
ALL DIGITAL INPUTS = +5V

-40 0 60 120

VREF = 1Vp-p

10 1k 100k

20 80

TEMPERATURE (°C)

THD + NOISE AT DAC OUTPUT

vs. REFERENCE FREQUENCY

VDD = +5V

= -5V

V

SS

INPUT CODE = FF HEX
FREQ = SWEPT

VREF = 8Vp-p

VREF = 4Vp-p

100 10k

REFERENCE FREQUENCY (Hz)

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

140

MAX509-FG02

10%

MAX509-FG05

0.1%

0.01%

MAX509/MAX510

1%

THD + NOISE (%)

0

-10

-20

-30

RELATIVE OUTPUT (dB)

VDD = +5V

= AGND

V

SS

VREF = 2.5VDC + 0.5Vp-p SINE WAVE

-40

1k 10k 100k

FREQUENCY (Hz)

0

MAX509-FG06

-10

-20

-30

RELATIVE OUTPUT (dB)

VDD = +5V

= AGND

V

SS

VREF = 2.5VDC + 0.05Vp-p SINE WAVE

-40

10M

1M

1k 10k 100k

FREQUENCY (Hz)

10M

1M

0

MAX509-FG07

-10

-20

-30

RELATIVE OUTPUT (dB)

-40

VDD = +5V

= -5V

V

SS

VREF = 2.5VDC + 4Vp-p SINE WAVE

1k 10k 100k

FREQUENCY (Hz)

10M

1M

_______________________________________________________________________________________

MAX509-FG08

5

Quad, Serial 8-DACs
with Rail-to-Rail Outputs

____________________________Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

ZERO-CODE ERROR

vs. NEGATIVE SUPPLY VOLTAGE

5.0

4.8

4.6

4.4

4.2

4.0

ZERO-CODE ERROR (mV)

3.8

3.6

MAX509/MAX510

3.4
0-4

-1 -2

-3

VSS (V)

VDD = +5V
VREF = +4V

-5

MAX509-FG09

-6

REFERENCE FEEDTHROUGH AT 10kHz





A = REFA, 10V
B = OUTA, 50µV/div, UNLOADED
TIMEBASE = 50µs/div




p-p

A

B

WORST-CASE 1LSB DIGITAL STEP CHANGE



2V 20mV







A = CS, 2V/div
B = OUTA, 20mV ˜
TIMEBASE = 200ns/div



REFERENCE FEEDTHROUGH AT 4kHz

5V 50µV





10

A = REFA, 10V
B = OUTA, 50µV/div, UNLOADED
TIMEBASE = 100µs/div



p-p

200nS

100µS

REFERENCE FEEDTHROUGH AT 40kHz



A



B

A = REFA, 10V
B = OUTA, 100µV/div, UNLOADED
TIMEBASE = 10µs/div
V

= +5V, VSS = -5V

DD

CODE = ALL 0s

REFERENCE FEEDTHROUGH AT 400Hz



A



B

A = REFA, 10V
B = OUTA, 50µV/div, UNLOADED
TIMEBASE = 1ms/div

A

B



p-p

A

B



p-p

6 _______________________________________________________________________________________

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

____________________________Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

POSITIVE SETTLING TIME

(V

= AGND OR -5V)

SS

5V 100mV

A = DIGITAL INPUT, 5V/div
B = OUT_ , 2V/div
TIMEBASE = 1µs/div
V

= +5V

DD

REF_ = +4V
ALL BITS OFF TO ALL BITS ON
R

= 10kΩ, CL = 100pF

L

NEGATIVE SETTLING TIME

(V

5V 100mV

SS

A

B

1µS

= -5V)

A





A = SCLK, 333kHz
B = OUT_, 10mV/div
TIMEBASE = 2µs/div

5V 100mV



CLOCK FEEDTHROUGH

NEGATIVE SETTLING TIME

(V

= AGND)

SS

A

B

A







MAX509/MAX510



A = DIGITAL INPUT, 5V/div
B = OUT_ , 2V/div
TIMEBASE = 1µs/div
V

= +5V

DD

REF_ = +4V
ALL BITS ON TO ALL BITS OFF
R

= 10kΩ, CL = 100pF

L

_______________________________________________________________________________________

1µS

B



B

1µS

A = DIGITAL INPUT, 5V/div
B = OUT_ , 2V/div
TIMEBASE = 1µs/div
V

= +5V

DD

REF_ = +4V
ALL BITS ON TO ALL BITS OFF
R

= 10kΩ, CL = 100pF

L

7

Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

______________________________________________________________Pin Description

PIN

MAX509 MAX510

1

2 OUTA DAC A Voltage Output
3 V
4 REFB Reference Voltage Input for DAC B

– REFAB Reference Voltage Input for DACs A and B
5 REFA Reference Voltage Input for DAC A
6 AGND Analog Ground

MAX509/MAX510

7, 14 N.C. Not Internally Connected

8 DGND Digital Ground

9

10 DOUT8

11

12 DIN10

13 SCLK11

15

16 REFD Reference Voltage Input for DAC D–

– REFCD Reference Voltage Input for DACs C and D13

17 REFC Reference Voltage Input for DAC C–
18 V
19 OUTD DAC D Output Voltage15
20 OUTC DAC C Output Voltage16

1

2
3
–
4
–
5
–
6

7

9

12

NAME FUNCTION

OUTB DAC B Voltage Output

SS

LDAC

CLR

CS

DD

Negative Power Supply, 0V to -5V ±10%. Connect to AGND for single-supply operation.

Load DAC Input (active low). Driving this asynchronous input low (level sensitive)
transfers the contents of each input latch to its respective DAC latch.

Serial Data Output. Can sink and source current. Data at DOUT is adjustable to be
clocked out on rising or falling edge of SCLK.

Clear DAC input (active low). Driving CLR low causes an asynchronous clear of input
and DAC registers and sets all DAC outputs to zero.

Serial Data Input. TTL/CMOS-compatible input. Data is clocked into DIN on the
rising edge of SCLK. CS must be low for data to be clocked in.

Serial Clock Input. Data is clocked in on the rising edge and clocked out on either the
rising (default) or the falling edge.

Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming
commands are executed when CS rises.

Positive Power Supply, +5V ±10%14

8 _______________________________________________________________________________________

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

_______________Detailed Description

Serial Interface

At power-on, the serial interface and all DACs are
cleared and set to code zero. The serial data output
(DOUT) is set to transition on SCLK's rising edge.

The MAX509/MAX510 communicate with microproces­sors through a synchronous, full-duplex, 3-wire inter­face (Figure 1). Data is sent MSB first and can be
transmitted in one 4-bit and one 8-bit (byte) packet or
in one 12-bit word. If a 16-bit control word is used, the
first four bits are ignored. A 4-wire interface adds a line
for LDAC and allows asynchronous updating. The serial
clock (SCLK) synchronizes the data transfer. Data is
transmitted and received simultaneously.

Figure 2 shows a detailed serial interface timing.
Please note that the clock should be low if it is stopped

CS

SCLK

between updates. DOUT does not go into a high­impedance state if the clock or CS is high.

Serial data is clocked into the data registers in MSB­first format, with the address and configuration infor­mation preceding the actual DAC data. Data is
clocked in on SCLK's rising edge while CS is low. Data
at DOUT is clocked out 12 clock cycles later, either at
SCLK's rising edge (default or mode 1) or falling edge
(mode 0).

Chip select (CS) must be low to enable the DAC. If CS
is high, the interface is disabled and DOUT remains
unchanged. CS must go low at least 40ns before the
first rising edge of the clock pulse to properly clock in
the first bit. With CS low, data is clocked into the
MAX509/MAX510's internal shift register on the rising
edge of the external serial clock. SCLK can be driven
at rates up to 12.5MHz.

INSTRUCTION

EXECUTED

• • •

• • •

MAX509/MAX510

DIN

DOUT

MODE 1

(DEFAULT)

DOUT

MODE 0

C1

A1

C0 D7 D6 D5 D4 D3 D2 D1 D0

A0

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 D6 D5 D4 D3 D2 D1

A1

A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 C1 C0 D7

MSB LSB

DACA

DATA FROM PREVIOUS DATA INPUT DATA FROM PREVIOUS DATA INPUT

Figure 1. MAX509/MAX510 3-Wire Interface Timing

_______________________________________________________________________________________ 9

• • •

A1

A1

• • •

A1

• • •

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

DACD

A0 C1 C0 D7

D6 D5 D4 D3 D2 D1

A1

D0

A1

D0

A1

Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

CS

• • •

t

CSH2

t

CLL

t

CSS

t

CSH0

SCLK

DIN

MAX509/MAX510

DOUT

LDAC

NOTE: TIMING SPECIFICATION t

IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY.

CLL

t

CH

t

DS

t

DH

t

CL

t

DO

Figure 2. Detailed Serial Interface Timing (Mode 0 Shown)

Table 1. Serial-Interface Programming Commands

12-Bit Serial Word

A1

A0

0
0
1
1

0
0
1
1

C1

0
1
0
1

0
1
0
1

0
1

X

1

0

0
0
0
0

1
1
1
1

0
0

1

1

1

C0

1
1
1
1

1
1
1
1

0
0

0

0

0

D7 . . . . . . . . D0

8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data

8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data

• • •

t

CSH1

• • •

• • •

• • •

FunctionLDAC

Load DAC A input register, DAC output unchanged.

1

Load DAC B input register, DAC output unchanged.

1

Load DAC C input register, DAC output unchanged.

1

Load DAC D input register, DAC output unchanged.

1

Load input and DAC register A.

1

Load input and DAC register B.

1

Load input and DAC register C.

1

Load input and DAC register D.

1

Update all DACs from shift register.X8-Bit DAC DataX
No Operation (NOP), shifts data in shift register.XX X X X X X X X X

“LDAC” Command, all DACs updated from respective

XX X X X X X X X0

input registers.
Mode 1, DOUT clocked out on rising edge of SCLK

(default). All DACs updated from respective input

XX X X X X X X X1

registers.
Mode 0, DOUT clocked out on falling edge of SCLK.

XX X X X X X X X1

All DACs updated from input registers.

t

LDW

10 ______________________________________________________________________________________

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

The 12-bit serial input format shown in Figure 3 com-

Serial Input Data Format and Control Codes

prises two DAC address bits (A1, A0), two control bits
(C1, C0) and eight bits of data (D0...D7).

The 4-bit address/control code configures the DAC as
shown in Table 1.

DOUT

This is the first bit shifted in

MSB

A1 A0C1 C0 D7D6 

Control and

8-bit DAC data

● ● ●

 D1 D0

LSB

DIN

Address bits

Figure 3. Serial Input Format

Load Input Register, DAC Registers Unchanged

(Single Update Operation)

A1

A0

(LDAC = H)

C1

C0

8-Bit Data0 1Address

D1D2D3D4D5D6D7

D0

When performing a single update operation, A1 and A0
select the respective input register. At the rising edge
of CS, the selected input register is loaded with the cur-
rent shift-register data. All DAC outputs remain
unchanged. This preloads individual data in the input
register without changing the DAC outputs.

Load Input and DAC Registers

A1

A0

(LDAC = H)

C1

C0

8-Bit Data1 1Address

D1D2D3D4D5D6D7

D0

This command directly loads the selected DAC register
at CS's rising edge. A1 and A0 set the DAC address.
Current shift-register data is placed in the selected
input and DAC registers.

For example, to load all four DAC registers simultaneously
with individual settings (DAC A = 1V, DAC B = 2V, D AC
C = 3V and DAC D = 4V), five commands are required.
First, perform four single input register update opera­tions. Next, perform an “LDAC” command as a fifth
command. All DACs will be updated from their respec­tive input registers at the rising edge of CS.

Update All DACs from Shift Registers

A1

A0

(LDAC = x)

C1

C0

8-Bit DAC Data0 0x 0

D1D2D3D4D5D6D7

D0

All four DAC registers are updated with shift-register
data. This command allows all DACs to be set to any
analog value within the reference range. This command
can be used to substitute CLR if code 00 hex is pro­grammed, which clears all DACs.

No Operation (NOP)

A0

C1

D0D1D2D3D4D5D6D7C0

xxx xxxxx0 0x 1

A1

(LDAC = x)

The NOP command (no operation) allows data to be shift­ed through the MAX509/MAX510 shift register without
affecting the input or DAC registers. This is useful in daisy
chaining (also see the

Daisy-Chaining Devices

section).
For this command, the data bits are "Don't Cares." As an
example, three MAX509/MAX510s are daisy-chained (A, B
and C), and DAC A and DAC C need to be updated. The
36-bit-wide command would consist of one 12-bit word for
device C, followed by an NOP instruction for device B and
a third 12-bit word with data for device A. At CS's rising
edge, only device B is not updated.

“LDAC” Command (Software)

A1

(LDAC = x)

C1

A0

1 00 x xxx xxx xx

D0D1D2D3D4D5D6D7C0

All DAC registers are updated with the contents of their
respective input registers at CS's rising edge. With the
exception of using CS to execute, this performs the
same function as the asynchronous LDAC.

Set DOUT Phase – SCLK Rising (Mode 1, Default)

A1

(LDAC = x)

C1

A0

1 01 1 xxxxxxxx

D0D1D2D3D4D5D6D7C0

Mode 1 resets the serial output DOUT to transition at
SCLK's rising edge. This is the MAX509/MAX510’s
default setting after the supply voltage has been
applied.

The command also loads all DAC registers with the con­tents of their respective input registers, and is identical to
the “LDAC” command.

MAX509/MAX510

______________________________________________________________________________________ 11

Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

Set DOUT Phase – SCLK Falling (Mode 0)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

xxxxxxxx1 0 1 0

(LDAC = x)

This command resets DOUT to transition at SCLK's falling
edge. Once this command is issued, the phase of DOUT is
latched and will not change except on power-up or if the
specific command is issued that sets the phase to rising
edge.

The same command also updates all DAC registers with
the contents of their respective input registers, identical to
the “LDAC” command.

MAX509/MAX510

LDAC is typically used in 4-wire interfaces (Figure 7).
LDAC allows asynchronous hardware control of the DAC

outputs and is level-sensitive. With LDAC low, the DAC reg­isters are transparent and any time an input register is
updated, the DAC output immediately follows.

Strobing the CLR pin low causes an asynchronous clear of
input and DAC registers and sets all DAC outputs to zero.
Similar to the LDAC pin, CLR can be invoked at any time,
typically when the device is not selected (CS = H). When
the DAC data is all zeros, this function is equivalent to the
"Update all DACs from Shift Registers" command.

Digital inputs and outputs are compatible with both TTL and
5V CMOS logic. The power-supply current (IDD) depends
on the input logic levels. Using CMOS logic to drive CS,
SCLK, DIN, CLR and LDAC turns off the internal level trans­lators and minimizes supply currents.

DOUT is the output of the internal shift register. DOUT can be
programmed to clock out data on SCLK's falling edge (mode

0) or rising edge (mode 1). In mode 0, output data lags the
input data by 12.5 clock cycles, maintaining compatibility with
Microwire, SPI, and QSPI. In mode 1, output data lags the input
by 12 clock cycles. On power-up, DOUT defaults to mode 1
timing. DOUT never three-states; it always actively drives either
high or low and remains unchanged when CS is high.

The MAX509/MAX510 are Microwire, SPI, and QSPI compati­ble. For SPI and QSPI, clear the CPOL and CPHA configura­tion bits (CPOL = CPHA = 0). The SPI/QSPI CPOL = CPHA
= 1 configuration can also be used if the DOUT output is
ignored.

LDAC Operation (Hardware)

Clear DACs with CLR

Digital Inputs and Outputs

Serial Data Output

Interfacing to the Microprocessor

SCLK

MAX509

DIN

MAX510

DOUT

CS

THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES.

Figure 4. Connections for Microwire

MAX509
MAX510

THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES.

Figure 5. Connections for SPI



DOUT

DIN

SCLK

CS

SK

SO

MICROWIRE

PORT

SI

I/0

MISO

MOSI

SPI

PORT

SCK

I/0

CPOL = 0, CPHA = 0

The MAX509/MAX510 can interface with Intel's
80C5X/80C3X family in mode 0 if the SCLK clock polarity is
inverted. More universally, if a serial port is not available,
three lines from one of the parallel ports can be used for bit
manipulation.

Digital feedthrough at the voltage outputs is greatly mini­mized by operating the serial clock only to update the regis­ters. Also see the Clock Feedthrough photo in the

Operating Characteristics

section. The clock idle state is low.

Typical

Daisy-Chaining Devices

Any number of MAX509/MAX510s can be daisy-chained by
connecting the DOUT pin of one device to the DIN pin of the
following device in the chain. The NOP instruction (Table 1)
allows data to be passed from DIN to DOUT without chang­ing the input or DAC registers of the passing device. A three­wire interface updates daisy-chained or individual
MAX509/MAX510s simultaneously by bringing CS high.

12 ______________________________________________________________________________________

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

MAX509/MAX510

SCLK

DIN

SCLK

DIN

MAX509

SCLK

MAX510

DIN

CS

CS

CS

SCLK

DIN

CS

DOUT DOUT DOUT

MAX509
MAX510

SCLK

DIN

CS

MAX509
MAX510

SCLK

DIN

CS

MAX509
MAX510

TO OTHER
SERIAL DEVICES

Figure 6. Daisy-chained or individual MAX509/MAX510s are simultaneously updated by bringing CShigh. Only three wires are
required.

DIN
SCLK
LDAC

CS1

CS2

CS3

TO OTHER
SERIAL
DEVICES

CS

LDAC

SCLK

DIN

MAX509
MAX510

CS

LDAC

SCLK

DIN

MAX509
MAX510

CS

LDAC

SCLK

DIN

MAX509
MAX510

Figure 7. Multiple MAX509/MAX510 DACs sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by
enabling individual CS.

______________________________________________________________________________________ 13

Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

R

2R 2R 2R 2R 2R

D0 D5 D6 D7

REF_

AGND

SHOWN FOR ALL 1 ON DAC

Figure 8. DAC Simplified Circuit Diagram

MAX509/MAX510

If multiple devices share a common DIN line, Figure 7's
configuration provides simultaneous update by strob­ing LDAC low. CS1, CS2, CS3... are driven separately,

thus controlling which data are written to devices 1, 2, 3....

The MAX509/MAX510 contain four matched voltage­output DACs. The DACs are inverted R-2R ladder net­works that convert 8-bit digital words into equivalent
analog output voltages in proportion to the applied ref­erence voltages. Each DAC in the MAX509 has a sepa­rate reference input, while the two reference inputs in
the MAX510 each share a pair of DACs. The two refer­ence inputs permit different full-scale output voltage
ranges for each pair of DACs. A simplified diagram of
one of the four DACs is shown in Figure 8.

The MAX509/MAX510 can be used for multiplying
applications. The reference accepts both DC and AC
signals. The voltage at each REF input sets the full­scale output voltage for its respective DAC(s). If the ref­erence voltage is positive, both the MAX509 and
MAX510 can be operated from a single supply. If dual
supplies are used, the reference input can vary from
VSSto VDD, but is always referred to AGND. The input
impedance at REF is code dependent, with the lowest
value (16kΩ for the MAX509 and 8kΩ for the MAX510)
occurring when the input code is 55 hex or 0101 0101.
The maximum value, practically infinity, occurs when
the input code is 00 hex. Since the REF input imped­ance is code dependent, the DAC's reference sources
must have a low output impedance (no more than 32Ω
for the MAX509 and 16Ω for the MAX510) to maintain
output linearity. The REF input capacitance is also code

RR

Analog Section

DAC Operation

Reference Input

OUT_

2R

dependent: 15pF typical for the MAX509 and 30pF
typical for the MAX510.

The output voltage for any DAC can be represented by
a digitally programmable voltage source as:

VOUT = (NB x VREF) / 256

where NB is the numerical value of the DAC's binary
input code.

Output Buffer Amplifiers

All MAX509/MAX510 voltage outputs are internally
buffered by precision unity-gain followers that slew at
up to 1V/µs. The outputs can swing from VSSto VDD.
With a 0V to +4V (or +4V to 0V) output transition, the
amplifier outputs will settle to 1/2LSB in typically 6µs
when loaded with 10kΩ in parallel with 100pF.

The buffer amplifiers are stable with any combination of
resistive loads ≥ 2kΩ and capacitive loads ≤ 300pF.

__________Applications Information

The MAX509/MAX510 are fully specified to operate with

Reference Operating Ranges

VDD= 5V ±10% and VSS= 0V to -5.5V. 8-bit perfor­mance is guaranteed for both single- and dual-supply
operation. The zero-code output error is less than 14mV
when operating from a single +5V supply.

The DACs work well with reference voltages from V
to VDD. The reference voltage is referred to AGND.

The preferred power-up sequence is to apply VSSand
then VDD, but bringing up both supplies at the same
time is also acceptable. In either case, the voltage
applied to REF should not exceed VDDduring power­up or at any other time. If proper power sequencing is
not possible, connect an external Schottky diode
between VSSand AGND to ensure compliance with the

Absolute Maximum Ratings

the digital inputs before the device is fully powered up.

Power-Supply Bypassing

and Ground Management

In single-supply operation (AGND = DGND = VSS=
0V), AGND, DGND and VSSshould be connected
together in a "star" ground at the chip. This ground
should then return to the highest quality ground avail­able. Bypass VDDwith a 0.1µF capacitor, located as
close to VDDand DGND as possible. In dual-supply
operation, bypass VSSto AGND with 0.1µF.

Careful PC board layout minimizes crosstalk among
DAC outputs, reference inputs, and digital inputs.
Figures 9 and 10 show suggested circuit board layouts
to minimize crosstalk.

Power Supply and

SS

. Do not apply signals to

14 ______________________________________________________________________________________

OUTC
OUTD

REFC
REFD

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

MAX509/MAX510

SYSTEM GND

OUTB
OUTA

V

DD

V

SS

REFB
REFA
AGND

OUTC
OUTD

V

REFCD

DD

SYSTEM GND

OUTB
OUTA

V

SS

REFAB
AGND

Figure 9. Suggested MAX509 PC Board Layout for Minimizing
Crosstalk (Bottom View)

Unipolar-Output, 2-Quadrant Multiplication

In unipolar operation, the output voltages and the refer­ence input(s) are the same polarity. Figures 11 and 12
show the MAX509/MAX510 unipolar configurations.
Both devices can be operated from a single supply if
the reference inputs are positive. If dual supplies are
used, the reference input can vary from VSSto VDD.
Table 2 shows the unipolar code.

Table 2. Unipolar Code Table

DAC CONTENTS

MSB LSB

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0V

+V

ANALOG

OUTPUT

+V

REF

+V

REF

(––––)= +

REF

+V

REF

+V

REF

255

(––––)

256
129

(––––)

256

V

128
256 2

127

(––––)

256

1

(––––)

256

REF

–

–––

Figure 10. Suggested MAX510 PC Board Layout for Minimizing
Crosstalk (Bottom View)

Bipolar-Output, 2-Quadrant Multiplication

Bipolar-output, 2-quadrant multiplication is achieved by
offsetting AGND positively or negatively. Table 3 shows
the bipolar code.

AGND can be biased above DGND to provide an arbi­trary nonzero output voltage for a 0 input code, as
shown in Figure 13. The output voltage at OUTA is:

V

= V

OUTA

+ (NB/256)(VIN),

BIAS

Table 3. Bipolar Code Table

DAC CONTENTS

MSB LSB

1 1 1 1 1 1 1 1

1 0 0 0

1 0 0 0 0 0 0 0 0V

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

0 0 0 1

+V

+V

-V

-V

-V

REF

ANALOG

OUTPUT

127

(––––)

REF

128

(––––)

REF

128

1

(––––)

REF

128
127

(––––)

REF

128

128

(––––) = -V

128

1

REF

Note: 1LSB = (V

) (2-8) = +V

REF

______________________________________________________________________________________ 15

REF

1

(––––)

256

Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

REFCREFBREFA

DAC A

DAC B

DAC C

REFD

SS

16

TO VDD)

SERIAL

INTERFACE

NOT SHOWN

REFERENCE INPUTS (V

517418

MAX509/MAX510

DAC D

V

SS

3

MAX509

-5V (OR GND)

Figure 11. MAX509 Unipolar Output Circuit

SERIAL

INTERFACE

NOT SHOWN

MAX510

REFERENCE INPUTS (V

414

REFAB

DAC A

DAC B

DAC C

DAC D

REFCD

V

SS

3

-5V (OR GND)

Figure 12. MAX510 Unipolar Output Circuit

AGND

68

TO VDD)

SS

AGND

13

56

+5V

AGND

-5V (OR GND)

AGND

-5V (OR GND)

DAC A

V

DAC A

V

SS

SS

5
REFA

3

4
REFAB

3

V

DD

2

OUTA

V

IN

1

OUTB

V

BIAS

20

OUTC

19

OUTD

DGND

V

V

BIAS

+5V

V

DD

2

OUTA

SERIAL INTERFACE NOT SHOWN

Figure 13. MAX509/MAX510 AGND Bias Circuits (Positive
Offset)

6

IN

5

MAX509

MAX510

+5V

V

DGND

+5V

V

DGND

18

DD

2

OUTA

8

14

DD

2

OUTA

6

where NB represents the digital input word. Since

1

OUTB

AGND is common to all four DACs, all outputs will be
offset by V
more than +1V above DGND, or more than 2.5V below

in the same manner. Do not bias AGND

BIAS

DGND.

16

OUTC

Figures 14 and 15 illustrate the generation of negative
offsets with bipolar outputs. In these circuits, AGND is
biased negatively (up to -2.5V with respect to DGND) to
provide an arbitrary negative output voltage for a 0
input code. The output voltage at OUTA is:

15

OUTD

OUTA = -(R2/R1)(2.5V) + (NB/256)(2.5V)(R2/R1+1)

where NB represents the digital input word. Since

DGND

AGND is common to all four DACs, all outputs will be
offset by V
V

= 2.5V, shows the digital code vs. output voltage

REF

for Figure 14 and 15's circuits with R1 = R2. The

in the same manner. Table 3, with

BIAS

ICL7612 op amp is chosen because its common-mode
range extends to both supply rails.

16 ______________________________________________________________________________________

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

MAX509/MAX510

+5V

0.1µF

MAX873

+2.5V

SERIAL

INTERFACE

NOT SHOWN

R1

330k

0.1%

ICL7611A

R2

330k

0.1%

+5V

0.1µF

7

2

6

3

8

1

0.1µF

-5V

Figure 14. MAX509 AGND Bias Circuit (Negative Offset)

REFERENCE INPUTS

5174

0.1µF

DAC A

DAC B

DAC C

DAC D

V

SS

-5V

+5V

16

18

V

DD

0.1µF

MAX509

2

OUTA

1

OUTB

20

OUTC

19

OUTD

3

AGND

6

DGND

8

Each DAC output may be configured for 4-quadrant

4-Quadrant Multiplication

multiplication using Figure 16 and 17's circuit. One op
amp and two resistors are required per channel. With
R1 = R2:

V

= V

OUT

[2(NB/256)-1]

REF

where NB represents the digital word in DAC register A.
The recommended value for resistors R1 and R2 is

330kΩ (±0.1%). Table 3 shows the digital code vs. out­put voltage for Figure 16 and 17's circuit.

______________________________________________________________________________________ 17

Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

+5V

SERIAL

6

+2.5V

INTERFACE

NOT SHOWN

R1

330k

0.1%

ICL7611A

330k

0.1%

+5V

7

2

3

8

1

-5V

0.1µF

2

MAX873

4

MAX509/MAX510

Figure 15. MAX510 AGND Bias Circuit (Negative Offset)

TO VDD)

SS

16

DAC A

DAC B

DAC C

DAC D

V

SS

AGND DGND

3

SERIAL

INTERFACE

NOT SHOWN

REFERENCE INPUTS (V

517418

0.1µF

AGND OR -5V

REFERENCE INPUTS

4

13

+5V

14

V

DD

0.1µF

MAX510

2

R2

1

16

15

0.1µF

V

OUTA

OUTB

OUTC

OUTD

0.1µF

OUT

V

OUT

2

OUTA

1

OUTB

20

OUTC

19

OUTD

V

-5V

DAC A

DAC B

DAC C

DAC D

SS

3

0.1µF

AGND

5

R1

R1

ICL7612A*

DGND

6

+5V

ICL7612A*

+5V

-5V

0.1µF

R2

0.1µF

-5V

*CONNECT ICL7612A PIN 8 TO AGND

R2

0.1µF

6

0.1µF

0.1µF

+5V

V

DD

MAX509

6

8

Figure 16. MAX509 Bipolar Output Circuit

18 ______________________________________________________________________________________

REFERENCE INPUTS

414

SERIAL

INTERFACE

NOT SHOWN

0.1µF

AGND OR -5V

Figure 17. MAX510 Bipolar Output Circuit

13

DAC A

DAC B

DAC C

DAC D

V

SS AGND

3

Quad, Serial 8-Bit DACs

with Rail-to-Rail Outputs

MAX509/MAX510

+5V

V

DD

0.1µF

MAX510

2
OUTA

1
OUTB

16
OUTC

15
OUTD

DGND

5

6

ICL7612A*

ICL7612A*

+5V

R1

R2

-5V

+5V

R1

R2

-5V

*CONNECT ICL7612A PIN 8 TO AGND

0.1µF

0.1µF

0.1µF

0.1µF

V

OUT

V

OUT

__Functional Diagrams (continued)

CLR

DOUT LDAC

12-BIT

SHIFT

REGISTER

SR

CONTROL

CS DIN

DGND

INPUT
REG A

INPUT
REG B

INPUT
REG C

INPUT
REG D

V

SS

MAX509

V

DD

DAC

REG A

DAC

REG B

DAC

REG C

DAC

REG D

AGND

DECODE

CONTROL

SCLK REFC

______________________________________________________________________________________ 19

REFAREFB

OUTA

DAC A

OUTB

DAC B

OUTC

DAC C

OUTD

DAC D

REFD

____Pin Configurations (continued)

TOP VIEW

OUTB
OUTA

V

REFAB

AGND

DGND

LDAC

DOUT

SS

1
2
3

MAX510

4
5
6
7
8

DIP/Wide SO

OUTC

16

OUTD

15

V

14

DD

REFCD

13

CS

12

SCLK

11

DIN

10

CLR

9

Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

___________________Chip Topography_Ordering Information (continued)

PART TEMP. RANGE PIN-PACKAGE

MAX509AEPP -40°C to +85°C 20 Plastic DIP
MAX509BEPP -40°C to +85°C 20 Plastic DIP
MAX509AEWP -40°C to +85°C 20 Wide SO
MAX509BEWP -40°C to +85°C 20 Wide SO ±1 1/2
MAX509AEAP -40°C to +85°C 20 SSOP ±1
MAX509BEAP -40°C to +85°C 20 SSOP ±1 1/2
MAX509AMJP -55°C to +125°C 20 CERDIP** ±1
MAX509BMJP -55°C to +125°C 20 CERDIP** ±1 1/2
MAX510ACPE

0°C to +70°C

16 Plastic DIP ±1

TUE

(LSB)

±1
±1 1/2
±1

REFB

(REFAB)

REFA

(REFAB)

AGND

MAX510BCPE 0°C to +70°C 16 Plastic DIP ±1 1/2

MAX509/MAX510

MAX510ACWE 0°C to +70°C 16 Wide SO ±1
MAX510BCWE 0°C to +70°C 16 Wide SO ±1 1/2

DGND

MAX510AEPE -40°C to +85°C 16 Plastic DIP ±1
MAX510BEPE -40°C to +85°C 16 Plastic DIP ±1 1/2
MAX510AEWE -40°C to +85°C 16 Wide SO ±1
MAX510BEWE -40°C to +85°C 16 Wide SO ±1 1/2
MAX510AMJE -55°C to +125°C 16 CERDIP** ±1
MAX510BMJE -55°C to +125°C 16 CERDIP** ±1 1/2

NOTE: LABELS IN ( ) ARE FOR MAX510 ONLY.
TRANSISTOR COUNT: 2235;

SUBSTRATE CONNECTED TO VDD.

**Contact factory for availability and processing to MIL-STD-883.

________________________________________________________Package Information

e

HE

V

SS

OUTA

DOUTLDAC

DIM

MAX509/MAX510

OUTB

OUTC

CLR

0.128"

(3.25mm)

INCHES MILLIMETERS



A

A1

B
C
D
E
e
H
L

α

MIN

0.068

0.002

0.010

0.005

0.278

0.205

0.301

0.022
0˚

MAX

0.078

0.008

0.015

0.009

0.289

0.212



0.311

0.037
8˚

OUTD

DIN



V

DD

MIN

1.73

0.05

0.25

0.13

7.07

5.20

7.65

0.55

0.65 BSC0.0256 BSC



0˚

REFC
(REFCD)

REFD
(REFCD)

CS

(3.07mm)

SCLK

MAX

1.99

0.21

0.38

0.22

7.33

5.38


7.90

0.95

8˚

21-0003A

0.121"

D

α

A

0.127mm

A1

B

0.004in.

C

L

20-PIN PLASTIC

SHRINK

SMALL-OUTLINE

PACKAGE

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]

© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.