The MAX509/MAX510 are quad, serial-input, 8-bit voltage-output digital-to-analog converters (DACs). They
operate with a single +5V supply or dual ±5V supplies.
Internal, precision buffers swing rail-to-rail. The reference input range includes both supply rails.
The MAX509 has four separate reference inputs, allowing each DAC's full-scale range to be set independently.
20-pin DIP, SSOP, and SO packages are available. The
MAX510 is identical to the MAX509 except it has two reference inputs, each shared by two DACs. The MAX510
is housed in space-saving 16-pin DIP and SO packages.
The serial interface is double-buffered: A 12-bit input
shift register is followed by four 8-bit buffer registers and
four 8-bit DAC registers. A 12-bit serial word is used to
____________________________Features
♦ Single +5V or Dual ±5V Supply Operation
♦ Output Buffer Amplifiers Swing Rail-to-Rail
♦ Reference Input Range Includes Both Supply Rails
♦ Calibrated Offset, Gain, and Linearity (1LSB TUE)
♦ 10MHz Serial Interface, Compatible with SPI, QSPI
(CPOL = CPHA = 0) and Microwire
♦ Double-Buffered Registers for Synchronous
Updating
♦ Serial Data Output for Daisy-Chaining
♦ Power-On Reset Clears Serial Interface and Sets
All Registers to Zero
______________Ordering Information
load data into each register. Both input and DAC registers can be updated independently or simultaneously
with single software commands. Two additional asynchronous control pins provide simultaneous updating
(LDAC) or clearing (CLR) of input and DAC registers.
The interface is compatible with MicrowireTMand SPI/
QSPITM. All digital inputs and outputs are TTL/CMOS
compatible. A buffered data output provides for readback or daisy-chaining of serial devices.
_______________Functional Diagrams
CLR
DOUT
LDAC
12-BIT
SHIFT
REGISTER
SR
CONTROL
CS DIN
Functional Diagrams continued at end of data sheet.
Microwire is a trademark of National Semiconductor. SPI and QSPI are trademarks of Motorola.
DGND
INPUT
REG A
INPUT
REG B
INPUT
REG C
INPUT
REG D
V
SS
MAX509
V
DD
DAC
REG A
DAC
REG B
DAC
REG C
DAC
REG D
AGND
DECODE
CONTROL
SCLKREFC
REFAREFB
OUTA
DAC A
OUTB
DAC B
OUTC
DAC C
OUTD
DAC D
REFD
PARTTEMP. RANGE PIN-PACKAGE
MAX509ACPP
0°C to +70°C20 Plastic DIP
MAX509BCPP0°C to +70°C20 Plastic DIP
MAX509ACWP0°C to +70°C20 Wide SO
MAX509BCWP20 Wide SO±1 1/2
0°C to +70°C
MAX509ACAP0°C to +70°C20 SSOP±1
MAX509BCAP0°C to +70°C20 SSOP±1 1/2
MAX509BC/D0°C to +70°CDice*±1 1/2
Ordering Information continued on last page.
* Dice are specified at +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.
_________________Pin Configurations
TOP VIEW
OUTB
1
OUTA
2
V
SS
3
REFB
4
REFA
5
AGND
6
N.C.
7
DGND
8
LDAC
9
DOUT
10
Pin Configurations continued at end of data sheet.
Note: The outputs may be shorted to VDD, VSS, or AGND if the package power dissipation is not exceeded. Typical short-circuitcurrent
MAX509/MAX510
to AGND is 50mA. Do not bias AGND more than +1V above DGND, or more than 2.5V below DGND.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
A
- 0.3V), (VDD+ 0.3V)
SS
= +70°C)
DD
+ 0.3V)
, V
DD
SS
ELECTRICAL CHARACTERISTICS
(VDD= +5V ±10%, VSS= 0V to -5.5V, V
unless otherwise noted.)
(VDD= +5V ±10%, VSS= 0V to -5.5V, V
unless otherwise noted.)
PARAMETERCONDITIONSMINTYPMAX UNITS
POWER SUPPLIES
Positive Supply Voltage
Negative Supply Voltage-5.50VFor specified performanceV
Positive Supply Current
Negative Supply CurrentmAI
Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex.
Note 3: VREF = 4V
MAX509/MAX510
code of all other DACs to 00 hex.
Note 4: VREF = 4V
Note 5: Guaranteed by design.
Note 6: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
p-p
, 10kHz. DAC code = 00 hex.
p-p
TIMING CHARACTERISTICS
(VDD= +5V ±10%, VSS= 0V to -5V, V
PARAMETER
LDAC Pulse Width Low
CS Rise to LDAC Fall Setup Time
CLR Pulse Width Low
SERIAL INTERFACE TIMING
CS Fall to SCLK Setup Time
SCLK Fall to CS Rise Hold Time
SCLK Rise to CS Rise Hold Time
SCLK Fall to CS Fall Hold Time
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time0nst
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK to DOUT Valid
Note 7: Guaranteed by design.
Note 8: If LDAC is activated prior to CS's rising edge, it must stay low for t
Note 9: Minimum delay from 12th clock cycle to CS rise.