The MAX5098A is a dual-output, high-switching-frequency DC-DC converter with integrated n-channel switches
that can be used either in high-side or low-side configuration. Each output can be configured either as a buck converter or a boost converter. In the buck configuration, this
device delivers up to 2A from converter 1 and 1A from
converter 2. The MAX5098A also integrates a load-dump
protection circuitry that is capable of handling load-dump
transients up to 80V for automotive applications. The
load-dump protection circuit utilizes an internal chargepump to drive the gate of an external n-channel MOSFET.
When an overvoltage or load-dump condition occurs, the
series protection MOSFET absorbs the high voltage transient to prevent damage to lower voltage components.
The DC-DC converters operate over a wide operating
voltage range from 4.5V to 19V. The MAX5098A operates 180° out-of-phase with an adjustable switching frequency to minimize external components while allowing
the ability to make trade-offs between the size, efficiency,
and cost. The high switching frequency (up to 2.2MHz)
also allows this device to operate outside the AM band
for automotive applications.
This device utilizes voltage-mode control for stable operation and external compensation, thus the loop gain is
tailored to optimize component selection and transient
response. This device can be synchronized to an external clock fed at the SYNC input. Also, a clock output
(CKO) allows a master-slave connection of two devices
with a four-phase synchronized switching sequence.
Additional features include internal digital soft-start, individual enable for each DC-DC regulator (EN1 and EN2),
open-drain power-good outputs (PGOOD1 and
PGOOD2), and a shutdown input (ON/OFF).
Other features of the MAX5098A include overvoltage protection, short-circuit (hiccup current limit) and thermal
protection. The MAX5098A is available in a thermally
enhanced, exposed pad, 5mm x 5mm, 32-pin TQFN
package and is fully specified over the automotive
-40°C to +125°C temperature range.
Applications
Automotive AM/FM Radio Power Supply
Automotive Instrument Cluster Display
Features
o Wide 4.5V to 5.5V or 5.2V to 19V Input Voltage
Range (with Up to 80V Load-Dump Protection)
o Dual-Output DC-DC Converter with Integrated
Power MOSFETs
o Each Output Configurable in Buck or Boost Mode
o Adjustable Outputs from 0.8V to 0.85V
IN
Buck
Configuration) and from VINto 28V (Boost
Configuration)
= -40°C to +125°C, unless otherwise noted.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specifications. For detailed information
on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial
.
V+ to SGND............................................................-0.3V to +25V
V+ to IN_HIGH...........................................................-19V to +6V
IN_HIGH to SGND ..................................................-0.3V to +19V
IN_HIGH Maximum Input Current .......................................60mA
BYPASS to SGND..................................................-0.3V to +2.5V
GATE to V+.............................................................-0.3V to +12V
GATE to SGND .......................................................-0.3V to +36V
SGND to PGND_ ...................................................-0.3V to +0.3V
V
L
to SGND..................-0.3V to the Lower of +6V or (V+ + 0.3V)
VDRV to SGND .........................................................-0.3V to +6V
BST1/VDD1, BST2/VDD2, DRAIN_,
PGOOD_ to SGND ..............................................-0.3V to +30V
ON/OFF to SGND ...............................-0.3V to (IN_HIGH + 0.3V)
BST1/VDD1 to SOURCE1,
BST2/VDD2 to SOURCE2......................................-0.3V to +6V
SOURCE_ to SGND................................................-0.6V to +25V
SOURCE_ to PGND_.................................................-1V for 50ns
EN_ to SGND............................................................-0.3V to +6V
OSC, FSEL_1, COMP_, SYNC,
FB_ to SGND..............................................-0.3V to (V
L
+ 0.3V)
CKO to SGND..........................................-0.3V to (VDRV + 0.3V)
SOURCE1, DRAIN1 Peak Current ..............................5A for 1ms
SOURCE2, DRAIN2 Peak Current ..............................3A for 1ms
V
L
, BYPASS to
SGND Short Circuit ................... Continuous, Internally Limited
5EN2Converter 2 Active-High Enable Input. Connect to VL for always-on operation.
6FB2
7COMP2Converter 2 Internal Transconductance Amplifier Output. See the Compensation section.
8OSC
9SYNC
10GATE
11ON/OFF
Converter 2 Internal MOSFET Source Connection. For buck converter operation, connect SOURCE2 to the
switched side of the inductor. For boost operation, connect SOURCE2 to PGND_ (Figure 6).
Converter 2 Internal MOSFET Drain Connection. For buck converter operation, use the MOSFET as a highside switch and connect DRAIN2 to the DC-DC converters supply input rail. For boost converter operation,
use the MOSFET as a low-side switch and connect DRAIN2 to the inductor and diode junction (Figure 6).
92.5% of its set regulation voltage. Use PGOOD2 and EN1 to sequence the converters. Converter 2 starts
first.
Converter 2 Feedback Input. Connect FB2 to a resistive divider between converter 2’s output and SGND to
adjust the output voltage. To set the output voltage below 0.8V, connect FB2 to a resistive voltage-divider
from BYPASS to regulator 2’s output (Figure 3). See the Setting the Output Voltage section.
Oscillator Frequency Set Input. Connect a resistor from OSC to SGND (R
(see the Setting the Switching Frequency section). Set R
input frequency when using external synchronization. R
connected to the SYNC input. See the Synchronization (SYNC)/Clock Output (CKO) section.
External Clock Synchronization Input. Connect SYNC to a 400kHz to 4400kHz clock to synchronize the
switching frequency with the system clock. Each converter frequency is 1/2 of the frequency applied to
SYNC (FSEL_1 = V
SYNC frequency. Connect SYNC to SGND when not used.
Gate Drive Output. Connect to the gate of the external n-channel load-dump protection MOSFET. GATE =
IN_HIGH + 9V (typ) with IN_HIGH = 12V. GATE pulls to IN_HIGH by an internal n-channel MOSFET when V+
raises 2V above IN_HIGH. Leave gate unconnected if the load-dump protection is not used (MOSFET not
installed).
n-Channel Switch Enable Input. Drive ON/OFF high for normal operation. Drive ON/OFF low to turn off the
external n-channel load-dump protection MOSFET and reduce the supply current to 7µA (typ). When
ON/OFF is driven low, both DC-DC converters are disabled and the PGOOD_ outputs are driven low.
Connect to V+ if the external load-dump protection is not used (MOSFET not installed).
). For FSEL_1 = SGND, the switching frequency of converter 1 becomes 1/4 of the
L
for an oscillator frequency equal to the SYNC
OSC
is still required when an external clock is
OSC
) to set the switching frequency
OSC
12IN_HIGH
13V+
14V
15SGND
L
Startup Input. IN_HIGH is protected by internally clamping to 21V (max). Connect a resistor (4kΩ max) from
IN_HIGH to the drain of the protection switch. Bypass IN_HIGH with a 4.7µF electrolytic or 1µF minimum
ceramic capacitor. Connect to V+ if the external load-dump protection is not used (MOSFET not installed).
Input Supply Voltage. V+ can range from 5.2V to 19V. Connect V+, IN_HIGH, and V
5.5V input operation. Bypass V+ to SGND with a 1µF minimum ceramic capacitor.
Internal Regulator Output. The VL regulator is used to supply the drive current at input VDRV. When driving
VDRV, use an RC lowpass filter to decouple switching noise from VDRV to the V
Application Circuit). Bypass V
Signal Ground. Connect SGND to exposed pad and to the board signal ground plane. Connect the board
signal ground and power ground planes together at a single point.
to SGND with a 4.7µF minimum ceramic capacitor.
L
together for 4.5V to
L
regulator (see the Typical
L
MAX5098A
Dual, 2.2MHz, Automotive Buck or Boost
Converter with 80V Load-Dump Protection
16BYPASSReference Output Bypass Connection. Bypass to SGND with a 0.22µF or greater ceramic capacitor.
for normal operation. Connect FSEL_1 to SGND
L
17FSEL_1
18COMP1Converter 1 Internal Transconductance Amplifier Output. See the Compensation section.
19FB1
20EN1Converter 1 Active-High Enable Input. Connect to VL for an always-on operation.
21PGOOD1
22, 23DRAIN1
Converter 1 Frequency Select Input. Connect FSEL_1 to V
to reduce converter 1’s switching frequency to 1/2 of converter 2’s switching frequency (converter 1
switching frequency is 1/4 the CKO frequency). Do not leave FSEL_1 unconnected.
Converter 1 Feedback Input. Connect FB1 to a resistive divider between converter 1’s output and SGND to
adjust the output voltage. To set the output voltage below 0.8V, connect FB1 to a resistive voltage-divider
from BYPASS to regulator 1’s output (Figure 3). See the Setting the Output Voltage section.
Converter 1 Open-Drain Power-Good Output. PGOOD1 output goes low when converter 1’s output falls
below 92.5% of its set regulation voltage. Use PGOOD1 and EN2 to sequence the converters. Converter 1
starts first.
Converter 1 Internal MOSFET Drain Connection. For buck converter operation, use the MOSFET as a highside switch and connect DRAIN1 to the DC-DC converters supply input rail. For boost converter operation,
use the MOSFET as a low-side switch and connect DRAIN1 to the inductor and diode junction (Figure 6).
24, 25SOURCE1
26BST1/VDD1
27VDRV
28CKO
29, 30
31BST2/VDD2
—EP
PGND1,
PGND2
Converter 1 Internal MOSFET Source Connection. For buck operation, connect SOURCE1 to the switched
side of the inductor. For boost operation, connect SOURCE1 to PGND_ (Figure 6).
Converter 1 Bootstrap Flying-Capacitor Connection. For buck converter operation, connect BST1/VDD1 to a
0.1µF ceramic capacitor and diode according to the Typical Application Circuit. For boost converter
operation, driver bypass capacitor connection. Connect to VDRV and bypass with a 0.1µF ceramic
capacitor to PGND_ (Figure 6).
Low-Side Driver Supply Input. Connect VDRV to V
internal V
VDRV. For boost converter operation, connect VDRV to BST1/VDD1 and BST2/VDD2. Bypass with a
minimum 2.2µF ceramic capacitor to PGND_ (see the Typical Application Circuit). Do not connect to anexternal supply.
Clock Output. CKO is an output with twice the frequency of each converter (FSEL_1 = V
phase with respect to converter 1. Connect CKO to the SYNC input of another MAX5098A for a four-phase
converter.
Power Ground. Connect both PGND1 and PGND2 together and to the board power ground plane.
Converter 2 Bootstrap Flying-Capacitor Connection. For buck converter operation, connect BST2/VDD2 to a
0.1µF ceramic capacitor and diode according to the Typical Application Circuit. For boost converter
operation, driver bypass capacitor connection. Connect to VDRV and bypass with a 0.1µF ceramic
capacitor from BST2/VDD2 to PGND_ (Figure 6).
Exposed Pad. Connect EP to SGND. For enhanced thermal dissipation, connect EP to a copper area as
large as possible. Do not use EP as the sole ground connection.
regulator. For buck converter operation, connect anode terminals of external bootstrap diodes to
L
through an RC filter to bypass switching noise to the
The MAX5098A dual DC-DC converter uses a pulsewidth-modulation (PWM) voltage-mode control scheme.
On each converter the device includes one integrated
n-channel MOSFET switch and requires an external
low-forward-drop Schottky diode for output rectification. The controller generates the clock signal by dividing down the internal oscillator (f
CKO
) or the SYNC
input when driven by an external clock, therefore each
controller’s switching frequency equals half the oscillator frequency (fSW= f
CKO
/2) or half of the SYNC input
frequency (fSW= f
SYNC
/2). An internal transconductance error amplifier produces an integrated error voltage at COMP_, providing high DC accuracy. The
voltage at COMP_ sets the duty cycle using a PWM
comparator and a ramp generator. At each rising edge
of the clock, converter 1’s MOSFET switch turns on and
remains on until either the appropriate or maximum
duty cycle is reached, or the maximum current limit for
the switch is reached. Converter 2 operates 180° outof-phase, so its MOSFET switch turns on at each falling
edge of the clock.
In the case of buck operation (see the
Typical
Application Circuit
), the internal MOSFET is used in
high-side configuration. During each MOSFET’s ontime, the associated inductor current ramps up. During
the second half of the switching cycle, the high-side
MOSFET turns off and forward biases the Schottky rectifier. During this time, the SOURCE_ voltage is
clamped to a diode drop (VD) below ground. A low forward voltage drop (0.4V) Schottky diode must be used
to ensure the SOURCE_ voltage does not go below
-0.6V abs max. The inductor releases the stored energy
as its current ramps down, and provides current to the
output. The bootstrap capacitor is also recharged when
the SOURCE_ voltage goes low during the high-side
MOSFET off-time. The maximum duty-cycle limit
ensures proper bootstrap charging at startup or low
input voltages. The circuit goes in discontinuous conduction mode operation at light load, when the inductor
current completely discharges before the next cycle
commences. Under overload conditions, when the
inductor current exceeds the peak current limit of the
respective switch, the high-side MOSFET turns off
quickly and waits until the next clock cycle.
In the case of boost operation, the MOSFET is a lowside switch (Figure 6). During each on-time, the inductor current ramps up. During the second half of the
switching cycle, the low-side switch turns off and for-
ward biases the Schottky diode. During this time, the
DRAIN_ voltage is clamped to a diode drop (VD) above
V
OUT_
and the inductor provides energy to the output
as well as replenishes the output capacitor charge.
Load-Dump Protection
Most automotive applications are powered by a multicell, 12V lead-acid battery with a voltage from 9V to
16V (depending on load current, charging status, temperature, battery age, etc.). The battery voltage is distributed throughout the automobile and is locally
regulated down to voltages required by the different
system modules. Load dump occurs when the alternator is charging the battery and the battery becomes
disconnected. Power in the alternator inductance flows
into the distributed power system and elevates the voltage seen at each module. The voltage spikes have rise
times typically greater than 5ms and decays within several hundred milliseconds but can extend out to 1s or
more depending on the characteristics of the charging
system. These transients are capable of destroying
sensitive electronic equipment on the first fault event.
During load dump, the MAX5098A provides the ability
to clamp the input-voltage rail of the internal DC-DC
converters to a safe level, while preventing power discontinuity at the DC-DC converters’ outputs.
The load-dump protection circuit utilizes an internal
charge pump to drive the gate of an external n-channel
MOSFET. This series protection MOSFET absorbs the
load-dump overvoltage transient and operates in saturation over the normal battery range to minimize power
dissipation. During load dump, the gate voltage of the
protection MOSFET is regulated to prevent the source
terminal from exceeding 19V.
The DC-DC converters are powered from the source
terminal of the load-dump protection MOSFET, so that
their input voltage is limited during load-dump and can
operate normally.
ON/OFF
The MAX5098A provides an input (ON/OFF) to turn on
and off the external load-dump protection MOSFET.
Drive ON/OFF high for normal operation. Drive ON/OFF
low to turn off the external n-channel load-dump protection MOSFET and reduce the supply current to 7µA (typ).
When ON/OFF is driven low, the converter also turns off,
and the PGOOD_ outputs are driven low. V+ will be self
discharged through the converters output currents and
the IC supply current.
The internal oscillator generates the 180° out-of-phase
clock signal required by each regulator. The switching
frequency of each converter (f
SW
) is programmable
from 200kHz to 2.2MHz using a single 1% resistor at
R
OSC
. See the
Setting the Switching Frequency
section.
With dual synchronized out-of-phase operation, the
MAX5098A’s internal MOSFETs turn on 180° out-ofphase. The instantaneous input current peaks of both
regulators do not overlap, resulting in reduced RMS ripple current and input-voltage ripple. This reduces the
required input capacitor ripple current rating, allows for
fewer or less expensive capacitors, and reduces
shielding requirements for EMI.
Synchronization (SYNC)/
Clock Output (CKO)
The main oscillator can be synchronized to the system
clock by applying an external clock (f
SYNC
) at SYNC.
The f
SYNC
frequency must be twice the required operating frequency of an individual converter. Use a TTL
logic signal for the external clock with at least 100ns
pulse width. R
OSC
is still required when using external
synchronization. Program the internal oscillator frequency to have f
SW
= 1/2 f
SYNC.
The device is properly
synchronized if the SYNC frequency, f
SYNC
, varies
within ±20%.
Two MAX5098As can be connected in the master-slave
configuration for four ripple-phase operation (Figure 1).
The MAX5098A provides a clock output (CKO) that is
45° phase-shifted with respect to the internal switch
turn-on edge. Feed the CKO of the master to the SYNC
input of the slave. The effective input ripple switching
frequency is four times the individual converter’s switching frequency. When driving the master converter using
an external clock at SYNC, set the f
SYNC
clock duty
cycle to 50% for effective 90° phase-shifted interleaved
operation. When a SYNC is applied (and FSEL_1 = 0),
converter 1 duty cycle is limited to 75% (max).
Input Voltage (V+)/
Internal Linear Regulator (V
L
)
All internal control circuitry operates from an internally
regulated nominal voltage of 5.2V (VL). At higher input
voltages (V+) of 5.2V to 19V, VLis regulated to 5.2V. At
5.2V or below, the internal linear regulator operates in
dropout mode, where VLfollows V+. Depending on the
load on VL, the dropout voltage can be high enough to
reduce VLbelow the undervoltage lockout (UVLO)
threshold. Do not use VLto power external circuitry.
For input voltages less than 5.5V, connect V+ and V
L
together. The load on VLis proportional to the switching
frequency of converter 1 and converter 2. See the V
L
Output Voltage vs. Converter Switching Frequency
graph in the
Typical Operating Characteristics
. For
input voltage ranges higher than 5.5V, disconnect V
L
from V+.
Bypass V+ to SGND with a 1µF or greater ceramic
capacitor placed close to the MAX5098A. Bypass V
L
with a 4.7µF ceramic capacitor to SGND.
Undervoltage Lockout/
Soft-Start/Soft-Stop
The MAX5098A includes an undervoltage lockout with
hysteresis and a power-on-reset circuit for converter
turn-on and monotonic rise of the output voltage. The
falling UVLO threshold is internally set to 4.1V (typ) with
180mV hysteresis. Hysteresis at UVLO eliminates “chattering” during startup. When VLdrops below UVLO, the
internal MOSFET switches are turned off.
The MAX5098A digital soft-start reduces input inrush
currents and glitches at the input during turn-on. When
UVLO is cleared and EN_ is high, digital soft-start slowly ramps up the internal reference voltage in 64 steps.
The total soft-start period is 4096 internal oscillator
switching cycles.
Driving EN_ low initiates digital soft-stop that slowly
ramps down the internal reference voltage in 64 steps.
The total soft-stop period is equal to the soft-start period.
To calculate the soft-start/soft-stop period, use the following equation:
where f
CKO
is the internal oscillator and f
CKO
is twice
each converters’ switching frequency (FSEL_1 = VL)
Enable (EN1, EN2)
The MAX5098A dual converter provides separate
enable inputs, EN1 and EN2, to individually control or
sequence the output voltages. These active-high enable
inputs are TTL compatible. Driving EN_ high initiates
soft-start of the converter, and PGOOD_ goes logic-high
when the converter output voltage reaches the
V
TPGOOD_
threshold. Driving EN_ low initiates a softstop of the converter, and immediately forces PGOOD_
low. Use EN1, EN2, and PGOOD1 for sequencing (see
Figure 2). Connect PGOOD1 to EN2 to make sure converter 1’s output is within regulation before converter 2
starts. Add an RC network from VLto EN1 and EN2 to
delay the individual converter. Sequencing reduces
input inrush current and possible chattering. Connect
EN_ to VLfor always-on operation.
tms
()
SS
4096
=
fkHz
CKO
()
MAX5098A
Dual, 2.2MHz, Automotive Buck or Boost
Converter with 80V Load-Dump Protection
Converter 1 and converter 2 include a power-good flag,
PGOOD1 and PGOOD2, respectively. Since PGOOD_
is an open-drain output and can sink 3mA while providing the TTL logic-low signal, pull PGOOD_ to a logic
voltage to provide a logic-level output. PGOOD1 goes
low when converter 1’s feedback FB1 drops to 92.5%
(V
TPGOOD_
) of its nominal set point. The same is true for
converter 2. Connect PGOOD_ to SGND or leave
unconnected if not used.
Current Limit
The internal MOSFET switch current of each converter is
monitored during its on-time. When the peak switch current crosses the current-limit threshold of 3.45A (typ) and
2.1A (typ) for converter 1 and converter 2, respectively,
the on-cycle is terminated immediately and the inductor
is allowed to discharge. The MOSFET is turned on at the
next clock pulse, initiating a new switching cycle.
In deep overload or short-circuit conditions when the
V
FB_
voltage drops below 0.2V, the switching frequency is reduced to 1/4 x fSWto provide sufficient time for
the inductor to discharge. During overload conditions, if
the voltage across the inductor is not high enough to
allow for the inductor current to properly discharge,
current runaway may occur. Current runaway can
destroy the device in spite of internal thermal-overload
protection. Reducing the switching frequency during
overload conditions allows more time for inductor discharge and prevents current runaway.
Output Overvoltage Protection
The MAX5098A outputs are protected from output voltage overshoots due to input transients and shorting the
output to a high voltage. When the output voltage rises
above the overvoltage threshold, 110% (typ) nominal
FB_, the overvoltage condition is triggered. When the
overvoltage condition is triggered on either channel,
both converters are immediately turned off, 20Ω pull-
down switches from SOURCE_ to PGND_ are turned on
to help the output-voltage discharge, and the gate of
the load-dump protection external MOSFET is pulled
low. The device restarts as soon as both converter outputs discharge, bringing both FB_ input voltages below
12.5V of their nominal set points.
Thermal-Overload Protection
During continuous short circuit or overload at the output, the power dissipation in the IC can exceed its limit.
The MAX5098A provides thermal shutdown protection
with temperature hysteresis. Internal thermal shutdown
is provided to avoid irreversible damage to the device.
When the die temperature exceeds +165°C (typ), an
on-chip thermal sensor shuts down the device, forcing
the internal switches to turn off, allowing the IC to cool.
The thermal sensor turns the part on again with softstart after the junction temperature cools by +20°C.
During thermal shutdown, both regulators shut down,
PGOOD_ goes low, and soft-start resets. The internal
20V zener clamp from IN_HIGH to SGND is not turned
off during thermal shutdown because clamping action
must be always active.
Figure 2. Power-Supply Sequencing Configurations
V
IN
V
L
V
L
V
IN
VLV+
OUTPUT2OUTPUT1
V
L
SEQUENCING—OUTPUT 2 DELAYED WITH RESPECT TO OUTPUT 1.R1/C1 AND R2/C2 ARE SIZED FOR REQUIRED SEQUENCING.
DRAIN2
SOURCE2
MAX5098A
DRAIN1
SOURCE1
FB1FB2
EN1EN2
PGOOD1
V
L
OUTPUT2OUTPUT1
V
L
VLV+
DRAIN2
SOURCE2
MAX5098A
DRAIN1
SOURCE1
EN1EN2
FB1FB2
R1R2
V
L
C1C2
MAX5098A
Dual, 2.2MHz, Automotive Buck or Boost
Converter with 80V Load-Dump Protection
The controller generates the clock signal by dividing
down the internal oscillator f
OSC
or the SYNC input signal when driven by an external oscillator. The switching
frequency equals half the internal oscillator frequency
(fSW= f
OSC
/2). The internal oscillator frequency is set
by a resistor (R
OSC
) connected from OSC to SGND. To
find R
OSC
for each converter switching frequency fSW,
use the formulas:
A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is lost, the internal oscillator takes control of the switching rate,
returning the switching frequency to that set by R
OSC
.
When an external synchronization signal is used, R
OSC
must be selected such that fSW= 1/2 f
SYNC
. When
f
SYNC
clock signal is applied, f
CKO
equals f
SYNC
waveform, phase shifted by 180°. If the MAX5098A is running without external synchronization, f
CKO
equals the
internal oscillator frequency f
OSC
.
Buck Converter
Effective Input Voltage Range
Although the MAX5098A converter can operate from
input supplies ranging from 5.2V to 19V, the input voltage range can be effectively limited by the MAX5098A
duty-cycle limitations for a given output voltage. The
maximum input voltage is limited by the minimum ontime (t
ON(MIN)
):
where t
ON(MIN)
is 100ns. The minimum input voltage is
limited by the maximum duty cycle (D
MAX
= 0.82):
where V
DROP1
is the total parasitic voltage drops in the
inductor discharge path, which includes the forward
voltage drop (VD) of the rectifier, the series resistance
of the inductor, and the PCB resistance. V
DROP2
is the
total resistance in the charging path that includes the
on-resistance of the high-side switch, the series resistance of the inductor, and the PCB resistance.
Setting the Output Voltage
For 0.8V or greater output voltages, connect a voltagedivider from OUT_ to FB_ to SGND (Figure 3). Select R
B
(FB_ to SGND resistor) to between 1kΩ and 20kΩ.
Calculate RA(OUT_ to FB_ resistor) with the following
equation:
where V
FB_
= 0.8V (see the
Electrical Characteristics
table) and V
OUT_
can range from V
FB_
to 28V (boost
operation).
For output voltages below 0.8V, set the MAX5098A output voltage by connecting a voltage-divider from OUT_
to FB_ to BYPASS (Figure 3). Select RC(FB_ to BYPASS
resistor) in the 50kΩ range. Calculate RAwith the following equation:
Three key inductor parameters must be specified for
operation with the MAX5098A: inductance value (L),
peak inductor current (IL), and inductor saturation current (I
SAT
). The minimum required inductance is a function of operating frequency, input-to-output voltage
differential and the peak-to-peak inductor current (ΔIL).
A good compromise is to choose ΔILequal to 30% of
the full load current. To calculate the inductance, use
the following equation:
where VINand V
OUT
are typical values (so that efficiency is optimum for typical conditions). The switching frequency is set by R
OSC
(see the
Setting the Switching
Frequency
section). The peak-to-peak inductor current,
which reflects the peak-to-peak output ripple, is worse
at the maximum input voltage. See the
Output
Capacitor
section to verify that the worst-case output
ripple is acceptable. The inductor saturation current is
also important to avoid runaway current during output
overload and continuous short circuit. Select the I
SAT
to
be higher than the maximum peak current limits of 4.3A
and 2.6A for converter 1 and converter 2.
Input Capacitor
The discontinuous input current waveform of the buck
converter causes large ripple currents at the input. The
switching frequency, peak inductor current, and the
allowable peak-to-peak voltage ripple dictate the input
capacitance requirement. Note that the two converters
of the MAX5098A run 180° out-of-phase, thereby effectively doubling the switching frequency at the input.
The input ripple waveform would be unsymmetrical due
to the difference in load current and duty cycle
between converter 1 and converter 2. The worst-case
mismatch is when one converter is at full load while the
other converter is at no load or in shutdown. The input
ripple is comprised of ΔVQ(caused by the capacitor
discharge) and ΔV
ESR
(caused by the ESR of the
capacitor). Use ceramic capacitors with high ripplecurrent capability at the input, connected between
DRAIN_ and PGND_. Assume the contribution from the
ESR and capacitor discharge equal to 50%. Calculate
the input capacitance and ESR required for a specified
ripple using the following equations:
where
and
where
where I
OUT
is the maximum output current from either
converter 1 or converter 2, and D is the duty cycle for
that converter. The frequency of each individual converter is fSW. For example, at VIN= 12V, V
OUT
= 3.3V at
I
OUT
= 2A, and with L = 3.3µH, the ESR and input
capacitance are calculated for a peak-to-peak input ripple of 100mV or less, yielding an ESR and capacitance
value of 20mΩ and 6.8µF for 1.25MHz frequency. At low
input voltages, also add one electrolytic bulk capacitor
of at least 100µF on the converters’ input voltage rail.
This capacitor acts as an energy reservoir to avoid possible undershoot below the undervoltage lockout threshold during power-on and transient loading.
Output Capacitor
The allowable output ripple voltage and the maximum
deviation of the output voltage during step load currents determines the output capacitance and its ESR.
The output ripple is comprised of ΔVQ(caused by the
capacitor discharge) and ΔV
ESR
(caused by the ESR of
the capacitor). Use low-ESR ceramic or aluminum electrolytic capacitors at the output. For aluminum electrolytic capacitors, the entire output ripple is
contributed by ΔV
ESR
. Use the ESR
OUT
equation to calculate the ESR requirement and choose the capacitor
accordingly. If using ceramic capacitors, assume the
contribution to the output ripple voltage from the ESR
and the capacitor discharge are equal. Calculate the
output capacitance and ESR required for a specified
ripple using the following equations:
VVV
()
OUT INOUT
L
=
××−Δ
VfI
INSWL
ESR
V
Δ
ESR
=
IN
I
OUT
I
Δ
L
+
2
−
VVV
()
ΔI
INOUTOUT
=
L
Vf L
INSW
IDD
OUT
C
=
IN
Δ
D
=
×
××
−1
×
()
×
Vf
QSW
V
OUT
V
IN
ESR
OUT
=
C
OUT
Δ
V
ESR
=
Δ
I
L
Δ
I
L
××
Δ8
Vf
QSW
MAX5098A
Dual, 2.2MHz, Automotive Buck or Boost
Converter with 80V Load-Dump Protection
ΔILis the peak-to-peak inductor current as calculated
above and fSWis the individual converter’s switching
frequency.
The allowable deviation of the output voltage during
fast transient loads also determines the output capacitance and its ESR. The output capacitor supplies the
step load current until the controller responds with a
greater duty cycle. The response time (t
RESPONSE
)
depends on the closed-loop bandwidth of the converter. The high switching frequency of the MAX5098A
allows for higher closed-loop bandwidth, reducing
t
RESPONSE
and the output capacitance requirement.
The resistive drop across the output capacitor ESR and
the capacitor discharge causes a voltage droop during
a step load. Use a combination of low-ESR tantalum or
polymer and ceramic capacitors for better transient
load and ripple/noise performance. Keep the maximum
output voltage deviation within the tolerable limits of the
electronics being powered. When using a ceramic
capacitor, assume 80% and 20% contribution from the
output capacitance discharge and the ESR drop,
respectively. Use the following equations to calculate
the required ESR and capacitance value:
where I
STEP
is the load step and t
RESPONSE
is the
response time of the controller. Controller response
time depends on the control-loop bandwidth.
Boost Converter
The MAX5098A can be configured for step-up conversion since the internal MOSFET can be used as a lowside switch. Use the following equations to calculate
the values for the inductor (L
MIN
), input capacitor (CIN),
and output capacitor (C
OUT
) when using the converter
in boost operation.
Inductor
Choose the minimum inductor value so the converter
remains in continuous mode operation at minimum output current (I
OMIN
).
where
The V
D
is the forward voltage drop of the external
Schottky diode, D is the duty cycle, and VDSis the voltage drop across the internal MOSFET switch. Select
the inductor with low DC resistance and with a saturation current (I
SAT
) rating higher than the peak switch
current limit of 4.3A (I
CL1
) and 2.6A (I
CL2
) of converter
1 and converter 2, respectively.
Input Capacitor
The input current for the boost converter is continuous
and the RMS ripple current at the input is low. Calculate
the capacitor value and ESR of the input capacitor
using the following equations.
where
where VDSis the voltage drop across the internal
MOSFET switch. ΔILis the peak-to-peak inductor ripple
current as calculated above. ΔVQis the portion of input
ripple due to the capacitor discharge and ΔV
ESR
is the
contribution due to ESR of the capacitor.
Output Capacitor
For the boost converter, the output capacitor supplies
the load current when the main switch is ON. The
required output capacitance is high, especially at higher duty cycles. Also, the output capacitor ESR needs to
be low enough to minimize the voltage drop due to the
ESR while supporting the load current. Use the following equation to calculate the output capacitor for a
specified output ripple tolerance.
where I
PK
is the peak inductor current as defined in the
Power Dissipation
section for the boost converter, IOis
the load current, ΔVQis the portion of the ripple due to
The MAX5098A includes two internal power MOSFET
switches. The DC loss is a function of the RMS current in
the switch while the switching loss is a function of switching frequency and instantaneous switch voltage and current. Use the following equations to calculate the RMS
current, DC loss, and switching loss of each converter.
The MAX5098A is available in a thermally enhanced
package and can dissipate up to 2.7W at +70°C ambient
temperature. The total power dissipation in the package
must be limited so that the operating junction temperature does not exceed its absolute maximum rating of
+150°C at maximum ambient temperature.
For the buck converter:
where
See the
Electrical Characteristics
table for the
R
ON(MAX)
maximum value.
For the boost converter:
where V
DS
is the drop across the internal MOSFET and
η is the efficiency. See the
Electrical Characteristics
table for the R
ON(MAX)
value.
where t
R
and tFare rise and fall times of the internal
MOSFET. tFcan be measured in the actual application.
The supply current in the MAX5098A is dependent on
the switching frequency. See the
Typical Operating
Characteristics
to find the supply current of the
MAX5098A at a given operating frequency. The power
dissipation (P
S
) in the device due to supply current
(I
SUPPLY
) is calculated using following equation.
PS = V
INMAX
x I
SUPPLY
The total power dissipation PTin the device is:
PT = P
DC1
+ P
DC2
+ P
SW1
+ P
SW2
+ P
S
where P
DC1
and P
DC2
are DC losses in converter 1 and
converter 2, respectively. P
SW1
and P
SW2
are switching
losses in converter 1 and converter 2, respectively.
Calculate the temperature rise of the die using the following equation:
TJ = TCx (PT x θJC)
where θJCis the junction-to-case thermal impedance of
the package equal to +1.7°C/W. Solder the exposed
pad of the package to a large copper area to minimize
the case-to-ambient thermal impedance. Measure the
temperature of the copper area near the device at a
worst-case condition of power dissipation and use
+1.7°C/W as θJCthermal impedance.
Compensation
The MAX5098A provides an internal transconductance
amplifier with its inverting input and its output available
for external frequency compensation. The flexibility of
external compensation for each converter offers wide
selection of output filtering components, especially the
output capacitor. For cost-sensitive applications, use
aluminum electrolytic capacitors; for component sizesensitive applications, use low-ESR tantalum, polymer,
or ceramic capacitors at the output. The high switching
frequency of MAX5098A allows use of ceramic capacitors at the output.
Choose all the passive power components that meet
the output ripple, component size, and component cost
requirements. Choose the small-signal components for
the error amplifier to achieve the desired closed-loop
22
IIIII
RMSDCPKDCPK
⎛
=++×
⎝
PI R
=×
DCRMSDS ON MAX
II
II
VI tt f
INORFSW
=
SW
P
IIIII
RMS
22
=++×
DCPK
()
Δ
I
L
=×
PI R
DCRMSDS ON MAX
()
2
=
DCO
=+
PKO
×× +
I
=
IN
VV D
()
=
=
II
DCIN
=+
II
PKIN
2
()
Δ
I
L
−
2
Δ
I
L
2
()
4
()
DCPK
VI
×
OO
η
V
×
IN
×
−
INDS
×
Lf
SW
Δ
I
L
−
2
Δ
I
L
2
()( )
D
MAX
⎞
×
⎠
3
×
D
MAX
×
3
P
SW
VI tt f
×× +
OIN R F SW
=
()
4
×
MAX5098A
Dual, 2.2MHz, Automotive Buck or Boost
Converter with 80V Load-Dump Protection
bandwidth and phase margin. Use a simple pole-zero
pair (Type II) compensation if the output capacitor ESR
zero frequency is below the unity-gain crossover frequency (fC). Type III compensation is necessary when
the ESR zero frequency is higher than f
C
or when compensating for a continuous mode boost converter that
has a right-half-plane zero.
Use procedure 1 to calculate the compensation network components when f
ZERO,ESR
< fC.
Buck Converter Compensation
Procedure 1 (See Figure 4)
1) Calculate the f
ZERO,ESR
and LC double-pole fre-
quencies:
2) Select the unity-gain crossover frequency:
If the f
ZERO,ESR
is lower than fCand close to fLC, use a
Type II compensation network where RFCFprovides a
midband zero f
MID,ZERO
, and RFCCFprovides a high-
frequency pole.
3) Calculate modulator gain GMat the crossover frequency.
where V
OSC
is a peak-to-peak ramp amplitude equal to
1V.
The transconductance error amplifier gain is:
G
E/A
= gMx R
F
The total loop gain at fCshould be equal to 1:
GM x G
E/A
= 1
or
4) Place a zero at or below the LC double pole:
5) Place a high-frequency pole at f
P
= 0.5 x fSW.
Procedure 2 (See Figure 5)
If the output capacitor used is a low-ESR ceramic type,
the ESR frequency is usually far away from the targeted
unity crossover frequency (fC). In this case, Type III
compensation is recommended. Type III compensation
provides two-pole zero pairs. The locations of the zero
and poles should be such that the phase margin peaks
around f
C
. It is also important to place the two zeros at
or below the double pole to avoid the conditional stability issue.
4) Calculate CIfor a target unity crossover frequency, fC.
5) Place a pole
or 5 x f
C
, whichever
is lower,
6) Place a second zero, fZ2, at 0.2 x fCor at fLC,
whichever is lower.
7) Place a second pole at 1/2 the switching frequency.
Boost Converter Compensation
The boost converter compensation gets complicated
due to the presence of a right-half-plane zero
f
ZERO,RHP
. The right-half-plane zero causes a drop in
phase while adding positive (+1) slope to the gain
curve. It is important to drop the gain significantly below
unity before the RHP frequency. Use the following procedure to calculate the compensation components:
1) Calculate the LC double-pole frequency, f
LC
, and
the right-half-plane-zero frequency.
where
Figure 5. Type III Compensation Network
Figure 6. Boost Application
f
Z
2
××
π
1
RC
FF
atf
..
075=
×
LC1
1
×××
fR
LCF
C
=
F
2075π.
fLCV
×× ××
2π
C
=
I
COUTOUTOSC
VR
×
INF
2=××π
1
fC
××
π
PI
1
1
RC
II
at f
f
P
R
=
I
2
ZERO ESR1
,
R
1
=
fC
××
π
2
ZI
1
2
R
−
I
C
C
=
CF
×× ××
()
V
OUT
F
fRC
SWFF
C
CF
−2051π.
V
L
MAX5098A
VDRV
BST_/VDD_
PGND_
PGND_
DRAIN_
DRAIN_
SOURCE_
SOURCE_
SGND
FB_
V+
V
OUT_
C
OUT
−1
f
LC
=
2π
××
D
LC
OUTOUT
R
I
R1
C
I
R2
FB_
V
REF
C
R
F
-
g
M
+
F
COMP_
f
ZERO RHP
,
D
R
MIN
()
=
DR
−
1
()
=
1
=
×
22π
V
IN
−
V
OUT
V
OUT
I
OUT MAX
()
L
OUT
MIN
()
MAX5098A
Dual, 2.2MHz, Automotive Buck or Boost
Converter with 80V Load-Dump Protection
3) Calculate CIfor a target crossover frequency, fC:
where ω
C
= 2π x fC:
4) Place a pole
5) Place the second zero
where
6) Place the second pole
the switching frequency.
Load-Dump Protection MOSFET
Select the external MOSFET with an adequate voltage
rating, V
DSS
, to withstand the maximum expected loaddump input voltage. The on-resistance of the MOSFET,
R
DS(ON)
, should be low enough to maintain a minimal
voltage drop at full load, limiting the power dissipation
of the MOSFET.
During regular operation, the power dissipated by the
MOSFET is:
P
NORMAL
= I
LOAD
2
x R
DS(ON)
where I
LOAD
is equal to the sum of both converters’
input currents.
The MOSFET operates in a saturation region during
load dump, with both high voltage and current applied.
Choose a suitable power MOSFET that can safely operate in the saturation region. Verify its capability to support the downstream DC-DC converters input current
during the load-dump event by checking its safe operating area (SOA) characteristics. Since the transient
peak power dissipation on the MOSFET can be very
high during the load-dump event, also refer to the thermal impedance graph given in the data sheet of the
power MOSFET to make sure its transient power dissipation is kept within the recommended limits.
Improving Noise Immunity
In applications where the MAX5098A is subject to noisy
environments, adjust the controller’s compensation to
improve the system’s noise immunity. In particular, highfrequency noise coupled into the feedback loop causes
jittery duty cycles. One solution is to lower the crossover
frequency (see the
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. This is especially
true for dual converters where one channel can affect
the other. Refer to the MAX5099 Evaluation Kit data
sheet for a specific layout example. Use a multilayer
board whenever possible for better noise immunity.
Follow these guidelines for good PCB layout:
1) For SGND, use a large copper plane under the IC
and solder it to the exposed paddle. To effectively
use this copper area as a heat exchanger between
the PCB and ambient, expose this copper area on
the top and bottom side of the PCB. Do not make a
direct connection from the exposed pad copper
plane to SGND underneath the IC.
2) Isolate the power components and high-current
path from the sensitive analog circuitry.
3) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
4) Connect SGND and PGND_ together at a single
point. Do not connect them together anywhere else
(refer to the MAX5099 Evaluation Kit data sheet for
more information).
5) Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PCBs (2oz vs. 1oz) to enhance fullload efficiency.
6) Ensure that the feedback connection to C
OUT
is
short and direct.
7) Route high-speed switching nodes (BST_/VDD_,
SOURCE_) away from the sensitive analog areas
(BYPASS, COMP_, and FB_). Use the internal PCB
layer for SGND as an EMI shield to keep radiated
noise away from the IC, feedback dividers, and
analog bypass capacitors.
Layout Procedure
1) Place the power components first, with ground terminals adjacent (inductor, C
IN_
, and C
OUT_
). Make
all these connections on the top layer with wide,
copper-filled areas (2oz copper recommended).
2) Group the gate-drive components (bootstrap
diodes and capacitors, and VLbypass capacitor)
together near the controller IC.
3) Make the DC-DC controller ground connections as
follows:
a) Create a small, signal ground plane underneath
the IC.
b) Connect this plane to SGND and use this plane
for the ground connection for the reference
(BYPASS), enable, compensation components,
feedback dividers, and OSC resistor.
c) Connect SGND and PGND_ together (this is the
only connection between SGND and PGND_).
Refer to the MAX5099 Evaluation Kit data sheet
for more information.
MAX5098A
Dual, 2.2MHz, Automotive Buck or Boost
Converter with 80V Load-Dump Protection
Dual, 2.2MHz, Automotive Buck or Boost
Converter with 80V Load-Dump Protection
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28
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