General Description
The MAX5092A/MAX5092B/MAX5093A/MAX5093B lowquiescent-current, low-dropout (LDO) regulators contain
simple boost preregulators operating at a high frequency.
The devices seamlessly provide a preset 3.3V
(MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B)
LDO output voltage from an automotive cold-crank
through load-dump (3.5V to 80V) input voltage conditions. The MAX5092_/MAX5093_ deliver up to 250mA
with excellent load and line regulation. During normal
operation, when the battery is healthy, the boost preregulator is completely turned off, reducing quiescent current
to 65µA (typ). This makes the devices suitable for
always-on power supplies.
The buck-boost operation achieved by this combination
of LDO and boost preregulator offers the advantage of
using a single off-the-shelf inductor in place of the multiple-winding custom magnetics needed in typical single-ended primary inductor converter (SEPIC) and
transformer-based flyback topologies. The high operating frequency of the boost regulator significantly
reduces component size. The MAX5092_ integrates a
blocking diode to further reduce the external component count. The boost preregulator output voltage is
preset to 7V. Both LDO and boost output voltages are
programmable using external resistors. The boost preregulator output voltage is adjustable up to 11V
(MAX5092_), or up to 12V (MAX5093_). The LDO output
voltage is adjustable from 1.5V to 9V (MAX5092_) or
from 1.5V to 10V (MAX5093_).
The devices feature a shutdown mode with 5µA (typ)
shutdown current, a HOLD input to implement a self-holding circuit, and a power-on-reset output (RESET) with an
externally programmable timeout period. Additional features include output overload, short-circuit, and thermal
protection.
The MAX5092_/MAX5093_ are available in a thermally
enhanced, 16-pin 5mm x 5mm thin QFN package and can
dissipate up to 2.7W at +70°C on a multilayer PC board.
Applications
Automotive—Body Electronics
Automotive—ECU
Industrial
Features
♦ Wide Operating Input Voltage Range: 3.5V to 72V
with a 4V Startup Voltage
♦ LDO Output Regulates to 5V Seamlessly from an
Input Voltage of 3.5V to 72V
♦ Up to 250mA Output Current
♦ Preset 3.3V, 5V, or Externally Programmable LDO
Output Voltage from 1.5V to 9V (MAX5092_) or
from 1.5V to 10V (MAX5093_)
♦ Preset 7V or Externally Programmable Boost
Output Voltage Up to 11V (MAX5092_) or Up to
12V (MAX5093_)
♦ 65µA Quiescent Current in LDO Mode (VIN≥8V)
♦ 5µA Shutdown Current
♦ Power-On Reset (RESET) with Programmable
Timeout Period
♦ Output Short-Circuit and Thermal Protection
♦ TQFN Package Capable of Dissipating Up to 2.7W
at +70°C
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
________________________________________________________________
Maxim Integrated Products
1
Pin Configuration
Ordering Information
19-0659; Rev 0; 10/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+
Denotes lead-free package.
*
Future product—contact factory for availability.
**
EP = Exposed pad.
Typical Operating Circuit and Selector Guide appear at end
of data sheet.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE
MAX5092AATE+* -40°C to +125°C 16 TQFN-EP** T1655-3
MAX5092BATE+ -40°C to +125°C 16 TQFN-EP** T1655-3
MAX5093AATE+* -40°C to +125°C 16 TQFN-EP** T1655-3
MAX5093BATE+ -40°C to +125°C 16 TQFN-EP** T1655-3
PINPACKAGE
PKG
CODE
TOP VIEW
BSFB
13
LX
PGND_BST
12 11 9
10
BSOUT
OUT
8
RESET
14
VL
CT
15
16
MAX5092_/
MAX5093_
1+2
IN
(5mm x 5mm)
3
EN
SGND LX
THIN QFN
7
6
5
4
HOLD
OUT_SENSE
SET
PGND_LDO
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN= VEN= 14V, I
OUT
= 1mA, CIN= 47µF, C
BSOUT
= 22µF, C
OUT
= 10µF, CVL= 1µF, TA= TJ= -40°C to +125°C, unless otherwise
noted. See Figures 4–7 as applicable. Typical specifications are at T
A
= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: As per JEDEC Standard 51 (Multilayer Board).
IN, EN, LX, BSOUT to SGND..................................-0.3V to +80V
PGND_BST, PGND_LDO to SGND .......................-0.3V to +0.3V
VL, RESET, OUT, OUT_SENSE to SGND ...............-0.3V to +12V
BSOUT to LX (MAX5092_)......................................-0.3V to +12V
SET, BSFB, CT to SGND ..........................................-0.3V to +6V
HOLD to SGND….....................................-0.3V to (V
OUT
+ 0.3V)
OUT Current (I
OUT
) Short Circuit to PGND_LDO,
(V
IN
≤ 28V) ..............................................................Continuous
RESET Sinking Current .........................................................5mA
Continuous Power Dissipation (T
A
= +70°C)
16-Pin Thin QFN (derate 33.3mW/°C
above +70°C)...............................................2666mW (Note 1)
Operating Temperature Range .........................-40°C to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INPUT SUPPLY
Input Voltage Range V
Internal Input Undervoltage
Lockout
Supply Current (Boost Converter
Off)
Supply Current (Boost Converter
On)
Shutdown Supply Current I
BOOST CONVERTER
Minimum BSOUT Output Current I
Boost Converter Disable
Threshold
Boost Converter Disable
Threshold Hysteresis
BSOUT Output Voltage V
Maximum BSOUT Output Voltage V
BSFB Regulation Voltage V
BSFB Input Bias Current I
Boost Internal Switch
On-Resistance
Boost Internal Switch Minimum
Off-Time
IN
V
UVLOF
V
UVLOR
I
Q
I
S
SHDN
BSOUT
V
BST_DIS
BSOUT
BSOUT(MAX
BSFB
BSFB
R
DS(ON)
t
OFF
(Note 3) 4 72 V
VIN falling 3.0 3.2 3.4
VIN rising 3.4 3.6 3.8
LDO mode,
= 100µA
I
OUT
LDO mode, I
VIN = 5V 0.4 1.0 mA
VEN ≤ +0.4V
VIN = 4V 250 mA
VIN rising 7.5 8.0 8.5 V
VIN = 4V, BSFB = SGND 6.65 7.00 7.35 V
MAX5092_ 11
MAX5093_ 12
T
= -40°C to +125°C
J
(Note 4)
= 250mA 70 100
OUT
= -40°C to +125°C
T
J
(Note 4)
65 85
610µA
0.5 V
1.18 1.24 1.30 V
100 nA
0.5 1.2 Ω
0.80 1 1.25 µs
V
µA
V
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VIN= VEN= 14V, I
OUT
= 1mA, CIN= 47µF, C
BSOUT
= 22µF, C
OUT
= 10µF, CVL= 1µF, TA= TJ= -40°C to +125°C, unless otherwise
noted. See Figures 4–7 as applicable. Typical specifications are at T
A
= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Boost Internal Switch Maximum
On-Time
Internal Switch Current Limit I
Boost Turn-On Response Time
Internal Diode Forward Voltage
Drop
LDO
Guaranteed Output Current I
Output Voltage V
Minimum Adjustable Output
Voltage
Maximum Adjustable Output
Voltage
Adjustable Output Voltage V
Dropout Voltage ∆V
LDO Startup Response Time
Line Regulation
SET Reference Voltage V
SET Input Bias Current I
Load Regulation
Power-Supply Rejection Ratio PSRR
Short-Circuit Current I
t
ON-MAX
LIM
V
F
OUT
OUT
V
ADJMIN
V
ADJMAX
ADJ
DOIOUT
∆V
OUT
∆V
IN
SET
SET
∆V
OUT
∆I
OUT
SC
Measured in steady-state condition 1.5 3.0 A
Time from V
BSOUT
to switch on-time
MAX5092_ only, IF = 1A 0.95 V
V
- V
BSOUT
= 2V (Note 5) 250 mA
OUT
SET = SGND,
MAX5092A/
MAX5093A
SET = SGND,
MAX5092B/
MAX5093B
Boost operation, VIN = 4V, V
Boost operation,
V
= 4V
IN
LDO operation, VIN ≥ V
(boost converter off) (Note 6)
= 250mA (Note 7) 0.9 1.6 V
Rising edge of V
V
OUT
7V ≤ VIN ≤ 72V,
/
I
LOAD
7V ≤ VIN ≤ 28V, I
/
I
= 1mA to 250mA 0.2 0.6 mV/mA
OUT
, RL = 500Ω, SET = SGND
= 10mA
BSOUT
LOAD
f = 100Hz
f = 1MHz
1.80 2.25 2.70 µs
falling below regulation
I
= 1mA 3.25 3.3 3.35
OUT
100µA ≤ I
I
= 1mA 4.900 5 5.075
OUT
100µA ≤ I
≤ 250mA 3.2 3.3 3.4
OUT
≤ 250mA 4.85 5 5.10
OUT
= 7V 1.5 V
BSOUT
MAX5092_,
V
BSOUT
= 11V
MAX5093_,
V
BSOUT
BST_DIS
= 12V
1.5 10.0 V
to the rising edge of
25µs
V
9
V
10
200 µs
MAX5092A/MAX5093A 0.4
MAX5092B/MAX5093B 0.5
mV/V
= 250mA 1.6
1.205 1.235 1.265 V
0.5 100 nA
I
= 10mA, V
OUT
= 500mV
I
= 10mA, V
OUT
= 500mV
P-P
P-P
BSOUT(AC)
, V
OUT
BSOUT(AC)
, V
OUT
= 5V
= 5V
80
dB
60
255 490 mA
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN= VEN= 14V, I
OUT
= 1mA, CIN= 47µF, C
BSOUT
= 22µF, C
OUT
= 10µF, CVL= 1µF, TA= TJ= -40°C to +125°C, unless otherwise
noted. See Figures 4–7 as applicable. Typical specifications are at T
A
= +25°C.) (Note 2)
Note 2: Limits at -40°C are guaranteed by design and characterization; not production tested.
Note 3: Guaranteed minimum operating voltage is 3.5V on V
IN
falling only.
Note 4: Guaranteed by design and not production tested.
Note 5: The continuous maximum output current from the LDO is guaranteed according to the maximum power dissipation imposed
by the package thermal constraints.
Note 6: Maximum output adjustable value is conditioned by the maximum adjustable BSOUT Output Voltage Range minus the maxi-
mum dropout across the pass transistor.
Note 7: Dropout voltage is defined as (V
BSOUT
- V
OUT
) when V
OUT
is 2% below the value of V
OUT
for V
BSOUT
= V
OUT
+ 2V.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ENABLE, HOLD and RESET
EN High Input Threshold EN
EN Low Input Threshold EN
EN Input Bias Current I
HOLD Low Input Threshold V
HOLD Release Voltage V
HOLD Pullup Current I
RESET Voltage Threshold V
RESET Threshold Hysteresis V
RESET Output Low Voltage V
RESET Output High Leakage
Current
RESET Output Minimum Timeout
Period
EN to RESET Minimum Timeout
Delay
Delay Comparator Threshold
(Rising)
Delay Comparator Threshold
Hysteresis
CT Charge Current I
CT Discharge Current I
EN
IL
IH
HOLD
RESET
RHYST
RL
I
RH
V
CTTH
V
CTTH-HYS
CT-CHG
CT-DIS
H
L
2.4 V
0.25 2 µA
Regulator on, EN transition from high to low 0.4 V
V
-
EN = low
OUT
0.4
Internally connected to OUT 4 µA
% of V
% of V
I
SINK
V
R E SE T
C
CT
C
CT
, V
OUT
OUT
falling 87 90 92 %
OUT
2%
= 1mA 0.4 V
= 5V 1 µA
not connected 25 µs
not connected 260 µs
1.205 1.24 1.265 V
100 mV
1.5 2 2.5 µA
5mA
0.4 V
V
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
_______________________________________________________________________________________
5
Typical Operating Characteristics
(VIN= VEN= 14V, CIN= 47µF, C
BSOUT
= 22µF, C
OUT
= 10µF, CVL= 1µF, TA= +25°C, unless otherwise noted.) (See Figures 4–7 as
applicable.)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5092B)
MAX5092/93 toc07
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (µA)
11085603510-15
4
6
8
10
2
-40 135
V
EN
= 0V
LINE-TRANSIENT RESPONSE
(V
IN
STEP FROM 4V TO 7V)
MAX5092/93 toc08
200µs/div
V
OUT
50mV/div
V
IN
1V/div
V
BSOUT
1V/div
5V (AC-COUPLED)
7V
4V
7V (AC-COUPLED)
I
OUT
= 250mA
QUIESCENT SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5092B)
90
85
80
75
70
65
60
QUIESCENT SUPPLY CURRENT (µA)
55
50
872
I
OUT
BOOST CONVERTER NOT SWITCHING,
QUIESCENT SUPPLY CURRENT = I
INPUT VOLTAGE (V)
= 10mA
I
OUT
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE (MAX5093B)
100
BOOST CONVERTER NOT SWITCHING,
QUIESCENT SUPPLY CURRENT = I
90
80
70
60
QUIESCENT SUPPLY CURRENT (µA)
50
40
-40 135
I
= 10mA
OUT
TEMPERATURE (°C)
I
= 100µA
IN
= 100µA
OUT
IN
- I
OUT
11085603510-15
- I
OUT
645616 24 32 40 48
100
MAX5092/93 toc01
INPUT CURRENT (mA)
0.1
MAX5092/93 toc04
SHUTDOWN SUPPLY CURRENT (µA)
INPUT CURRENT (IIN)
vs. INPUT VOLTAGE (MAX5092B)
I
= 10mA
OUT
10
I
= 100µA
1
BOOST CONVERTER SWITCHING
4.0 7.0
OUT
INPUT VOLTAGE (V)
MAX5092/93 toc02
QUIESCENT SUPPLY CURRENT (µA)
6.56.05.55.04.5
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5092B)
10
8
6
4
2
0
474
INPUT VOLTAGE (V)
V
MAX5092/93 toc05
SHUTDOWN SUPPLY CURRENT (µA)
= 0V
EN
645444342414
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE (MAX5092B)
100
BOOST CONVERTER NOT SWITCHING,
QUIESCENT SUPPLY CURRENT = I
90
80
70
60
50
40
-40 135
TEMPERATURE (°C)
I
OUT
= 10mA
I
OUT
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5093B)
10
8
6
4
2
0
474
INPUT VOLTAGE (V)
- I
IN
= 100µA
V
OUT
11085603510-15
EN
MAX5092/93 toc03
MAX5092/93 toc06
= 0V
645444342414
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VIN= VEN= 14V, CIN= 47µF, C
BSOUT
= 22µF, C
OUT
= 10µF, CVL= 1µF, TA= +25°C, unless otherwise noted.) (See Figures 4–7 as
applicable.)
LINE-TRANSIENT RESPONSE
(V
IN
STEP FROM 3.5V TO 72V)
MAX5092/93 toc09
40ms/div
V
IN
50V/div
V
OUT
50mV/div
V
BSOUT
50V/div
72V
3.5V
5V (AC-COUPLED)
72V
7V
I
OUT
= 5mA
LINE-TRANSIENT RESPONSE
(V
IN
STEP FROM 3.5V TO 14V)
MAX5092/93 toc10
200µs/div
V
OUT
100mV/div
V
BSOUT
5V/div
V
IN
5V/div
14V
14V
7V
5V (AC-COUPLED)
3.5V
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX5092/93 toc14
FREQUENCY (Hz)
100k10k1k
-70
0
100 1M
VIN = 8V, I
OUT
= 10mA
PSRR (dB)
10dB/div
STARTUP THROUGH INPUT VOLTAGE
MAX5092/93 toc15
100µs/div
0V
V
IN
10V/div
V
BSOUT
10V/div
I
LX
5A/div
V
OUT
5V/div
0V
0A
0V
I
OUT
= 250mA
DROPOUT VOLTAGE (V
BSOUT
- V
OUT
)
vs. LDO LOAD CURRENT
MAX5092/93 toc11
LDO LOAD CURRENT (mA)
DROPOUT VOLTAGE (mV)
20015010050
200
400
600
800
1000
0
0 250
LDO OUTPUT VOLTAGE
vs. LDO LOAD CURRENT (MAX5092B)
MAX5092/93 toc12
LDO LOAD CURRENT (mA)
LDO OUTPUT VOLTAGE (V)
200100
4.90
4.95
5.00
5.05
5.10
5.15
4.85
0 300
TA = -40°C: CIN = 10µF, C
BSOUT
= 4.7µF, C
OUT
= 10µF
(CERAMIC)
TA = +25°C, +135°C: CIN = 47µF, C
BSOUT
= 22µF
(ELECTROLYTIC), C
OUT
= 10µF (CERAMIC)
TA = +25°C, VIN = 4V
T
A
= +25°C, VIN = 14V
TA = -40°C, VIN = 4V
T
A
= -40°C, VIN = 14V
TA = +135°C, VIN = 4V
T
A
= +135°C, VIN = 14V
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX5092/93 toc13
FREQUENCY (Hz)
100k10k1k
-70
0
10dB/div
100 1M
VIN = 14V, I
OUT
= 10mA
PSRR (dB)
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(VIN= VEN= 14V, CIN= 47µF, C
BSOUT
= 22µF, C
OUT
= 10µF, CVL= 1µF, TA= +25°C, unless otherwise noted.) (See Figures 4–7 as
applicable.)
_______________________________________________________________________________________
7
SHUTDOWN THROUGH V
V
IN
10V/div
V
BSOUT
10V/div
I
LX
1A/div
V
OUT
5V/div
2ms/div
SHUTDOWN THROUGH ENABLE
V
IN
10V/div
V
BSOUT
10V/div
V
OUT
5V/div
V
EN
2V/div
200µs/div
IN
MAX5092/93 toc16
I
= 250mA
OUT
MAX5092/93 toc18
I
= 250mA
OUT
0V
0V
0A
0V
14V
14V
0V
0V
V
10V/div
V
BSOUT
10V/div
V
OUT
5V/div
V
2V/div
V
2V/div
V
RESET
2V/div
2V/div
OUT
V
STARTUP THROUGH ENABLE
IN
EN
200µs/div
RESET TIMING RESPONSE
EN
200µs/div
I
OUT
I
OUT
C
T
MAX5092/93 toc17
= 250mA
MAX5092/93 toc19
= 250mA
= 680pF
14V
14V
0V
0V
0V
0V
0V
V
vs. TEMPERATURE
3.36
3.34
3.32
(V)
3.30
OUT
V
3.28
3.26
3.24
-40 135
OUT
I
= 10mA, R5 = 100kΩ,
OUT
R4 = 165kΩ, FIGURE 6
TEMPERATURE (°C)
V
vs. TEMPERATURE
OUT
(MAX5092B)
5.10
MAX5092/93 toc20
11085603510-15
5.05
(V)
5.00
OUT
V
4.95
I
= 1mA, V
4.90
-40 135
OUT
TEMPERATURE (°C)
MAX5092/93 toc21
= 0V
SET
11085603510-15
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VIN= VEN= 14V, CIN= 47µF, C
BSOUT
= 22µF, C
OUT
= 10µF, CVL= 1µF, TA= +25°C, unless otherwise noted.) (See Figures 4–7 as
applicable.)
LDO LOAD-TRANSIENT RESPONSE
(MAX5092B)
V
OUT
50mV/div
I
OUT
100mA/div
2ms/div
MAX5092/93 toc22
(AC-COUPLED)
0mA
V
OUT
20mV/div
20V/div
INPUT-VOLTAGE STEP RESPONSE
V
IN
200ms/div
MAX5092/93 toc23
I
= 5mA
OUT
5V (AC-COUPLED)
72V
3.5V
ENABLE AND HOLD TIMING
V
EN
5V/div
V
HOLD
5V/div
V
OUT
5V/div
BOOST CONVERTER POWER LOSS
= 7V)
(V
1.0
TA = +105°C: VIN = 3.5V
0.8
V
V
0.6
0.4
POWER LOSS (W)
0.2
0
0 350
BSOUT
= 4V
IN
= 5V
IN
TA = +25°C: VIN = 3.5V
V
V
I
(mA)
OUT
200ms/div
IN
IN
= 4V
= 5V
30025020015010050
MAX5092/93 toc24
MAX5092/93 toc26
INTERNAL BOOST DIODE FORWARD DROP
(MAX5092)
1500
1250
0V
0V
0V
BOOST CONVERTER POWER LOSS
= 11V)
(V
IN
IN
BSOUT
= 5V
= 3.5V
I
OUT
VIN = 5V
(mA)
1.2
TA = +105°C: VIN = 4V
1.0
V
V
0.8
0.6
VIN = 3.5V
POWER LOSS (W)
0.4
0.2
0
0350
1000
750
500
DIODE VOLTAGE (mV)
250
VIN = 4V
30025020015010050
VIN = 8V, BOOST CONVERTER
0
03.0
NOT SWITCHING
DIODE CURRENT (A)
GROUND CURRENT DISTRIBUTION
40
35
MAX5092/93 toc27
30
25
20
15
NUMBER OF UNITS
10
5
0
52
54
56 60 62 64 66
MAX5092/93 toc25
2.52.01.51.00.5
(162 UNITS TESTED)
TA = TJ = +125°C
= TJ = -40°C
T
A
58
I
(µA)
GND
MAX5092/93 toc28
68
70
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1IN
2EN
3 SGND
4 HOLD
5 PGND_LDO
6 SET
7 OUT_SENSE LDO Regulator Output Sense. Connect OUT_SENSE to OUT at the output capacitor near the load.
8 OUT
9 BSOUT
10, 11 LX
12 PGND_BST
13 BSFB
14 VL
15 CT
16 RESET
—EP
Input Supply Voltage. Bypass IN to the power ground plane with a 47µF (low-ESR) aluminum electrolytic
capacitor in parallel with a 1µF ceramic capacitor placed as close to the IC as possible.
Enable Input. Drive EN high to turn on the IC. Drive EN low to disable the IC. Connect EN directly to IN for
always-on operation.
Signal Ground. Connect SGND to the signal ground plane and the exposed paddle. Connect the power
ground and signal ground plane together at the negative terminal of the input capacitor(s).
Output Hold. When HOLD is forced low, the regulator stores the on-state of the output, allowing the
regulator to remain enabled even if EN is pulled low. To shut down the regulator, release HOLD after EN is
pulled low. If HOLD is unused, either connect HOLD to OUT or leave unconnected. HOLD is internally
connected to OUT through a 4µA pullup current.
LDO Power Ground. Connect PGND_LDO to the power ground plane. Connect the PGND_LDO ground and
signal ground plane together.
Feedback Input for the LDO. Connect SET directly to SGND to set the output voltage of the LDO to the
preset voltage of 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B). Connect SET to the center
tap of a resistor-divider connected between the LDO output and SGND to set the output voltage. V
regulates to 1.24V when using an adjustable output.
LDO Regulator Output. Bypass OUT to the power ground plane with a 10µF ceramic capacitor. V
regulates to a preset voltage of 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B), or is
adjustable from 1.5V to 9V (MAX5902_) or 1.5V to 10V (MAX5093_).
Boost Regulator Output Voltage. Bypass BSOUT to the PGND_BST ground plane with a 22µF (low-ESR)
aluminum electrolytic capacitor in parallel with a 1µF ceramic capacitor placed as close to the IC as
possible. Connect BSFB directly to SGND to regulate the BOOST output to a fixed voltage of 7V for V
BSOUT
follows V
7V. V
by connecting BSFB to the center tap of an external resistor-divider connected between the BOOST output
and PGND_BST.
Inductor Connection to the Drain of the Internal Power MOSFET. Connect LX to the switched side of the
inductor. Connect pins 10 and 11 together as close to the device as possible. For the MAX5093, also
connect LX to the anode of the external Schottky diode.
Boost Regulator Power Ground. Connect PGND_BST to the power ground plane. Connect the PGND_BST
ground plane and the signal ground plane together at the negative terminal of the input capacitor(s).
Feedback Input for the Boost Regulator. Connect BSFB directly to SGND to set the boost regulator output
voltage to 7V. Connect BSFB to the center tap of an external resistor-divider connected between BSOUT
and SGND to set the output voltage. V
Internal Regulator Output for IC Supply. Bypass VL to SGND with a 1µF/6.3V ceramic capacitor placed as
close to the IC as possible. V
RESET Timeout Programming Input. Connect a capacitor from CT to SGND to set the RESET timeout
period. See the CT Capacitor Selection section.
RESET Output. RESET is an open-drain output that goes high impedance when V
output voltage threshold after a programmed time delay. RESET pulls low immediately once V
below 90% of the regulated LDO output voltage.
Exposed Paddle. Connect to the signal ground plane (SGND). Connect to a large-signal ground plane for
increased thermal performance.
for VIN > 7V. V
IN
regulates to 5.5V with V
VL
is programmable up to 11V (MAX5092_) or 12V (MAX5093_)
BSOUT
regulates to 1.24V when using an adjustable output.
BSFB
≥ 5.5V.
BSOUT
exceeds 92% of the
OUT
OUT
SET
OUT
IN
drops
≤
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
10 ______________________________________________________________________________________
Figure 1. MAX5092_ Functional Diagram
Functional Diagrams
MAX5092_
HOLD
EN
2.25µs
ONE-SHOT
INOUT
THERMAL SHUTDOWN,
AND OVERCURRENT
1µs
ONE-SHOT
INOUT
CONTROL LOGIC,
PROTECTION
IN
INTERNAL
LDO
Q
S
Q
R
DRIVER
CURRENT-LIMITING
COMPARATOR
V
PK
V
REF
V
REF
R
S
MUX
ERROR AMPLIFIER
LDO
VL
VL
LX
LX
BSOUT
R1
BSFB
R2
OUT
OUT_SENSE
R3
MUX
DELAY
COMPARATOR
PGND_BST
0.92 x V
REF
CT
COMPARATOR
VL
2µA
SGND
PGND_LDO
P
R4
SET
CT
RESET
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 11
Figure 2. MAX5093_ Functional Diagram
Functional Diagrams (continued)
MAX5093_
2.25µs
ONE-SHOT
IN
1µs
ONE-SHOT
INOUT
Q
S
Q
R
INOUT
CURRENT-LIMITING
DRIVER
COMPARATOR
V
PK
V
REF
INTERNAL
LDO
R
S
MUX
LDO
VL
VL
LX
LX
BSOUT
R1
BSFB
R2
HOLD
EN
0.92 x V
REF
CONTROL LOGIC,
THERMAL SHUTDOWN,
AND OVERCURRENT
PROTECTION
CT
COMPARATOR
V
REF
VL
2µA
SGND
PGND_LDO
P
ERROR AMPLIFIER
R3
R4
MUX
DELAY
COMPARATOR
PGND_BST
OUT
OUT_SENSE
SET
CT
RESET
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
12 ______________________________________________________________________________________
Detailed Description
The MAX5092A/MAX5092B/MAX5093A/MAX5093B
include a step-up, switch-mode DC-DC converter and a
linear regulator to provide step-up/-down voltage conversion over a wide range of input voltages. This combination of an LDO and a boost converter offers the
advantage of using a single off-the-shelf inductor in
place of the multiple-winding custom magnetics needed
in typical SEPIC or transformer-based flyback topologies. The boost preregulator is completely turned off
during normal automotive operation (VIN= 14V),
reduces quiescent current to 65µA (typ), and makes the
devices suitable for always-on power supplies.
The devices have an internal UVLO threshold of 3.8V
(max, VINrising) that must be exceeded before the
device is enabled. When VINis above V
UVLO
, the internal boost converter starts switching and regulates
V
BSOUT
to the programmed boost output voltage. The
low quiescent-current LDO steps down V
BSOUT
to the
programmed LDO output voltage. The boost output is
preset to 7V, and the LDO output is preset to 3.3V
(MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B).
Both output voltages can be adjusted by using external
resistor-dividers.
If VINrises above 8V (typ), the boost converter is disabled, forcing V
BSOUT
to follow VIN. If VINfalls below
7.5V (typ), the boost converter starts switching and
regulates V
BSOUT
to 7V if BSFB is directly connected to
SGND. The boost converter regulates V
BSOUT
for V
IN
down to 3.5V, providing uninterrupted operation during
low cold-crank voltages even if the programmed LDO
output voltage is greater than VIN(but less than 9V).
The boost converter turn-on response time is less than
10µs, making cold-crank input glitches transparent to
the system even at full load.
The boost-converter output is followed by a high PSRR,
low-quiescent-current LDO. The LDO rejects the
switching noise present at BSOUT and provides a
clean, regulated output voltage. The linear regulator
uses an internal p-channel MOSFET pass element.
Additional features include a power-on-reset function
with an externally adjustable timeout, an enable (EN)
input, and a hold (HOLD) regulator control input.
Boost Converter
The switch-mode converter uses a minimum off-time,
maximum on-time pulse frequency modulation (PFM)
control scheme. The internal MOSFET turns on whenever V
BSOUT
falls below the regulation point determined
by V
BSFB
(see the
Setting the Boost Output Voltage
(V
BSOUT
)
section). The MOSFET turns off when the
inductor current reaches the peak current limit (2.5A
typ) or after 2.25µs maximum on-time, whichever
occurs first. The MOSFET is held off for at least 1µs
after the turn-on phase. A new switching cycle initiates
once V
BSOUT
falls below the threshold. In this control
scheme, switching frequency and output ripple are
functions of load current and input voltage. No frequency compensation is needed in the PFM control scheme.
The output of the boost converter is preset to 7V and is
adjustable by using external resistors. See the
Setting
the Boost Output Voltage V
BSOUT
section. Due to the
integrated blocking diode in the MAX5092_, V
BSOUT
is
limited to 11V. Use the MAX5093_ for higher boost output voltages (or to reduce the power dissipation in to
the package). The MAX5093_ requires an external
diode for the boost converter. Select the external diode
according to the
Schottky Diode Selection (MAX5093_)
section.
Linear Regulator
The MAX5092_/MAX5093_ contain an internal p-channel MOSFET used as the pass transistor for the LDO.
The output of the boost regulator is connected to the
source of the p-MOSFET. The LDO starts up 200µs
after the boost regulator starts up. The LDO supplies
up to 250mA with a typical dropout voltage of 0.9V. The
maximum LDO output current is determined by the
package power-dissipation limit as well as the internal
current limit. The LDO is designed to be a low-quiescent-current type. During normal operation when the
battery voltage is > 9V, the MAX5092_/MAX5093_ consume only 75µA (max) at +85°C and 100µA load.
The output voltage of the LDO is set using the SET
input. Connect SET to SGND to use the factory-preset
output voltage. Connect SET to the center of an external resistor-divider connected from OUT to SGND to
program a different output voltage. See the
Setting the
LDO Output Voltage (V
OUT
)
section.
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 13
Internal Regulator (VL)
An internal regulator (VL) is used to supply all internal
low-voltage blocks. Bypass VL to SGND with a 1µF
ceramic capacitor placed as close to the IC as possible. V
VL
regulates to 5.5V when V
BSOUT
is above 5.5V.
VVLtracks the voltage at BSOUT when V
BSOUT
is
below 5.5V.
Power-On-Reset Output (
RESET
)
The MAX5092_/MAX5093_ contain an open-drain output
(RESET) that indicates when the LDO output (V
OUT
) is
out of regulation. If the output of the LDO falls below 90%
of the nominal output voltage, RESET pulls low after a
short delay. Once the output rises above 92% of the
nominal output voltage, RESET goes high impedance
after the programmed reset timeout period. Connect a
100kΩ pullup resistor from OUT to RESET. See the
CT
Capacitor Selection
section for details on setting the
RESET timeout period.
Enable and Hold Inputs
The MAX5092_/MAX5093_ utilize two logic inputs, EN
(active-high) and HOLD (active low), to implement a
self-holding circuit with no additional components. For
example, an automotive ignition switch drives EN high
and the regulator turns on. If HOLD is then driven low,
the regulator remains on even if EN goes low. As long
as HOLD is forced low and remains low after initial regulator power-up, the regulator remains on. From this
state, release HOLD (an internal current source connects HOLD to OUT), or connect HOLD to OUT to turn
the regulator off. Drive EN low and HOLD high to place
the IC into shutdown mode. Shutdown mode reduces
supply current to 5µA. Figure 3 shows the timing diagram for the enable and hold functions. Table 1 shows
the state of the regulator output with respect to the voltage level at EN and HOLD with reference to Figure 3.
Connect HOLD to OUT or leave unconnected to disable the hold feature and use EN as a standard on/off
control input.
3
1
HOLD
EN
OUT
ORDER
2
4 56
Figure 3. Enable and Hold Timing Diagram
EN
COMMENTS
1
X
Initial State. EN has a 500nA pulldown to GND. HOLD has an internal current source to OUT.
HOLD follows OUT.
2
Regulator output is active when EN is pulled high. HOLD is in release state, and it follows
OUT.
3
HOLD is in release state. OUT follows EN.
4
Low
HOLD is pulled low externally after OUT turns on. The regulator output is forced on
regardless of the state of EN. A self-holding state.
5
HOLD is released after EN is pulled low. Output turns off.
5
X
Regulator enabled. Normal turn-on behavior. Regulator follows EN and HOLD follows OUT.
Table 1. Truth Table for Enable and Hold Timing Diagram
ORDER
Low
High Released On
Low Released Off
High
Low Released Off
High
HOLD OUT
Off
On
On
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
14 ______________________________________________________________________________________
Applications Information
Figure 4. MAX5092A Typical Application Circuit with Factory Preprogrammed LDO and Boost Output Voltages
L1
4.7µH
INPUT
4V TO 72V
C1*
47µF
VOUT
RESET
***
ON
OFF
1µF
R1
100kΩ
0.22µF
C2*
10 11
LX
1
IN
MAX5092A
16
RESET
2
EN
3
SGND
15
CT
C5
U1
LX
BSOUT
PGND_BST
BSFB
HOLD
OUT_SENSE
OUT
PGND_LDO
SET
14
VL
C6
1µF
9
C3*
12
13
4
7
8
5
6
1µF
C7
10µF
P
7V
C4*
22µF
µP
SIGNAL
OUTPUT
3.3V AT 250mA**
VOUT
P
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE.
**OUTPUT CURRENT IS LIMITED BY THE TOTAL POWER-DISSIPATION CAPABILITY OF THE PACKAGE.
***SEE PC BOARD LAYOUT GUIDELINES SECTION.
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 15
Applications Information (continued)
Figure 5. MAX5093A Typical Application Circuit with Factory Preprogrammed Boost and LDO Output Voltages
***
INPUT
4V TO 72V
VOUT
RESET
OFF
C1*
47µF
ON
L1
4.7µH
R1
100kΩ
0.22µF
C2*
1µF
C5
10 11
LX
1
IN
MAX5093A
16
RESET
2
EN
3
SGND
15
CT
U1
LX
BSOUT
PGND_BST
BSFB
HOLD
OUT_SENSE
OUT
PGND_LDO
SET
14
VL
C6
1µF
9
C3*
12
13
4
7
8
5
6
1µF
C7
10µF
P
7V
C4*
22µF
µP
SIGNAL
OUTPUT
3.3V AT 250mA**
VOUT
P
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE.
**OUTPUT CURRENT IS LIMITED BY THE TOTAL POWER-DISSIPATION CAPABILITY OF THE PACKAGE.
***SEE PC BOARD LAYOUT GUIDELINES SECTION.
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
16 ______________________________________________________________________________________
Applications Information (continued)
Figure 6. MAX5092A Typical Application Circuit with User-Programmed LDO and Boost Output Voltages
L1
4.7µH
INPUT
4V TO 72V
C1*
47µF
VOUT
RESET
***
ON
OFF
C2*
1µF
R3
100kΩ
C5
0.22µF
10 11
LX
1
IN
MAX5092A
16
RESET
2
EN
3
SGND
15
CT
U1
LX
BSOUT
PGND_BST
BSFB
HOLD
OUT_SENSE
OUT
PGND_LDO
SET
14
VL
9
12
13
4
7
8
5
6
C6
1µF
C3*
1µF
C7
10µF
P
5.5V
µP
SIGNAL
C4*
22µF
OUTPUT
8V (11V MAX)
R1
2.74MΩ (3.92MΩ)
R2
499kΩ
VOUT
OUTPUT
5V** (9V MAX)
R4
301kΩ (619kΩ)
R5
100kΩ
P
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST V
**OUTPUT CURRENT IS LIMITED BY THE TOTAL OUTPUT POWER AND THE DISSIPATION CAPABILITY OF THE PACKAGE.
***SEE PC BOARD LAYOUT GUIDELINES SECTION.
VOLTAGE.
IN
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 17
Applications Information (continued)
Figure 7. MAX5093A Typical Application Circuit with User-Programmable Boost Output Voltage and LDO Output Voltage
***
INPUT
4V TO 72V
VOUT
RESET
OFF
C1*
47µF
ON
L1
4.7µH
R3
100kΩ
0.22µF
C2*
1µF
C5
10 11
LX
1
IN
MAX5093A
16
RESET
2
EN
3
SGND
15
CT
U1
LX
BSOUT
PGND_BST
BSFB
HOLD
OUT_SENSE
OUT
PGND_LDO
SET
14
VL
C6
1µF
OUTPUT
9
C3*
12
13
4
7
8
5
6
1µF
C7
10µF
C4*
22µF
µP
SIGNAL
9V (12V MAX)
R1
3.16MΩ (4.32MΩ)
R2
499kΩ
VOUT
OUTPUT
5V** (10V MAX)
R4
301kΩ (698kΩ)
R5
P
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST V
**OUTPUT CURRENT IS LIMITED BY THE TOTAL OUTPUT POWER AND THE DISSIPATION CAPABILITY OF THE PACKAGE.
***SEE PC BOARD LAYOUT GUIDELINES SECTION.
VOLTAGE.
IN
100kΩ
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
18 ______________________________________________________________________________________
Design Guidelines
Input Capacitor (CIN) and
Boost Capacitor (C
BSOUT
) Selection
The input current waveform of the boost converter is
continuous, and usually does not demand high capacitance at its input. However, the MAX5092_/MAX5093_
boost converter is designed to fully turn on as soon as
the input drops below a certain voltage in order to ride
out cold-crank droops. This operation demands low
input source impedance for proper operation. If the
source (battery) is located far from the IC, high-capacity, low-ESR capacitors are recommended for C
IN
. The
worst-case peak capacitor current could be as high as
3A. Use a 47µF, 100mΩ low-ESR capacitor placed as
close as possible to the input of the device. Note that
the aluminum electrolytic capacitor ESR increases significantly at cold temperatures. In the cold temperature
case, choose an electrolyte capacitor with ESR lower
than 40mΩ or connect a low-ESR ceramic capacitor
(10µF) in parallel with the electrolytic capacitor.
The boost converter output (BSOUT) is fed to the input
of the internal 250mA LDO. The boost-converter output
current waveform is discontinuous and requires highcapacity, low-ESR capacitors at BSOUT to ensure low
V
BSOUT
ripple. During the on-time of the internal MOSFET,
the BSOUT capacitor supplies 250mA current to the
LDO input. During the off-time, the inductor dumps current into the output capacitor while supplying the output
load current. The internal 250mA LDO is designed with
high PSRR; however, high-frequency spikes may not be
rejected by the LDO. Thus, high-value, low-ESR electrolytic capacitors are recommended for C
BSOUT
.
Peak-to-peak V
BSOUT
ripple depends on the ESR of the
electrolyte capacitor. Use the following equation to calculate the required ESR (ESR
BSOUT
) of the BSOUT
capacitor:
where ∆V
ESRBS
is 75% of total peak-to-peak ripple at
BSOUT, I
LIM
is the internal switch current limit (3A max),
and I
OUT
is the LDO output current. Use a 100mΩ or
lower ESR electrolytic capacitor. Make sure the ESR at
cold temperatures does not cause excessive ripple
voltage. Alternately, use a 10µF ceramic capacitor in
parallel with the electrolyte capacitor.
During the switch on-time, the BSOUT capacitor discharges while supplying I
OUT
. The ripple caused by
the capacitor discharge (∆V
CBS
) is estimated by using
the following equation:
where I
OUT
is the LDO output current and C
BSOUT
is
the BSOUT capacitance.
Inductor Selection
The control scheme of the MAX5092/MAX5093 permits
flexibility in choosing an inductor value. Smaller inductance values typically offer smaller physical size for a
given series resistance, allowing the smallest overall
circuit dimensions. Circuits using larger inductance
may provide higher efficiency and exhibit less ripple,
but also may reduce the maximum output current. This
occurs when the inductance is sufficiently large to prevent the LX current limit (I
LIM
) from being reached
before the maximum on-time (t
ON-MAX
) expires.
For maximum output current, choose the inductor value
so that the controller reaches the current limit before
the maximum on-time is reached:
where t
ON-MAX
is typically 2.25µs, and the current limit
(I
LIM
) is a maximum of 3A (see the
Electrical
Characteristics
). Choose an inductor with the maximum
saturation current (I
SAT
) greater than 3A.
∆
V
ESR
BSOUT
ESRBS
=
−
II
LIM OUT
−
6
27 10
I
∆V
CBS
OUT
=
.
××
C
BSOUT
Vt
IN ON MAX
L
≤
×
I
LIM
−
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 19
Setting the Boost
Output Voltage (V
BSOUT
)
The MAX5092_/MAX5093_ feature Dual Mode™ operation for the internal boost converter output voltage.
These devices operate in a preset output-voltage mode
or an adjustable output-voltage mode. In preset mode,
internal trimmed feedback resistors set V
BSOUT
to a
fixed 7V. Select the preset mode by directly connecting
BSFB to SGND (Figures 4 and 5). Ensure a low-impedance path between BSFB and SGND to limit the transient at BSFB to below 100mV. In adjustable mode,
connect BSFB to the center tap of an external resistordivider connected between BSOUT and SGND to program V
BSOUT
(Figures 6 and 7). Note that the current
drawn by the resistor-divider at BSOUT adds to the quiescent current and the shutdown current of the IC. Use
the resistor-divider only if V
BSOUT
is required to be sig-
nificantly different than 7V. Select 499kΩ or lower resistance value for the bottom resistor (R2) of the divider
connected to SGND. The top resistor (R1) value is calculated as:
where V
BSFB
is the regulation voltage at BSFB (1.24V
typ) and V
BSOUT
is the desired output voltage for
BSOUT.
Setting the LDO Output Voltage (V
OUT
)
The LDO output voltage is also Dual Mode (preset and
adjustable). Preset mode is selected by connecting
SET to SGND (Figures 4 and 5). In preset mode, V
OUT
regulates to 3.3V (MAX5092A/MAX5093A) or 5V
(MAX5092B/MAX5093B) by internal trimmed feedback
resistors. Adjustable mode is selected by connecting
SET to the center tap of an external resistor-divider
connected between OUT and SGND (Figures 6 and 7).
Note that the current drawn by the resistor-divider at
OUT adds to the quiescent current of the LDO. Use the
resistor-divider only if V
OUT
is required to be signifi-
cantly different than the preset voltage. Select 100kΩ or
lower value for the bottom resistor (R5) of the divider
connected to SGND. The top resistor (R4) value is calculated as:
where V
SET
is the regulation voltage at SET (1.24V typ)
and V
OUT
is the desired output voltage for the LDO
output.
Schottky Diode Selection (MAX5093_)
The MAX5093_ requires an external diode connected
between LX and BSOUT (Figures 5 and 7). Proper
selection of an external diode can offer a lower forwardvoltage drop and a higher reverse-voltage handling
capability. Since the high switching frequency of the IC
demands a high-speed rectifier, Schottky diodes are
recommended for most applications because of their
fast recovery time and low forward-voltage drop.
Ensure that the diode’s peak current rating is greater
than or equal to the peak current limit of internal boost
converter MOSFET. A diode average forward current
rating of at least 1A is recommended. Additionally, the
diode reverse breakdown voltage must be greater than
the worst-case load-dump-condition voltage.
CT Capacitor Selection
The MAX5092_/MAX5093_ contain an open-drain
power-on-reset output (RESET) that indicates when the
LDO output voltage (V
OUT
) is out of regulation. When
V
OUT
rises above 92% of the nominal output voltage,
RESET goes high impedance after a user-programmable time delay. This time duration is programmable by a
capacitor (CCT) from CT to SGND (Figures 4–7). For a
chosen RESET active timeout period (t
DELAY
), calculate
the required capacitor value as:
When V
OUT
drops below 90% of the LDO output regulation voltage, a 5mA pulldown current from CT to SGND
discharges C
CT
. The time required to discharge CT
determines the delay necessary to pull RESET low. This
delay provides glitch immunity to the RESET function.
The glitch immunity delay is directly proportional to the
CT capacitor and is approximately 70µs for a 0.1µF
capacitor at CT.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
RR
12 1=×
⎛
⎜
⎝
V
BSOUT
V
BSFB
⎞
−
⎟
⎠
C
CT
−
6
210
××
=
.
124
t
DELAY
⎛
V
RR
45 1=×
OUT
⎜
V
⎝
SET
⎞
−
⎟
⎠
MAX5092/MAX5093
Maximum Output Current (I
OUT_MAX
)
The MAX5092_/MAX5093_ high input voltage (+72V
max) provides up to 250mA of current from OUT.
Package power-dissipation limits the amount of output
current available for a given input/output voltage and
ambient temperature. Figure 8 depicts the maximum
power-dissipation curve for the devices. The graph
assumes that the exposed metal pad of the IC package
is soldered to the PC board copper according to the
JEDEC 51 standard (multilayer board). Use Figure 8 to
determine the allowable package dissipation for a
given ambient temperature. Alternately, use the following formula to calculate the allowable package dissipation (P
DISS
) in watts:
For TA≤ +70°C:
P
DISS
= 2.67
For +70°C < TA≤ +125°C:
P
DISS
= 2.67 - (0.0333 x (TA- 70))
where +70°C < TA≤ +125°C and 0.0333W/°C is the
package thermal derating. After determining the allowable package dissipation, calculate the maximum output current (I
OUT_MAX
) using the following formula:
where P
DISS
is the allowable package power dissipa-
tion and P
LOSS(BST)
is the boost converter power loss.
P
DISS
includes the losses in the boost converter operation and the LDO itself. The boost converter loss
P
LOSS(BST)
, depends on VIN, V
BSOUT
, and I
OUT
. See
the Boost Converter Power Loss graphs in the
Typical
Operating Characteristics
to estimate the losses at a
given VINand V
BSOUT
at room temperature. At a higher
ambient temperature of +105°C, P
LOSS(BST)
increases
by up to 20% due to higher R
DS-ON
and switching losses of the internal boost converter MOSFET. (Note:
I
OUT_MAX
must be less than 250mA).
PC Board Layout Guidelines
Good PC board (PCB) layout and routing are required
in high-frequency switching power supplies to achieve
proper regulation and stability. It is strongly recommended that the evaluation kit PCB layouts be followed
as closely as possible. Refer to the MAX5092 EV kit for
an example layout. Follow these guidelines for good
PCB layout:
1) For SGND, use a large copper plane under the IC
and solder it to the exposed paddle. To effectively
use this copper area as a heat exchanger between
the PCB and ambient, expose this copper area on
the top and bottom side of the PCB. Do not make a
direct connection from the EP copper plane to pin 3
(SGND) underneath the IC so as to minimize
ground bounce.
2) Isolate the power components and high-current
path from the sensitive analog circuit.
3) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
4) Connect the return terminals of input capacitors
and boost output capacitors to the PGND_BST
power ground plane. Connect the power ground
(PGND_BST) and signal ground (SGND) planes
together at the negative terminal of the input capacitors. Do not connect them anywhere else. Connect
PGND_LDO ground plane to SGND ground plane
at a single point.
5) Ensure that the feedback connections are short and
direct. Ensure a low-impedance path between
BSFB and SGND to limit the transient at BSFB to
100mV.
6) Route high-speed switching nodes away from the
sensitive analog areas. Use the internal PCB layer
for SGND as an EMI shield to keep radiated noise
away from the IC, feedback dividers, and bypass
capacitors.
4V to 72V Input LDOs with Boost Preregulator
20 ______________________________________________________________________________________
Figure 8. MAX5092/MAX5093 Package Power Dissipation
MAXIMUM POWER DISSIPATION
3.0
2.5
2.0
1.5
1.0
0.5
MAXIMUM POWER DISSIPATION (W)
vs. AMBIENT TEMPERATURE
0
-40 125
AMBIENT TEMPERATURE (°C)
1109580655035205-10-25
I
OUT MAX
PP
−
_
VV
IN OUT
DISS LOSS BST
=
()
−
MAX5092/93 fig08
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 21
Chip Information
PROCESS: BiCMOS
Selector Guide
Typical Operating Circuit
INPUT
4V TO 72V
VOUT
RESET
OUTPUT
ENABLE
*
P
IN
RESET
EN
SGND
CT
LX
MAX5092B
LX
BSOUT
PGND_BST
BSFB
HOLD
OUT_SENSE
OUT
PGND_LDO
SET
VL
+7V OUTPUT
+5V OUTPUT
VOUT
P
*SEE PC BOARD LAYOUT GUIDELINES SECTION.
PART
MAX5092AATE+ 3.3 Yes 7 Yes Internal
MAX5092BATE+ 5 Yes 7 Yes Internal
MAX5093AATE+ 3.3 Yes 7 Yes External
MAX5093BATE+ 5 Yes 7 Yes External
PRESET LDO
OUTPUT (V)
ADJUSTABLE
LDO OUTPUT
PRESET BSOUT
OUTPUT (V)
ADJUSTABLE BSOUT
OUTPUT
BOOST DIODE
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
22 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
QFN THIN.EPS
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
23
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
Loading...