Rainbow Electronics MAX500 User Manual

19-1016; Rev 2; 2/96
CMOS, Quad, Serial-Interface
8-Bit DAC
_______________General Description
The MAX500 is a quad, 8-bit, voltage-output digital-to­analog converter (DAC) with a cascadable serial inter­face. The IC includes four output buffer amplifiers and input logic for an easy-to-use, two- or three-wire serial interface. In a system with several MAX500s, only one serial data line is required to load all the DACs by cas­cading them. The MAX500 contains double-buffered logic and a 10-bit shift register that allows all four DACs to be updated simultaneously using one control signal. There are three reference inputs so the range of two of the DACs can be independently set while the other two DACs track each other.
The MAX500 achieves 8-bit performance over the full operating temperature range without external trimming.
________________________Applications
Minimum Component Count Analog Systems Digital Offset/Gain Adjustment Industrial Process Control Arbitrary Function Generators Automatic Test Equipment
________________Functional Diagram
V
C
REF
V
A/B
V
DAC A
REF
D
V
A
OUT
REF
SRO
AGND
DGND V
INPUT REG A
V
LDAC
DD
SS
DAC
REG A
____________________________Features
Buffered Voltage OutputsDouble-Buffered Digital InputsMicroprocessor and TTL/CMOS CompatibleRequires No External AdjustmentsTwo- or Three-Wire Cascadable Serial Interface16-Pin DIP/SO Package and 20-Pin LCCOperates from Single or Dual Supplies
______________Ordering Information
PART
MAX500ACPE MAX500BCPE
MAX500ACWE MAX500BCWE MAX500BC/D 0°C to +70°C Dice* MAX500AEPE -40°C to +85°C 16 Plastic DIP MAX500BEPE -40°C to +85°C 16 Plastic DIP MAX500AEWE MAX500BEWE MAX500AEJE -40°C to +85°C 16 CERDIP MAX500BEJE -40°C to +85°C 16 CERDIP MAX500AMJE MAX500BMJE MAX500AMLP MAX500BMLP
*Contact factory for dice specifications.
TEMP. RANGE PIN-PACKAGE
0°C to +70°C 0°C to +70°C 0°C to +70°C
16 Plastic DIP 16 Plastic DIP 16 Wide SO
0°C to +70°C 16 Wide SO
-40°C to +85°C 16 Wide SO
-40°C to +85°C 16 Wide SO
-55°C to +125°C 16 CERDIP
-55°C to +125°C 16 CERDIP
-55°C to +125°C 20 LCC
-55°C to +125°C 20 LCC
ERROR (LSB)
±1 ±2 ±1 ±2 ±2 ±1 ±2 ±1 ±2 ±1 ±2 ±1 ±2 ±1 ±2
_________________Pin Configurations
MAX500
V
10/11-
SHIFT
REGISTER
CONTROL
LOGIC
LOAD
BIT
SCL
SDA
B
INPUT REG B
DATA BUS
INPUT REG C
INPUT REG D
DAC
REG B
DAC
REG C
DAC
REG D
DAC B
DAC C
DAC D
OUT
V
C
OUT
V
D
OUT
MAX500
________________________________________________________________
TOP VIEW
B
V
V
OUT
V
OUT
REF
AGND DGND
LDAC
V A/B
SDA
1
A
2
SS
3
MAX500
4 5 6 7 8
16 15 14 13 12 11 10
V V V VREFC V SRO SCL
LOAD
9
DIP/SO
Pin Configurations continued on last page.
Maxim Integrated Products
OUTC
OUT DD
REF
D
D
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
CMOS, Quad, Serial-Interface 8-Bit DAC
ABSOLUTE MAXIMUM RATINGS
Power Requirements
to AGND...........................................................-0.3V, +17V
V
DD
to DGND ..........................................................-0.3V, +17V
V
DD
to DGND..................................................-7V, (VDD+ 0.3V)
V
SS
to VSS...............................................................-0.3V, +24V
V
DD
Digital Input Voltage to DGND ....................-0.3V, (V
to AGND.............................................-0.3V, (VDD+ 0.3V)
V
REF
MAX500
to AGND (Note 1)...............................-0.3V, (VDD+ 0.3V)
V
OUT
Power Dissipation (T
Plastic DIP (derate 10.53mW/°C above +70°C)............842mW
= +70°C)
A
DD
+ 0.3V)
Wide SO (derate 9.52mW/°C above +70°C)................762mW
CERDIP (derate 10.00mW/°C above +70°C)...............800mW
LCC (derate 9.09mW/°C above +70°C).......................727mW
Operating Temperature Ranges
MAX500_C_ _ ....................................................0°C to + 70°C
MAX500_E_ _...................................................-40°C to +85°C
MAX500_M_ _................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
Note 1: The outputs may be shorted to AGND, provided that the power dissipation of the package is not exceeded.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Typical short-circuit current to AGND is 25mA
ELECTRICAL CHARACTERISTICS—Dual Supplies
(VDD= +11.4V to +16.5V, VSS= -5V ±10%, AGND = DGND = 0V, V
STATIC PERFORMANCE
Total Unadjusted Error
Relative Accuracy
Full-Scale Error
Zero-Code Error
REFERENCE INPUT
Reference Input Resistance
AC Feedthrough TA= +25°C (Notes 2, 3) -70 dB
DIGITAL INPUTS
Digital Input High Voltage V Digital Input Low Voltage V Digital Output High Voltage V Digital Output Low Voltage V
Digital Input Capacitance TA= +25°C (Note 2) 8 pF
VDD= 15V ±5%, V
= 10V
REF
MAX500A MAX500B Guaranteed monotonic MAX500A MAX500B V
= 10V
REF
TA= +25°C
TA= T
V
REF
V
REF
TA= +25°C, code dependent (Note 2) T
A
IH IL
I
OH OL
OUT
I
OUT
(Note 4)Digital Input Leakage Current
to T
MIN
MAX
C, V
D
REF
A/B
= +25°C (Notes 2, 3)
= -1mA, SRO only VDD- 1 V = 1mA, SRO only 0.4 V
= +2V to (VDD- 4V), TA= T
REF
CONDITIONS
MAX500A MAX500B
MAX500A MAX500B MAX500A MAX500B
Excluding LOAD LOAD = 0V
to T
MIN
11
5.5
2.4 5.5
, unless otherwise noted.)
MAX
UNITSMIN TYP MAXSYMBOLPARAMETER
±1 ±2
±1/2
±1
±1/2
±1
ppm/°C±5Full-Scale Tempco ±15 ±20 ±20 ±30
- 4Reference Input Range
DD
0.8 V
±1 30
Bits8Resolution
LSB
LSB LSB±1Differential Nonlinearity LSB
mV
µV/°C±30Zero-Code Tempco
V2V k pF100Reference Input Capacitance
dB-60Channel-to-Channel Isolation
V
µA
2 _______________________________________________________________________________________
CMOS, Quad, Serial-Interface
8-Bit DAC
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(VDD= +11.4V to +16.5V, VSS= -5V ±10%, AGND = DGND = 0V, V
DYNAMIC PERFORMANCE
TA = +25°C (Note 2)
Settling Time
OUT
To ±1/2LSB, V 2kin parallel with 100pF load (Note 2)
REF
(Note 5) (Note 5) V
= 10V
OUT
Positive Supply Voltage
POWER SUPPLIES
Positive Supply Voltage
Positive Supply Current
Negative Supply Current
I
DD
I
For specified performance
DD
For specified performance V11.4 16.5V
DD
Outputs unloaded
Outputs unloaded
SS
SWITCHING CHARACTERISTICS (TA= +25°C, Note 6) 3-Wire Mode
SDA Valid to SCL Setup SDA Valid to SCL Setup SDA Valid to SCL Hold SCL High Time SCL Low Time
S1 S1
H
1 2
(Note 7) µs50SCL Rise Time (Note 7) µs50SCL Fall Time
LOAD Pulse Width LOAD Delay from SCL LDAC Pulse Width
SRO Output Delay t
2-Wire Mode
SCL High Time t SDA Valid to SCL Hold t SCL High Time t SCL Low Time t
LDW
LDS
t
LDAC
D1
H
C
= 50pF 150 ns
LOAD
1
1 2
SCL Rise Time (Note 7) 50 µs SCL Fall Time (Note 7) 50 µs LDAC Pulse Width SCL Valid to SDA Setup t SDA Valid to SCL Setup t SDA Valid to Rising SCL t SRO Output Delay t
t
LDAC
S1 S2 S3 D1
Start condition 150 ns Stop condition 100 ns
C
= 50pF 150 ns
LOAD
= +2V to (VDD- 4V), TA= T
REF
CONDITIONS
= 10V, VDD= +15V,
TA= +25°C TA= T
MIN
TA= +25°C TA= T
MIN
to T
to T
MAX
MAX
to T
MIN
, unless otherwise noted.)
MAX
38Voltage Output Slew Rate
10 12
-9
-10
150 ns
350 ns
0 ns 350 ns 350 ns
150 ns
125 ns
MAX500
UNITSMIN TYP MAXSYMBOLPARAMETER
V/µs
µs2.5 4.5V
nV-s50Digital Feedthrough nV-s50Digital Crosstalk
k2Output Load Resistance
V11.4 16.5V
mA
mA
ns150t ns150t ns0t ns350t ns350t
ns150t ns150t
_______________________________________________________________________________________ 3
CMOS, Quad, Serial-Interface
8-Bit DAC
ELECTRICAL CHARACTERISTICS—Single Supply
(VDD= +15V ±5%, VSS= AGND = DGND = 0V, V
STATIC PERFORMANCE
Total Unadjusted Error
MAX500
Relative Accuracy
Full-Scale Error
Zero-Code Error
REFERENCE INPUTAll specifications are the same as for dual supplies. DIGITAL INPUTSAll specifications are the same as for dual supplies. DYNAMIC PERFORMANCEAll specifications are the same as for dual supplies. POWER SUPPLIES
Positive Supply Voltage Positive Supply Current
SWITCHING CHARACTERISTICSAll specifications are the same as for dual supplies.
Note 2: Guaranteed by design. Not production tested. Note 3: T
= +25°C, V
A
= 10kHz, 10V peak-to-peak sine wave.
REF
Note 4: LOAD has a weak internal pull-up resistor to V Note 5: DAC switched from all 1s to all 0s, and all 0s to all 1s code. Note 6: Sample tested at +25°C to ensure compliance. Note 7: Slow rise and fall times are allowed on the digital inputs to facilitate the use of opto-couplers. Only timing for SCL is given
because the other digital inputs should be stable when SCL transitions.
I
DD
DD
= 10V, TA= T
REF
MIN
to T
CONDITIONS
VDD= 15V ±5%, V
= 10V
REF
Guaranteed monotonic
V
= 10V ppm/°C±5Full-Scale Tempco
REF
TA= +25°C
TA= T
MIN
to T
MAX
For specified performance Outputs unloaded
.
DD
, unless otherwise noted.)
MAX
MAX500A MAX500B MAX500A MAX500B
MAX500A MAX500B
MAX500A MAX500B MAX500A MAX500B
TA= +25°C TA= T
MIN
to T
MAX
±1 ±2
±1/2
±1
±1/2
±1
±15 ±20 ±20 ±30
10 12
UNITSMIN TYP MAXSYMBOLPARAMETER
Bits8Resolution
LSB
LSB LSB±1Differential Nonlinearity LSB
mV
µV/°C±30Zero-Code Tempco
V14.25 15.75V
mA
__________________________________________Typical Operating Characteristics
RELATIVE ACCURACY vs. REFERENCE VOLTAGE
1.0
0.5
-0.5
RELATIVE ACCURACY (LSB)
-1.0 0
2
TA = +25°C, VSS = -5V
VDD = 15V
VDD = 12V
406 8 10 12 14
(V)
V
REF
MAX500-04
DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE
1.0
0.5
0
-0.5
DIFFERENTIAL NONLINEARITY (LSB)
-1.0
TA = +25°C, VSS = -5V
20
VDD = 12V
VDD = 15V
6 8 10 12 14
4
V
(V)
REF
MAX500-05
4 _______________________________________________________________________________________
CMOS, Quad, Serial-Interface
8-Bit DAC
____________________________Typical Operating Characteristics (continued)
OUTPUT SINK CURRENT
16
VSS = -5V
14 12 10
(mA)
8
SINK
I
6 4 2 0
0
vs. OUTPUT VOLTAGE
RO 200
VSS = 0V
4
2610
V
(V)
OUT
8
12 10
MAX500-01
8 6 4 2 0
SUPPLY CURRENT (mA)
-2
-4
-6
-55 125
_______________Detailed Description
The MAX500 has four matched voltage-output digital-to­analog converters (DACs). The DACs are “inverted” R-2R ladder networks which convert 8 digital bits into equivalent analog output voltages in proportion to the applied reference voltage(s). Two DACs in the MAX500 have a separate reference input while the other two DACs share one reference input. A simplified circuit diagram of one of the four DACs is provided in Figure 1.
R
RR
SUPPLY CURRENT
vs. TEMPERATURE
I
DD
I
SS
25-25 0 7550 100
TEMPERATURE (°C)
V
OUT
ZERO-CODE ERROR
2.0
1.5
MAX500-02
1.0
0.5
0.0
-0.5
-1.0
ZERO-CODE ERROR (mV)
-1.5
-2.0
-55 12525-25 0 7550 100
of the V
inputs is code dependent. The lowest
REF
value, approximately 11k(5.5kfor V
vs. TEMPERATURE
V
OUT
VSS = -5V
TEMPERATURE (°C)
V
A
OUT
V
B
OUT
V
C
OUT
D
A/B), occurs
REF
when the input code is 01010101. The maximum value of infinity occurs when the input code is 00000000. Because the input resistance at V
is code depen-
REF
dent, the DAC’s reference sources should have an out­put impedance of no more than 20(no more than 10for V
A/B). The input capacitance at V
REF
REF
also code dependent and typically varies from 15pF to 35pF (30pF to 70pF for V V
OUT
C, and V
D can be represented by a digitally
OUT
REF
A/B). V
OUT
A, V
OUT
programmable voltage source as:
V
OUT
= Nbx V
REF
/ 256
where Nbis the numeric value of the DAC’s binary input code.
MAX500
MAX500-03
is
B,
2R 2R 2R 2R
2R
DB0
DB0 DB5 DB6 DB7
V
REF
AGND
… …
DB5
DB6
DB7
Figure 1. Simplified DAC Circuit Diagram
The voltage at the V
V
pins (pins 4, 12, and 13) sets
REF
REF
Input
the full-scale output of the DAC. The input impedance
_______________________________________________________________________________________
Output Buffer Amplifiers
All voltage outputs are internally buffered by precision unity-gain followers, which slew at greater than 3V/µs. When driving 2kin parallel with 100pF with a full-scale transition (0V to +10V or +10V to 0V), the output settles to ±1/2LSB in less than 4µs. The buffers will also drive 2kin parallel with 500pF to 10V levels without oscilla­tion. Typical dynamic response and settling perfor­mance of the MAX500 is shown in Figures 2 and 3.
A simplified circuit diagram of an output buffer is shown in Figure 4. Input common-mode range to AGND is provided by a PMOS input structure. The out­put circuitry incorporates a pull-down circuit to actively drive V (VSS). The buffer circuitry allows each DAC output to
to within +15mV of the negative supply
OUT
5
CMOS, Quad, Serial-Interface 8-Bit DAC
POSITIVE STEP 
= -5V or 0V)
(V
SS
MAX500
1µs/div
Figure 2. Positive and Negative Settling Times
DYNAMIC RESPONSE
= -5V or 0V)
(V
SS
LDAC 5V/div
OUTPUT 100mV/div
LDAC 5V/div
OUTPUT 5V/div
INPUT
(5V/div)
OUTPUT
(20mV/div)
V
DD
FROM
INVERTED
OUTPUT
DAC
(+)
INPUTS
PMOS
NEGATIVE STEP 
= -5V or 0V)
(V
SS
1µs/div
(-)
C
C
LDAC 5V/div
OUTPUT 100mV/div
FOLLOWER
NPN
EMITTER PULL-UP
V
OUT
2µs/div
Figure 3. Dynamic Response
V
SS
Figure 4. Simplified Output Buffer Circuit
sink, as well as source up to 5mA. This is especially important in single-supply applications, where VSSis connected to AGND, so that the zero error is kept at or under 1/2LSB (V Current vs. Output Voltage is shown in the
Operating Characteristics
= +10V). A plot of the Output Sink
REF
section.
Typical
Digital Inputs
and Interface Logic
The digital inputs are compatible with both TTL and 5V CMOS logic; however, the power-supply current (IDD) is somewhat dependent on the input logic level. Supply current is specified for TTL input levels (worst case) but is reduced (by about 150µA) when the logic inputs are driven near DGND or 4V above DGND.
Do not drive the digital inputs directly from CMOS logic running from a power supply exceeding 5V. When driv-
ing SCL through an opto-isolator, use a Schmitt trigger to ensure fast SCL rise and fall times.
The MAX500 allows the user to choose between a 3-wire serial interface and a 2-wire serial interface. The choice between the 2-wire and the 3-wire inter­face is set by the LOAD signal. If the LOAD is allowed to float (it has a weak internal pull-up resistor to VDD), the 2-wire interface is selected. If the LOAD signal is kept to a TTL-logic high level, the 3-wire interface is selected.
3-Wire Interface
The 3-wire interface uses the classic Serial Data (SDA), Serial Clock (SCL), and LOAD signals that are used in standard shift registers. The data is clocked in on the falling edge of SCL until all 10 bits (8 data bits and 2 address bits) are entered into the shift register.
6 _______________________________________________________________________________________
NMOS
ACTIVE
PULL-DOWN
CIRCUIT
CMOS, Quad, Serial-Interface
8-Bit DAC
MAX500
SCL
SDA
LOAD
LDAC
SRO
(SERIAL OUTPUT)
SCL
SDA
SRO
Figure 5. 3-Wire Mode
A1 A0
t
2
t
S1
t
D1
D7
D6 D5 D4 D3 D2
MSB
t
1
t
H
SCL
LOAD
LDAC
D0
D1
LSB
t
t
LDS
LDS
t
LDW
t
LDAC
SCL
SDA
LDAC
SRO
(SERIAL OUTPUT)
SCL
SDA
SRO
Figure 6. 2-Wire Mode
_______________________________________________________________________________________ 7
D7
A0
A1
t
2
t
S1
t
D1
t
D1
MSB
t
1
D6 D5 D4
t
S3
D3
SCL
SDA
LDAC
D2 D1
D0
LSB
t
S2
t
LDS
t
LDAC
CMOS, Quad, Serial-Interface 8-Bit DAC
A low level on LOAD line initiates the transfer of data from the shift register to the addressed input register. The data can stay in this register until all four of the input registers are updated. Then all of the DAC regis­ters can be simultaneously updated using the LDAC (load DAC) signal. When LDAC is low, the input regis­ter’s data is loaded into the DAC registers (see Figure 5 for timing diagram). This mode is cascadable by con-
MAX500
necting Serial Output (SRO) to the second chip’s SDA pin. The delay of the SRO pin from SCL does not cause setup/hold time violations, no matter how many MAX500s are cascaded. Restrict the voltage at LDAC and LOAD to +5.5V for a logic high.
2-Wire Interface
The 2-wire interface uses SDA and SCL only. LOAD must be floating or tied to VDD. Each data frame (8 data bits and 2 address bits) is synchronized by a timing relationship between SDA and SCL (see Figure 6 for the timing diagram). Both SDA and SCL should normal­ly be high when inactive. A falling edge of SDA (while SCL is high) followed by a falling edge of SCL (while SDA is low) is the start condition. This always loads a 0 into the first bit of the shift register. The shift register is extended to 11 bits so this “data” will not affect the input register information. The timing now follows the 3­wire interface, except the SDA line is not allowed to change when SCL is high (this prevents the MAX500 from retriggering its start condition). After the last data bit is entered, the SDA line should go low (while the SCL line is low), then the SCL line should rise followed by the SDA line rising. This is defined as the stop con­dition, or end of frame.
Cascading the 2-wire interface can be done, but the user must be careful of both timing and formatting. Timing must take into account the intrinsic delay of the SRO pin from the internally generated start/stop condi­tions. The tS2value should be increased by n times t (where n = number of cascaded MAX500s). The t value should also be increased by n times tD1. No other timing parameters need to be modified. A more serious concern is one of formatting. Generally, since each frame has a start/stop condition, each chip that has data cascaded through it will accept that data as if it were its own data. Therefore, to circumvent this limita­tion, the user should not generate a stop bit until all DACs have been loaded. For example, if there are three MAX500s cascaded in the 2-wire mode, the data transfer should begin with a start condition, followed by 10 data bits, a zero bit, 10 data bits, a zero bit, 10 data bits, and then a stop condition. This will prevent each MAX500 from decoding the middle data for itself.
D1
LDS
The data is entered into the shift register in the follow­ing order:
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
(First) (MSB) (Last)
where address bits A1 and A0 select which DAC regis­ter receives data from the internal shift register. Table 1 lists the channel addresses. D7 (MSB) through D0 is the data byte.
Since LDAC is asynchronous with respect to SCL, SDA, and LOAD, care must be taken to assure that incorrect data is not latched through to the DAC registers. If the 3-wire serial interface is used, LDAC can be either tied low permanently or tied to LOAD as long as t
LDS
always maintained. However, if the 2-wire interface is used, LDAC should not fall before the stop condition is internally detected. (This is the reason for the t
LDS
delay of LDAC after the last rising edge of SDA.)
Table 1. DAC Addressing
A1 A0 SELECTED INPUT REGISTER
L L DAC A Input Register L H DAC B Input Register H L DAC C Input Register H H DAC D Input Register
Table 2. Logic Input Truth Table
SCL SDA LOAD LDAC FUNCTION
F Data V
H Data V
LXV F Data M H
HXMH
LXMH
HXLH
HXLL
Notes:
H = Logic High 2W = 2-Wire L = Logic Low 3W = 3-Wire M = TTL Logic High F = Falling Edge X = Don’t Care
DD
DD
DD
Latching data into
H
shift register (2W) Data should not be
H
changing (2W) Data is allowed to
H
change (2W) Latching data into shift register (3W) Data is allowed to change (3W) Data is allowed to change (3W) Loads input register from shift register (3W) DAC register reflects data held in their respective input registers
is
8 _______________________________________________________________________________________
CMOS, Quad, Serial-Interface
8-Bit DAC
The SRO output swings from VDDto DGND. Cascading to other MAX500s poses no problem. If SRO is used to drive a TTL-compatible input, use a clamp diode between TTL +5V and VDDand the current-limiting resistor to prevent potential latchup problems with the 5V supply.
Table 2 shows the truth table for SDA, SCL, LOAD, and LDAC operation. Figures 5 and 6 show the timing dia­grams for the MAX500.
__________Applications Information
Power-Supply and Reference
Operating Ranges
The MAX500 is fully specified to operate with V between +12V ±5% and +15V ±10% (+11.4V to +16.5V), and with VSSfrom 0V to -5.5V. 8-bit perfor­mance is also guaranteed for single-supply operation (VSS= 0V), however, zero-code error is reduced when VSSis -5V (see
Output Buffer Amplifiers
section).
For an adequate DAC and buffer operating range, the V
voltage must always be at least 4V below VDD.
REF
The MAX500 is specified to operate with a reference input range of +2V to VDD- 4V.
Ground Management
Digital or AC transient signals between AGND and DGND will create noise at the analog outputs. It is rec­ommended that AGND and DGND be tied together at the DAC and that this point be tied to the highest quali­ty ground available. If separate ground buses are used, then two clamp diodes (1N914 or equivalent) should be connected between AGND and DGND to keep the two
DD
ground buses within one diode drop of each other. To avoid parasitic device turn-on, AGND must not be allowed to be more negative than DGND. DGND should be used as supply ground for bypassing purposes.
REFERENCE INPUTS
12414
13
V
D
CV
REF
REF
DAC A
DAC B
V
SS
3
AGND
DIGITAL INPUTS
NOT
SHOWN
MAX500
REF
A/B
V
DAC C
DAC D
-5V (OR GND)
Figure 8. MAX500 Unipolar Output Circuit
+15V
V
DD
2
V
A
OUT
1
V
B
OUT
16
V
C
OUT
15
V
D
OUT
DGND
56
MAX500
SYSTEM GND
B
V
OUT
V
A
OUT
V
SS
V
A/B
REF
AGND DGND
COMPONENT SIDE (TOP VIEW)
Figure 7. Suggested MAX500 PC Board Layout for Minimizing Crosstalk
_______________________________________________________________________________________ 9
C
V
OUT
D
V
OUT
V
DD
V
C
REF
V
D
REF
V
REF
DAC OUTPUT FROM MAX500
NOTE: V
R1 R2
+15V
-15V
R1 = R2 = 10k ±0.1%
IS THE REFERENCE INPUT FOR THE MAX500
REF
V
OUT
Figure 9. Bipolar Output Circuit
CMOS, Quad, Serial-Interface 8-Bit DAC
Table 3. Unipolar Code Table Table 4. Bipolar Code Table
DAC CONTENTS
MSB LSB
1 1 1 1 1 1 1 1
ANALOG
OUTPUT
+V
REF
255
(––––)
256
MAX500
1 0 0 0
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0V
Note: 1LSB = (V
) (2-8) = +V
REF
0 0 0 1
REF
+V
1
(–––)
256
+V
REF
+V
+V
Careful PC board ground layout techniques should be used to minimize crosstalk between DAC outputs, the reference input(s), and the digital inputs. This is partic­ularly important if the reference is driven from an AC source. Figure 7 shows suggested PC board layouts for minimizing crosstalk.
Unipolar Output
In unipolar operation, the output voltages and the refer­ence input(s) are the same polarity. The unipolar circuit configuration is shown in Figure 8 for the MAX500. The device can be operated from a single supply with a slight increase in zero error (see
Amplifiers
the voltage at V respect to AGND. The unipolar code table is given in Table 3.
section). To avoid parasitic device turn-on,
must always be positive with
REF
129
(––––)
REF
256
128
(––––)= +
256 2
127
(––––)
REF
256
1
(––––)
REF
256
Output Buffer
V
REF
––––
DAC CONTENTS
MSB LSB
1 1 1 1 1 1 1 1
1 0 0 0
1 0 0 0 0 0 0 0 0V
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
Note: 1LSB = (V
+
V
IN
­5
+
V
BIAS
-
DIGITAL INPUTS NOT SHOWN
Figure 10. AGND Bias Circuit
) (2-8) = +V
REF
AGND
-5V (OR GND)
0 0 0 1
4 V
DAC A
V
SS
3
REF
A/B
MAX500
REF
1
(–––)
256
+15V
DGND
-V
14
V
DD
6
ANALOG
OUTPUT
+V
REF
+V
REF
-V
REF
-V
REF
128
(––––) = -V
REF
128
127
(––––)
128
1
(––––)
128
1
(––––)
128 127
(––––)
128
REF
2
V
A
OUT
Bipolar Output
Each DAC output may be configured for bipolar opera­tion using the circuit in Figure 9. One op amp and two resistors are required per channel. With R1 = R2:
V
= V
OUT
where DAis a fractional representation of the digital word in Register A.
Table 4 shows the digital code versus output voltage for the circuit in Figure 9.
REF
(2DA- 1)
AGND can be biased above DGND to provide an arbi­trary nonzero output voltage for a “zero” input code. This is shown in Figure 10. The output voltage at V
V
OUT
A = V
BIAS
+ DAV
where DAis a fractional representation of the digital input word. Since AGND is common to all four DACs, all outputs will be offset by V Since AGND current is a function of the four DAC
Offsetting AGND
IN
in the same manner.
BIAS
codes, it should be driven by a low-impedance source. V
must be positive.
BIAS
10 ______________________________________________________________________________________
OUT
A is:
CMOS, Quad, Serial-Interface
8-Bit DAC
Using an AC Reference
In applications where V the MAX500 has multiplying capability within the limits of the V
input range specifications. Figure 11 shows
REF
a technique for applying a sine-wave signal to the refer­ence input, where the AC signal is biased up before being applied to V
REF
than 0.1% with input frequencies up to 50kHz, and the typical -3dB frequency is 700kHz. Note that V never be more negative than AGND.
The performance of the MAX500 is specified for both dual and single-supply (VSS= 0V) operation. When the improved performance of dual-supply operation is desired, but only a single supply is available, a -5V V supply can be generated using an ICL7660 in one of the circuits of Figure 12.
has AC signal components,
REF
. Output distortion is typically less
must
REF
Generating V
SS
SS
Digital Interface Applications
Figures 13 through 16 show examples of interfacing the MAX500 to most popular microprocessors.
12V to 15V
10k
6V
ZENER
2N2222
8
10k 10µF
3
10µF
2
CAP+ CAP-
V+
ICL7660
GND
4
5
V
OUT
+15V
15k
AC
REFERENCE
INPUT
+4V
DIGITAL INPUTS NOT SHOWN
10k
-4V
4 V
DAC B
SS
36
-5V (OR GND)
Figure 11. AC Reference Input Circuit
10µF
2
CAP+ CAP-
8
V+
ICL7660
3
GND
10µF
-5V
+5V
LOGIC
SUPPLY
OUT
V
SS
REF
A/B
AGND
4
V
OUT
MAX500
14
V
DD
V
V
OUT
MAX500
DGNDV
5
5
-5V
10µF
B
B
OUT
1
OUT
V
SS
Figure 12. Generating -5V for V
80C51
P1.0 P1.1
P1.2
. . . . . . .
P1.3
*
CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR CONNECT LOAD TO VDD FOR 2-WIRE MODE
Figure 13. 80C51 Interface
______________________________________________________________________________________ 11
SS
SCL SDA LDAC LOAD*
MAX500
A15
SRO
A
V
OUT
B
V
OUT
V
C
OUT
V
D
OUT
A/B
V
REF
V
C
REF
V
D
REF
Z80
I/O REQ
ADDRESS BUS
A0
ADDRESS
EN
WR INT
D7 D0
CODE
DATA BUS
*
CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR CONNECT LOAD TO V
A1 A0
FOR 2-WIRE MODE
DD
B/A C/D CE
RD INT
D7 D0
Z8420
B0 B1
MAX500
SCL SDA
B2
LDAC
. .
B3
LOAD*
Figure 14. Z-80 with Z8420 PIO Interface
CMOS, Quad, Serial-Interface, 8-Bit DAC
A15
A8
8085/
MAX500
8088
WR
ALE
AD7 AD0
ADDRESS BUS
82C55
A0
PA0
ADDRESS
DECODE
LATCH
EN
ADDRESS AND DATA BUS
*
CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR CONNECT LOAD TO V
A1 CS WR
D7
D0
FOR 2-WIRE MODE
DD
PA1 PA2
PA3
SCL
MAX500
SDA LDAC
. .
LOAD*
Figure 15. 8085/8088 with Programmable Peripheral Interface Figure 16. 6809/6502 Interface
6809/ 6502
R/W
Θ OR E
A15
A0
7 D0
ADDRESS BUS
ADDRESS
DECODE
DATA BUS
*
CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR CONNECT LOAD TO V
6821 6521
C32 R/W
E DB7 DB0
FOR 2-WIRE MODE
DD
PA0 PA1
PA2 PA3
SCL
MAX500
SDA
LDAC
. .
LOAD*
TOP VIEW
V
REF
AGND
N.C. N.C.
V
A/B
___________________Chip Topography____Pin Configurations (continued)
V
B
A
OUT
OUT
V
V
3
2
SS
5 6 7 8
9
DGND
MAX500
10
LDAC
N.C.
1
11
SDA
C
OUT
V
20
12
LOAD
D
OUT
V
19
13
SCL
184 17 16 15 14
V
DD
V
REF
V
REF
SRO N.C.
V
ss
B
V
REF
A
V
REF
C D
AGND
LCC
V
OUT
DGND
OUT
A
0.150"
(3.810mm)
B
V
SDA
LDAC
OUT
V
OUT
C
LOAD
D
SCL
V
DD
V
C
REF
V
D
REF
0.159"
(4.039mm)
SRO
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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