The MAX500 is a quad, 8-bit, voltage-output digital-toanalog converter (DAC) with a cascadable serial interface. The IC includes four output buffer amplifiers and
input logic for an easy-to-use, two- or three-wire serial
interface. In a system with several MAX500s, only one
serial data line is required to load all the DACs by cascading them. The MAX500 contains double-buffered
logic and a 10-bit shift register that allows all four DACs
to be updated simultaneously using one control signal.
There are three reference inputs so the range of two of
the DACs can be independently set while the other two
DACs track each other.
The MAX500 achieves 8-bit performance over the full
operating temperature range without external trimming.
________________________Applications
Minimum Component Count Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Arbitrary Function Generators
Automatic Test Equipment
________________Functional Diagram
V
C
REF
V
A/B
V
DAC A
REF
D
V
A
OUT
REF
SRO
AGND
DGND V
INPUT
REG A
V
LDAC
DD
SS
DAC
REG A
____________________________Features
♦ Buffered Voltage Outputs
♦ Double-Buffered Digital Inputs
♦ Microprocessor and TTL/CMOS Compatible
♦ Requires No External Adjustments
♦ Two- or Three-Wire Cascadable Serial Interface
♦ 16-Pin DIP/SO Package and 20-Pin LCC
♦ Operates from Single or Dual Supplies
______________Ordering Information
PART
MAX500ACPE
MAX500BCPE
MAX500ACWE
MAX500BCWE
MAX500BC/D0°C to +70°CDice*
MAX500AEPE -40°C to +85°C16 Plastic DIP
MAX500BEPE -40°C to +85°C16 Plastic DIP
MAX500AEWE
MAX500BEWE
MAX500AEJE -40°C to +85°C16 CERDIP
MAX500BEJE -40°C to +85°C16 CERDIP
MAX500AMJE
MAX500BMJE
MAX500AMLP
MAX500BMLP
MAX500_C_ _ ....................................................0°C to + 70°C
MAX500_E_ _...................................................-40°C to +85°C
MAX500_M_ _................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
Note 1: The outputs may be shorted to AGND, provided that the power dissipation of the package is not exceeded.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Typical short-circuit current to AGND is 25mA
ELECTRICAL CHARACTERISTICS—Dual Supplies
(VDD= +11.4V to +16.5V, VSS= -5V ±10%, AGND = DGND = 0V, V
STATIC PERFORMANCE
Total Unadjusted Error
Relative Accuracy
Full-Scale Error
Zero-Code Error
REFERENCE INPUT
Reference Input Resistance
AC FeedthroughTA= +25°C (Notes 2, 3) -70dB
DIGITAL INPUTS
Digital Input High VoltageV
Digital Input Low VoltageV
Digital Output High VoltageV
Digital Output Low VoltageV
Digital Input CapacitanceTA= +25°C (Note 2) 8pF
VDD= 15V ±5%,
V
= 10V
REF
MAX500A
MAX500B
Guaranteed monotonic
MAX500A
MAX500B
V
REFERENCE INPUT—All specifications are the same as for dual supplies.
DIGITAL INPUTS—All specifications are the same as for dual supplies.
DYNAMIC PERFORMANCE—All specifications are the same as for dual supplies.
POWER SUPPLIES
Positive Supply Voltage
Positive Supply Current
SWITCHING CHARACTERISTICS—All specifications are the same as for dual supplies.
Note 2: Guaranteed by design. Not production tested.
Note 3: T
= +25°C, V
A
= 10kHz, 10V peak-to-peak sine wave.
REF
Note 4: LOAD has a weak internal pull-up resistor to V
Note 5: DAC switched from all 1s to all 0s, and all 0s to all 1s code.
Note 6: Sample tested at +25°C to ensure compliance.
Note 7: Slow rise and fall times are allowed on the digital inputs to facilitate the use of opto-couplers. Only timing for SCL is given
because the other digital inputs should be stable when SCL transitions.
The MAX500 has four matched voltage-output digital-toanalog converters (DACs). The DACs are “inverted”
R-2R ladder networks which convert 8 digital bits into
equivalent analog output voltages in proportion to the
applied reference voltage(s). Two DACs in the MAX500
have a separate reference input while the other two
DACs share one reference input. A simplified circuit
diagram of one of the four DACs is provided in Figure 1.
R
…
RR
SUPPLY CURRENT
vs. TEMPERATURE
I
DD
I
SS
25-2507550100
TEMPERATURE (°C)
V
OUT
ZERO-CODE ERROR
2.0
1.5
MAX500-02
1.0
0.5
0.0
-0.5
-1.0
ZERO-CODE ERROR (mV)
-1.5
-2.0
-5512525-2507550100
of the V
inputs is code dependent. The lowest
REF
value, approximately 11kΩ (5.5kΩ for V
vs. TEMPERATURE
V
OUT
VSS = -5V
TEMPERATURE (°C)
V
A
OUT
V
B
OUT
V
C
OUT
D
A/B), occurs
REF
when the input code is 01010101. The maximum value
of infinity occurs when the input code is 00000000.
Because the input resistance at V
is code depen-
REF
dent, the DAC’s reference sources should have an output impedance of no more than 20Ω (no more than
10Ω for V
A/B). The input capacitance at V
REF
REF
also code dependent and typically varies from 15pF to
35pF (30pF to 70pF for V
V
OUT
C, and V
D can be represented by a digitally
OUT
REF
A/B). V
OUT
A, V
OUT
programmable voltage source as:
V
OUT
= Nbx V
REF
/ 256
where Nbis the numeric value of the DAC’s binary
input code.
MAX500
MAX500-03
is
B,
2R2R2R2R
2R
DB0
DB0DB5DB6DB7
V
REF
AGND
…
…
DB5
DB6
DB7
Figure 1. Simplified DAC Circuit Diagram
The voltage at the V
V
pins (pins 4, 12, and 13) sets
REF
REF
Input
the full-scale output of the DAC. The input impedance
All voltage outputs are internally buffered by precision
unity-gain followers, which slew at greater than 3V/µs.
When driving 2kΩ in parallel with 100pF with a full-scale
transition (0V to +10V or +10V to 0V), the output settles
to ±1/2LSB in less than 4µs. The buffers will also drive
2kΩ in parallel with 500pF to 10V levels without oscillation. Typical dynamic response and settling performance of the MAX500 is shown in Figures 2 and 3.
A simplified circuit diagram of an output buffer is
shown in Figure 4. Input common-mode range to
AGND is provided by a PMOS input structure. The output circuitry incorporates a pull-down circuit to actively
drive V
(VSS). The buffer circuitry allows each DAC output to
to within +15mV of the negative supply
OUT
5
CMOS, Quad, Serial-Interface
8-Bit DAC
POSITIVE STEP
= -5V or 0V)
(V
SS
MAX500
1µs/div
Figure 2. Positive and Negative Settling Times
DYNAMIC RESPONSE
= -5V or 0V)
(V
SS
LDAC
5V/div
OUTPUT
100mV/div
LDAC
5V/div
OUTPUT
5V/div
INPUT
(5V/div)
OUTPUT
(20mV/div)
V
DD
FROM
INVERTED
OUTPUT
DAC
(+)
INPUTS
PMOS
NEGATIVE STEP
= -5V or 0V)
(V
SS
1µs/div
(-)
C
C
LDAC
5V/div
OUTPUT
100mV/div
FOLLOWER
NPN
EMITTER
PULL-UP
V
OUT
2µs/div
Figure 3. Dynamic Response
V
SS
Figure 4. Simplified Output Buffer Circuit
sink, as well as source up to 5mA. This is especially
important in single-supply applications, where VSSis
connected to AGND, so that the zero error is kept at or
under 1/2LSB (V
Current vs. Output Voltage is shown in the
Operating Characteristics
= +10V). A plot of the Output Sink
REF
section.
Typical
Digital Inputs
and Interface Logic
The digital inputs are compatible with both TTL and 5V
CMOS logic; however, the power-supply current (IDD)
is somewhat dependent on the input logic level. Supply
current is specified for TTL input levels (worst case) but
is reduced (by about 150µA) when the logic inputs are
driven near DGND or 4V above DGND.
Do not drive the digital inputs directly from CMOS logic
running from a power supply exceeding 5V. When driv-
ing SCL through an opto-isolator, use a Schmitt trigger
to ensure fast SCL rise and fall times.
The MAX500 allows the user to choose between a
3-wire serial interface and a 2-wire serial interface.
The choice between the 2-wire and the 3-wire interface is set by the LOAD signal. If the LOAD is allowed
to float (it has a weak internal pull-up resistor to VDD),
the 2-wire interface is selected. If the LOAD signal is
kept to a TTL-logic high level, the 3-wire interface
is selected.
3-Wire Interface
The 3-wire interface uses the classic Serial Data (SDA),
Serial Clock (SCL), and LOAD signals that are used
in standard shift registers. The data is clocked in on
the falling edge of SCL until all 10 bits (8 data bits and
2 address bits) are entered into the shift register.
A low level on LOAD line initiates the transfer of data
from the shift register to the addressed input register.
The data can stay in this register until all four of the
input registers are updated. Then all of the DAC registers can be simultaneously updated using the LDAC
(load DAC) signal. When LDAC is low, the input register’s data is loaded into the DAC registers (see Figure 5
for timing diagram). This mode is cascadable by con-
MAX500
necting Serial Output (SRO) to the second chip’s SDA
pin. The delay of the SRO pin from SCL does not cause
setup/hold time violations, no matter how many
MAX500s are cascaded. Restrict the voltage at LDAC
and LOAD to +5.5V for a logic high.
2-Wire Interface
The 2-wire interface uses SDA and SCL only. LOAD
must be floating or tied to VDD. Each data frame (8 data
bits and 2 address bits) is synchronized by a timing
relationship between SDA and SCL (see Figure 6 for
the timing diagram). Both SDA and SCL should normally be high when inactive. A falling edge of SDA (while
SCL is high) followed by a falling edge of SCL (while
SDA is low) is the start condition. This always loads a 0
into the first bit of the shift register. The shift register is
extended to 11 bits so this “data” will not affect the
input register information. The timing now follows the 3wire interface, except the SDA line is not allowed to
change when SCL is high (this prevents the MAX500
from retriggering its start condition). After the last data
bit is entered, the SDA line should go low (while the
SCL line is low), then the SCL line should rise followed
by the SDA line rising. This is defined as the stop condition, or end of frame.
Cascading the 2-wire interface can be done, but the
user must be careful of both timing and formatting.
Timing must take into account the intrinsic delay of the
SRO pin from the internally generated start/stop conditions. The tS2value should be increased by n times t
(where n = number of cascaded MAX500s). The t
value should also be increased by n times tD1. No other
timing parameters need to be modified. A more serious
concern is one of formatting. Generally, since each
frame has a start/stop condition, each chip that has
data cascaded through it will accept that data as if it
were its own data. Therefore, to circumvent this limitation, the user should not generate a stop bit until all
DACs have been loaded. For example, if there are
three MAX500s cascaded in the 2-wire mode, the data
transfer should begin with a start condition, followed by
10 data bits, a zero bit, 10 data bits, a zero bit, 10 data
bits, and then a stop condition. This will prevent each
MAX500 from decoding the middle data for itself.
D1
LDS
The data is entered into the shift register in the following order:
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
(First) (MSB) (Last)
where address bits A1 and A0 select which DAC register receives data from the internal shift register. Table 1
lists the channel addresses. D7 (MSB) through D0 is
the data byte.
Since LDAC is asynchronous with respect to SCL, SDA,
and LOAD, care must be taken to assure that incorrect
data is not latched through to the DAC registers. If the
3-wire serial interface is used, LDAC can be either tied
low permanently or tied to LOAD as long as t
LDS
always maintained. However, if the 2-wire interface is
used, LDAC should not fall before the stop condition is
internally detected. (This is the reason for the t
LDS
delay of LDAC after the last rising edge of SDA.)
Table 1. DAC Addressing
A1A0SELECTED INPUT REGISTER
LLDAC A Input Register
LHDAC B Input Register
HLDAC C Input Register
HHDAC D Input Register
Table 2. Logic Input Truth Table
SCLSDALOAD LDACFUNCTION
FDataV
HDataV
LXV
FDataMH
HXMH
LXMH
HXLH
HXLL
Notes:
H = Logic High2W = 2-Wire
L = Logic Low3W = 3-Wire
M = TTL Logic HighF = Falling Edge
X = Don’t Care
DD
DD
DD
Latching data into
H
shift register (2W)
Data should not be
H
changing (2W)
Data is allowed to
H
change (2W)
Latching data into
shift register (3W)
Data is allowed to
change (3W)
Data is allowed to
change (3W)
Loads input register
from shift register (3W)
DAC register reflects
data held in their respective
input registers
The SRO output swings from VDDto DGND. Cascading
to other MAX500s poses no problem. If SRO is used to
drive a TTL-compatible input, use a clamp diode
between TTL +5V and VDDand the current-limiting
resistor to prevent potential latchup problems with
the 5V supply.
Table 2 shows the truth table for SDA, SCL, LOAD, and
LDAC operation. Figures 5 and 6 show the timing diagrams for the MAX500.
__________Applications Information
Power-Supply and Reference
Operating Ranges
The MAX500 is fully specified to operate with V
between +12V ±5% and +15V ±10% (+11.4V to
+16.5V), and with VSSfrom 0V to -5.5V. 8-bit performance is also guaranteed for single-supply operation
(VSS= 0V), however, zero-code error is reduced when
VSSis -5V (see
Output Buffer Amplifiers
section).
For an adequate DAC and buffer operating range, the
V
voltage must always be at least 4V below VDD.
REF
The MAX500 is specified to operate with a reference
input range of +2V to VDD- 4V.
Ground Management
Digital or AC transient signals between AGND and
DGND will create noise at the analog outputs. It is recommended that AGND and DGND be tied together at
the DAC and that this point be tied to the highest quality ground available. If separate ground buses are used,
then two clamp diodes (1N914 or equivalent) should be
connected between AGND and DGND to keep the two
DD
ground buses within one diode drop of each other. To
avoid parasitic device turn-on, AGND must not be
allowed to be more negative than DGND. DGND should
be used as supply ground for bypassing purposes.
REFERENCE INPUTS
12414
13
V
D
CV
REF
REF
DAC A
DAC B
V
SS
3
AGND
DIGITAL
INPUTS
NOT
SHOWN
MAX500
REF
A/B
V
DAC C
DAC D
-5V (OR GND)
Figure 8. MAX500 Unipolar Output Circuit
+15V
V
DD
2
V
A
OUT
1
V
B
OUT
16
V
C
OUT
15
V
D
OUT
DGND
56
MAX500
SYSTEM GND
B
V
OUT
V
A
OUT
V
SS
V
A/B
REF
AGND
DGND
COMPONENT SIDE (TOP VIEW)
Figure 7. Suggested MAX500 PC Board Layout for
Minimizing Crosstalk
Careful PC board ground layout techniques should be
used to minimize crosstalk between DAC outputs, the
reference input(s), and the digital inputs. This is particularly important if the reference is driven from an AC
source. Figure 7 shows suggested PC board layouts for
minimizing crosstalk.
Unipolar Output
In unipolar operation, the output voltages and the reference input(s) are the same polarity. The unipolar circuit
configuration is shown in Figure 8 for the MAX500. The
device can be operated from a single supply with a
slight increase in zero error (see
Amplifiers
the voltage at V
respect to AGND. The unipolar code table is given in
Table 3.
section). To avoid parasitic device turn-on,
must always be positive with
REF
129
(––––)
REF
256
128
(––––)= +
256 2
127
(––––)
REF
256
1
(––––)
REF
256
Output Buffer
V
REF
––––
DAC CONTENTS
MSBLSB
1 1 1 11 1 1 1
1 0 0 0
1 0 0 00 0 0 00V
0 1 1 11 1 1 1
0 0 0 00 0 0 1
0 0 0 00 0 0 0
Note: 1LSB = (V
+
V
IN
5
+
V
BIAS
-
DIGITAL INPUTS NOT SHOWN
Figure 10. AGND Bias Circuit
) (2-8) = +V
REF
AGND
-5V (OR GND)
0 0 0 1
4
V
DAC A
V
SS
3
REF
A/B
MAX500
REF
1
(–––)
256
+15V
DGND
-V
14
V
DD
6
ANALOG
OUTPUT
+V
REF
+V
REF
-V
REF
-V
REF
128
(––––) = -V
REF
128
127
(––––)
128
1
(––––)
128
1
(––––)
128
127
(––––)
128
REF
2
V
A
OUT
Bipolar Output
Each DAC output may be configured for bipolar operation using the circuit in Figure 9. One op amp and two
resistors are required per channel. With R1 = R2:
V
= V
OUT
where DAis a fractional representation of the digital
word in Register A.
Table 4 shows the digital code versus output voltage
for the circuit in Figure 9.
REF
(2DA- 1)
AGND can be biased above DGND to provide an arbitrary nonzero output voltage for a “zero” input code. This
is shown in Figure 10. The output voltage at V
V
OUT
A = V
BIAS
+ DAV
where DAis a fractional representation of the digital
input word. Since AGND is common to all four DACs,
all outputs will be offset by V
Since AGND current is a function of the four DAC
Offsetting AGND
IN
in the same manner.
BIAS
codes, it should be driven by a low-impedance source.
V
In applications where V
the MAX500 has multiplying capability within the limits
of the V
input range specifications. Figure 11 shows
REF
a technique for applying a sine-wave signal to the reference input, where the AC signal is biased up before
being applied to V
REF
than 0.1% with input frequencies up to 50kHz, and the
typical -3dB frequency is 700kHz. Note that V
never be more negative than AGND.
The performance of the MAX500 is specified for both
dual and single-supply (VSS= 0V) operation. When the
improved performance of dual-supply operation is
desired, but only a single supply is available, a -5V V
supply can be generated using an ICL7660 in one of
the circuits of Figure 12.
has AC signal components,
REF
. Output distortion is typically less
must
REF
Generating V
SS
SS
Digital Interface Applications
Figures 13 through 16 show examples of interfacing the
MAX500 to most popular microprocessors.
12V to 15V
10k
6V
ZENER
2N2222
8
10k10µF
3
10µF
2
CAP+CAP-
V+
ICL7660
GND
4
5
V
OUT
+15V
15k
AC
REFERENCE
INPUT
+4V
DIGITAL INPUTS NOT SHOWN
10k
-4V
4
V
DAC B
SS
36
-5V (OR GND)
Figure 11. AC Reference Input Circuit
10µF
2
CAP+CAP-
8
V+
ICL7660
3
GND
10µF
-5V
+5V
LOGIC
SUPPLY
OUT
V
SS
REF
A/B
AGND
4
V
OUT
MAX500
14
V
DD
V
V
OUT
MAX500
DGNDV
5
5
-5V
10µF
B
B
OUT
1
OUT
V
SS
Figure 12. Generating -5V for V
80C51
P1.0
P1.1
P1.2
. . . . . . .
P1.3
*
CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR
CONNECT LOAD TO VDD FOR 2-WIRE MODE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
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