The MAX4399 audio/video switch is ideal for digital settop box applications. The MAX4399 provides video and
audio routing from the MPEG decoder source to the TV,
VCR, and AUX SCART (peritelevision) connectors. In
addition, the TV audio channel features clickless
switching and programmable volume control from
-56dB to +6dB in 2dB steps. The device can mix an
auxiliary audio tone into the TV audio channel and can
mix the stereo audio signal into a mono audio signal.
The MAX4399 directly drives an external RF modulator
with a composite video with blanking and sound
(CVBS) signal created by an on-chip luma/chroma
(Y/C) mixer and external RLC trap filter. The MAX4399
features a fast-mode I2C™-compatible 2-wire interface
allowing communication at data rates up to 400kbps.
The MAX4399 operates with standard +5V and +12V
single supplies and supports slow and fast switching.
All video and audio inputs are AC-coupled. The DC
biases of all input and output signals are set to predefined levels. All video outputs, including the RF modulator, drive standard 150Ω loads. Red, green, and
blue (RGB) outputs feature a programmable gain of
+6dB ±1dB. All other video outputs have a fixed +6dB
gain. The VCR and AUX audio output gains are programmable for -6dB, 0dB, and +6dB.
The MAX4399 is available in a compact 68-pin thin
QFN package and is specified for the 0°C to +70°C
commercial temperature range. The MAX4399 evaluation kit is available to help speed designs.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltages
V_VID to G_VID .....................................................-0.3V to +6V
V12 to G_AUD .....................................................-0.3V to +14V
V_DIG to G_DIG ....................................................-0.3V to +6V
G_AUD to G_DIG ...............................................-0.1V to +0.1V
G_VID to G_DIG .................................................-0.1V to +0.1V
G_AUD to G_VID ................................................-0.1V to +0.1V
Video Inputs, Video Outputs, ENC_FS_IN, VCR_FS_IN,
VID_BIAS, TRAP ................................-0.3V to (V
V_VID
+ 0.3V)
V_AUD to G_AUD................................................-0.3V to +9V
Audio Inputs, Audio Outputs,
AUD_BIAS........................................-0.3V to (V
V_AUD
+ 0.3V)
SDA, SCL, DEV_ADDR, INTERRUPT_OUT .........-0.3V to +6V
AUX_SS, TV_SS, VCR_SS ....................-0.3V to (V
= 5V, 0.47µF ceramic X5R capacitor in parallel with a 10µF aluminum electrolytic capacitor from
V_AUD to G_AUD, no load, T
A
= +25°C, unless otherwise noted.)
INPUT CLAMP CURRENT
vs. INPUT VOLTAGE
MAX4399 toc19
INPUT VOLTAGE (V)
INPUT CLAMP CURRENT (mA)
4321
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
05
OUTPUT BIAS VOLTAGE
vs. TEMPERATURE
MAX4399 toc20
TEMPERATURE (°C)
OUTPUT BIAS VOLTAGE (V)
5025
0.5
1.0
1.5
2.0
2.5
0
075
RGB, LUMA, CVBS
CHROMA
PINNAMEFUNCTION
1V_DIGDigital Supply Voltage. Connect to 5V.
2DEV_ADDR
Device Address Set Input. Connect to G_DIG to set write and read addresses of 94h and 95h,
respectively. Connect to V_DIG to set write and read addresses of 96h and 97h, respectively.
3SDABidirectional Data I/O. I2C-compatible, 2-wire interface data input/output. Output is open drain.
Interrupt Output. INTERRUPT_OUT is an open-drain output that goes high impedance to
indicate a change in the slow switch lines, AUX_SS, TV_SS, or VCR_SS.
Audio Input Bias Voltage. Bypass AUD_BIAS with a 10µF capacitor and a 0.1µF capacitor to
G_AUD.
Audio Supply Voltage. Connect all V_AUD together. An on-board linear regulator creates the
11, 22, 30V_AUD
12AUX_L_INAUX SCART Left-Channel Audio Input
13AUX_R_INAUX SCART Right-Channel Audio Input
14VCR_R_INVCR SCART Right-Channel Audio Input
15VCR_L_INVCR SCART Left-Channel Audio Input
16TV_R_INTV SCART Right-Channel Audio Input
+8V audio supply voltage from V12. Bypass pin 30 with a 10µF aluminum electrolytic capacitor
in parallel with a 0.47µF low-ESR ceramic capacitor to audio ground, and bypass pins 11 and
22 with 0.1µF capacitors to audio ground.
31V12+12V Supply. Bypass V12 with a 10µF capacitor in parallel with a 0.1µF capacitor to ground.
32AUX_SSAUX SCART Bidirectional Slow-Switch Signal
33TV_SSTV SCART Bidirectional Slow-Switch Signal
34VCR_SSVCR SCART Bidirectional Slow-Switch Signal
Trap Filter. Connect a series RLC trap filter to eliminate the color subcarrier frequency
35TRAP
36, 42, 50G_VIDVideo Ground
37TV_FS_OUT
38, 46, 61V_VID
39RF_CVBS_OUTRF Modulator Composite Video Output. Internally biased at 1.0V.
40TV_Y/CVBS_OUTTV SCART Luma/Composite Video Output. Internally biased at 1.0V.
41TV_R/C_OUT
43TV_G_OUTTV SCART Green Video Output. Internally biased at 1.0V.
44TV_B_OUTTV SCART Blue Video Output. Internally biased at 1.0V.
45AUX_R/C_OUT
47AUX_Y/CVBS_OUT AUX SCART Luma/Composite Video Output. Internally biased at 1.0V.
48VCR_Y/CVBS_OUT VCR SCART Luma/Composite Video Output. Internally biased at 1.0V.
49VCR_R/C_OUT
51VID_BIAS
52TV_R/C_INTV SCART Red/Chroma Video Input. Internally biased at 1.22V for red, or 1.8V for chroma.
(4.43MHz) from the luma signal. The filter prevents cross-mixing of the color subcarriers when
the luma and chroma signals are added together to form a composite signal. Internally biased
at +0.5V.
TV SCART Fast-Switching Output. This signal is used to switch the TV to its RGB inputs for onscreen display purposes.
Video Supply. Bypass each V_VID with a 0.01µF capacitor to V_GND. Connect a 200nH ferrite
bead from V_VID to a 5V supply.
TV SCART Red/Chroma Video Output. Internally biased at 1.0V for red video signal and 2.1V
for chroma video signal.
AUX SCART Red/Chroma Video Output. Internally biased at 1.0V for red video signal and 2.1V
for chroma video signal.
VCR SCART Red/Chroma Video Output. Internally biased at 1.0V for red video signal and 2.1V
for chroma video signal.
Video Bias Voltage Output. VID_BIAS sets video bias level for chroma signals. Bypass
VID_BIAS with a low-ESR 0.1µF capacitor to G_VID.
MAX4399
Detailed Description
The MAX4399 audio/video switch matrix connects audio
and video signals between different ports. In the case of
a set-top box, the ports consist of the MPEG decoder
and three SCART connectors. For DVD+RW recorders
and some televisions, the ports consist of the main
board, front panel, tuner, and two SCART connectors.
The video section consists of input buffers, a crosspoint
switch, and output drivers that can be disabled. There
is also a mixer, which creates a composite video signal
from S-video. The video inputs can be set in either
clamp or bias mode. The red/chroma outputs have pulldowns that connect the outputs to video ground as
described in the Video Inputs section.
The audio section features input buffers, a crosspoint
switch, and output drivers. The TV audio path has volume control from -56dB to +6dB in 2dB steps. The VCR
and AUX audio paths have volume control from -6dB to
+6dB in 6dB steps. The MAX4399 can be configured to
switch inputs during a zero crossing to reduce clicks.
The MAX4399 can also switch volume levels during a
zero crossing to reduce zipper noise. The audio outputs can operate in different modes. For instance, left
and right audio channels can be swapped (see the
Audio Outputs section).
The MAX4399 has two fast-switching inputs and one
fast-switching output. Fast switching is used for creating on-screen displays by switching between the CVBS
and RGB signals. Under I
2
C-compatible control, the
fast-switching output can follow either of the fastswitching inputs or be set high or low.
The MAX4399 features three slow-switching input/outputs to support slow switching, which sets the screen
aspect ratio or video source of the display device. The
slow switching relies on tri-level logic in which the levels
are 0V, 6V, and 12V. The status of the slow-switching
input is continuously read and stored in register 0Eh. If
INTERRUPT_OUT is enabled, then INTERRUPT_OUT
changes to a high-impedance state if any of the slowswitching inputs change logic levels. The slow-switching
outputs can be set to a logic level or high impedance by
writing to registers 07h, 09h, or 0Bh.
The MAX4399 can be configured through an I
2
C-compatible interface. DEV_ADDR sets the I2C-compatible
address.
SCART Video Switching
The MAX4399 triple SCART audio/video switch
includes multiplexed video amplifiers and a Y-C mixerdriver with a trap filter to drive an RF modulator. The
MAX4399 switches video from an MPEG decoder output and TV, VCR, and AUX SCART connectors.
53TV_Y/CVBS_INTV SCART Luma/Composite Video Input. Internally biased at 1.22V.
54AUX_R/C_INAUX SCART Red/Chroma Video Input. Internally biased at 1.22V for red, or 1.8V for chroma.
55AUX_Y/CVBS_INAUX SCART Luma/Composite Video. Internally biased at 1.22V.
56VCR_Y/CVBS_INVCR SCART Luma/Composite Video Input. Internally biased at 1.22V.
57VCR_FS_INVCR SCART Fast-Switching Input
58VCR_R/C_INVCR SCART Red/Chroma Video Input. Internally biased at 1.22V for red, or 1.8V for chroma.
59VCR_G_INVCR SCART Green Video Input. Internally biased at 1.22V.
60VCR_B_INVCR SCART Blue Video Input. Internally biased at 1.22V.
62ENC_Y/CVBS_INDigital Encoder Luma/Composite Video Input. Internally biased at 1.22V.
63ENC_R/C_IN
64ENC_G_INDigital Encoder Green Video Input. Internally biased at 1.22V.
65ENC_B_INDigital Encoder Blue Video Input. Internally biased at 1.22V.
66ENC_Y_INDigital Encoder Luma Video Input. Internally biased at 1.22V.
67ENC_C_INDigital Encoder Chroma Video Input. Internally biased at 1.8V.
68ENC_FS_INDigital Encoder Fast-Switching Input
Digital Encoder Red/Chroma Video Input. Internally biased at 1.22V for red, or 1.8V for
chroma.
The inputs and outputs are grouped by SCART connectors: TV, VCR, and AUX. While the SCART connector
supports RGB, S-video, and composite formats, RGB
and S-video share a bidirectional set of SCART connector pins. The MAX4399 supports connection of auxiliary
devices (DVD players, DVD+R/W recorders, game consoles, camcorders, etc.) by including full I/O support for
an auxiliary (AUX) SCART connector.
Video Inputs
All of the video amplifier inputs are AC-coupled with an
external 0.1µF capacitor. Either a clamp or bias circuit
sets the DC input level of the video signals. The clamp
circuit positions the sync tip of the CVBS, RGB, or luma
(S-VHS) signals. If the signal does not have sync, then
the clamp positions the minimum of the signal at the
clamp voltage. The bias circuit positions the chroma signal (S-VHS) at its midlevel. On the video inputs that can
receive either a chroma or a red video signal, the 2-wire
interface sets whether the clamp or bias circuit is active.
Red/chroma signals, such as TV_R/C_OUT signals are
bidirectional. When the red/chroma signal is being
used as an input, then the red/chroma output must connect the 75Ω back-termination resistor to ground, as
shown in Figure 1, so the transmitting device can see
the proper termination on the receiving side. The
MAX4399 provides an active pulldown to G_VID on all
red/chroma outputs (AUX_R/C_OUT, TV_R/C_OUT, and
VCR_R/C_OUT).
The MPEG decoder and VCR uses the RGB format to
insert an on-screen display (OSD), usually text, onto the
TV. A fast-switching signal controls whether the RGB
signals or composite video signal appear on the TV.
The MAX4399 supports RGB as an input from either the
VCR or the MPEG decoder and as an output only to the
TV. The red video signal of the RGB format and the
chroma video signal of the S-VHS format share the
same SCART connector pin; therefore RGB signals and
S-VHS signals cannot be present at the same time.
Loop-through is possible with a composite video signal
but not with RGB signals because the RGB SCART pins
are used for both input and output.
The VCR, MPEG decoder, auxiliary device, and TV use
the S-VHS format, which is the high-quality format for the
home today. The MAX4399 supports S-VHS as an input
from the VCR, MPEG decoder, auxiliary device, and TV,
and as a separately switchable output to the TV, VCR,
and AUX SCART connectors. Because S-VHS support
was not included in the original specification of the
SCART connector, the Y signal of S-VHS and the CVBS
signal share the same SCART connector pins. If S-VHS
is present, then a composite signal must be created
from the Y and C signals to drive the legacy
RF_CVBS_OUT output. The circuit is shown as a summing point with bias in Figure 2. The MAX4399 sums Y
and C to get CVBS, and the bias provides the DC levels
for offsetting the chroma signal. Again, loop-through is
not possible with S-VHS because the chroma SCART
pin is used for both input and output.
The MAX4399 supports the CVBS format, with inputs
from the VCR, MPEG decoder, TV, and auxiliary device.
Full loop-through is possible to all devices except the
MPEG decoder because the SCART connector has
separate input and output pins for the CVBS format.
Slow Switching
The MAX4399 supports the tri-level slow switching of
IEC 933-1, Amendment 1, which selects the aspect ratio
for the display device. Under I2C-compatible control,
the MAX4399 sets the slow-switching output levels. Table
1 shows the valid output levels of the slow-switching
signal and the corresponding operating modes of the
display device.
The slow-switching SCART pins are bidirectional. The
MAX4399 can set the slow-switch output drivers to highimpedance mode to receive signals. When enabled,
INTERRUPT_OUT becomes high impedance if the
voltage level changes on TV_SS, VCR_SS, or AUX_SS.
The VCR or MPEG decoder outputs a fast-switching
signal to the display device. The fast-switching signal
can also be set to a constant high or low through the 2wire interface. The pass-through delay from VCR to TV
or MPEG decoder to TV matches that of the RGB signals facilitating proper OSD insertion.
Video Outputs
The DC level at the video outputs is controlled so coupling capacitors are not required, and all of the video
outputs are capable of driving a 150Ω, back-terminated
coax load directly with respect to ground. Since some
televisions and VCRs use the horizontal sync height for
automatic gain control, the MAX4399 accurately reproduces the sync height to within ±2%.
Y/C Mixer and Trap Filter
The MAX4399 includes an on-chip mixer to produce
CVBS from Y and C. The Y signal input to the mixer has
an external trap filter connection, TRAP, to eliminate the
color subcarrier frequency (4.43MHz), preventing
cross-mixing of the subcarriers in the mixer. TRAP is
internally biased at 0.5V. Connect a series RLC filter to
G_VID, or leave TRAP unconnected if not used.
SCART Audio Switching
Audio Inputs
The audio block has four stereo audio inputs from the TV,
VCR, and AUX SCART connectors, plus the MPEG
decoder. Additionally, the MAX4399 provides a satellite
tone input. Each input has a 100kΩ resistor connected to
an internally generated voltage equal to 0.5 x V_AUD.
There are three main sections—the TV channel, the VCR
channel, and the AUX channel.
Audio Outputs
Each channel has a stereo output and the TV channel
has an additional phono output and a mono output. The
phono outputs always follow the TV audio input selection. The mono output, a mix of the TV right and left
channels, drives the channel 3/4 RF modulator. The
three stereo outputs can be configured to normal
mode, swap mode, mono, both channels to right input,
and both channels to left input. The latter two modes
are useful if the left audio channel carries one language
and the right audio channel carries another language.
The phono output is ideal for connection to a hi-fi, and
carries the same signals as the TV output when
switched to normal mode.
The mono mixer, a resistor summer, attenuates the
amplitude of each of the two signals by 6dB. The 3dB
gain block, which follows the mono mixer (Figures 3
and 4), is a compromise between a 0dB gain block and
a 6dB gain block. If the left and right audio channels
were completely uncorrelated, then a 6dB gain block
could be used. If the left and right channels were completely correlated, then a 0dB block would have to be
used. In reality, most stereo audio channels are partially correlated and hence a 3dB gain block was used.
The TV channel incorporates a zero-crossing detect
(ZCD) circuit that minimizes click noise due to abrupt
signal level changes that occur when switching between
audio signals at an arbitrary moment in time.
To implement the zero-cross function when switching
audio signals, set the ZCD bit by loading register 00h
through the I2C-compatible interface (if the ZCD bit is
not already set). Then set the mute bit high by loading
register 00h. Next, wait for a period of time long enough
for the audio signal to cross zero. This period is a function of the audio signal path’s low frequency 3dB corner (f
L3dB
). For example, if f
L3dB
= 20Hz, the time
period to wait for zero cross is 1/20Hz or 50ms. Next,
set the appropriate TV switches using register 01h.
Finally, clear the mute bit (while leaving the ZCD bit
high) using register 00h. The MAX4399 switches the
signal out of mute at the next zero crossing.
To implement the zero-cross function for TV volume
changes, or for TV and phono volume bypass switching, simply ensure the ZCD bit in register 00h is set.
Volume Control
The TV channel volume control ranges from -56dB to
+6dB in 2dB increments. The VCR and AUX volume
control settings are programmable for -6dB, 0dB, and
+6dB. With the ZCD bit set, the TV volume control
switches only at zero crossings, thus minimizing click
noise. The TV outputs can bypass the volume control.
While the phono outputs always follow the TV audio
input selection, the phono outputs can either be
processed through the TV volume control or they can
bypass the TV volume control.
Digital Section
Serial Interface
The MAX4399 uses a simple 2-wire serial interface
requiring only two I/O lines (2-wire bus) of a standard
microprocessor (µP) port. The fast-mode I2C-compatible serial interface allows communication at data rates
up to 400kbps. Figure 5 shows the timing diagram for
signals on the 2-wire bus.
The two bus lines (SDA and SCL) must be high when the
bus is not in use. The MAX4399 is a slave device and
must be controlled by a bus master device. Figure 6
shows a typical application where multiple devices can
be connected to the bus provided they have different
address settings. External pullup resistors are not necessary on these lines (when driven by push-pull drivers),
though the MAX4399 can be used in applications where
pullup resistors are required to maintain compatibility
with existing circuitry. The serial interface operates at
SCL rates up to 400kHz. The SDA state is allowed to
change only while SCL is low, with the exception of
START and STOP conditions as shown in Figure 7.
SDA’s state is sampled, and therefore must remain stable while SCL is high. Data is transmitted in 8-bit bytes.
Nine clock cycles are required to transfer each byte to
the MAX4399. Release SDA during the 9th clock cycle
as the selected device acknowledges the receipt of the
byte, by pulling SDA low during this time. A series
resistor on the SDA line may be needed if the master’s
output is forced high while the selected device
acknowledges (Figure 6).
The MAX4399 is compatible with existing I2C systems.
SCL and SDA are high-impedance inputs. SDA has an
open drain that pulls the data line low during the 9th
clock pulse. Figure 8 shows a typical I2C interface
application. The communication protocol supports the
standard I2C 8-bit communications. The general call
address is ignored, and CBUS formats are not supported.
The MAX4399 address is compatible with the 7-bit I2C
addressing protocol only. No 10-bit formats are supported. RESTART protocol is supported, but an immediate
STOP condition is necessary to update the MAX4399.
Digital Inputs and Interface Logic
The I2C-compatible, 2-wire interface has logic levels
defined as VOL= 0.8V and VOH= 2.0V. All of the inputs
include Schmitt-trigger buffers to accept slow-transition
interfaces. The digital inputs are compatible with 3V
CMOS logic levels.
INTERRUPT_OUT Signal
INTERRUPT_OUT is an open-drain output that
becomes high impedance when a change in any of the
slow-switch signals occurs. Clear INTERRUPT_OUT by
setting bit 3 of register 04h low.
Data Format of the 2-Wire Interface
Write mode
Read mode
Where S = Start Condition, A = Acknowledge, P = Stop
Condition.
Figure 6. Multiple Devices Controlled by a 2-Wire Interface
Figure 7. Start and Stop Conditions on a 2-Wire Interface
Figure 8. A Typical I2C Interface Application
V
DD
µ
C
SDASCL
SCL
RS*
SDA
SCL
OTHER DEVICE #1
SDA
SCL
OTHER DEVICE #2
SDA
RS* IS OPTIONAL.
MAX4399
V_DIG
V
V
DD
DD
SDA
µ
C
SDA SCL
SCL
SDA
SCL
OTHER DEVICE #1
SDA
SCL
OTHER DEVICE #2
SDA
V_DIG
MAX4399
V
V
V
DD
DD
DD
SCL
START CONDITION
STOP CONDITION
Slave
S
Address
Slave
S
Address
A
A
Register
Address
Register
Address
ADataAP
ADataAP
MAX4399
2-Wire Interface Slave Address
Programming
Connect DEV_ADDR to G_DIG or V_DIG to set the
MAX4399 write and read addresses as shown in Table 2.
Data Register Writing and Reading
Program the SCART video and audio switches by writing to registers 00h through 0Dh (Tables 3 through 18).
Registers 00h through 0Dh can also be read, allowing
read-back of data after programming and facilitating
system debugging. The status register is read-only and
can be read from address 0Eh (Table 19).
Applications Information
Filtering of Encoder Outputs
The DAC outputs of encoder chips need to be
processed through a lowpass filter (reconstruction filter)
to attenuate out-of-band noise. Figure 9 shows how the
MAX7440 provides an integrated, convenient solution for
reconstruction filtering.
0Ch00hNot usedNot usedNot usedNot used Not usedNot used
0Dh00h
POR
VALUE
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
ENC_R/C_IN
Clamp
TV_R/C_IN
clamp
VCR_R/C_IN
clamp
AUX_R/C_IN
clamp
AUX_Y/CVBS_
OUT
enable
Not usedNot usedNot usedNot usedNot usedNot usedNot used
RGB gain
RF_CVBS_OUT
switch
Not usedNot usedNot used Not usedVCR video switch
Not usedNot usedNot used Not usedAUX video switch
AUX_R/C_OUT
enable
TV_Y/CVBS_
OUT switch
TV_R/C_OUT
enable
DEV_ADDR
CONNECTION
G_DIG94h95h
V_DIG96h97h
WRITE
ADDRESS
READ
ADDRESS
TV audio
mute
Phono
volume
bypass
TV video switch
Set TV slow switch
Set VCR slow switch
Set AUX slow switch
V C R_Y /
C V BS _
OU T
enab l e
TV_FB_
OUT
enable
Not used
VCR_R/
C_OUT
enable
RF_CVBS_
OUT
enable
TV G and B video
switch
TV fast switch
TV_G_OUT
enable
TV_B_OUT
Interrupt
enable
enable
TV volume
bypass
TV_R/C_OUT
ground
VCR_R/C_
OUT
ground
AUX_R/C_
OUT ground
TV_Y/CVBS_
OUT enable
Hot-Plug of SCART Connectors—Floating
Chassis Discharge
The MAX4399 features high-ESD protection on all
SCART inputs and outputs, and requires no external
transient voltage suppressor (TVS) devices to protect
against floating chassis discharge. Some set-top boxes
have a floating chassis problem in which the chassis is
not connected to earth ground. As a result, the chassis
can charge up to 500V. When a SCART cable is con-
nected to the SCART connector, the charged chassis
can discharge through a signal pin. The equivalent circuit is a 2200pF capacitor charged to 311V connected
through less than 0.1Ω to a signal pin. The MAX4399 is
soldered on the PC board when it experiences such a
discharge. Therefore, the current spike flows through
the ESD protection diodes and is absorbed by the supply bypass capacitors, which have high capacitance
and low ESR.
ALL CAPACITORS ARE 0.1µF AND ALL RESISTORS ARE 75Ω, UNLESS OTHERWISE NOTED.
AUX_R_OUT_SC
VCR_R_OUT_SC
10µF
10µF
VCR_L_OUT_SC
PHONO_R_OUT_SC
10µF
10µF
PHONO_L_OUT_SC
10µF
10µF
TV_L_OUT_SC
RF_MONO_OUT_SC
10µF
TV_R_OUT_SC
0.47µF
10µF10µF
10kΩ
10kΩ
10kΩ
+12V
TV_SS
AUX_SS
VCR_SS
To better protect the MAX4399 against excessive voltages during the cable discharge event, additional 75Ω
resistors should be placed in series with all inputs and
outputs that go to the SCART connector (Figure 10).
For harsh environments needing ±15kV protection, the
MAX4385E and MAX4386E single and quad highspeed op amps feature the industry’s first integrated
±15kV ESD protection on video inputs and outputs.
Power Supplies and Bypassing
The MAX4399 features single +5V and +12V supply
operation, and requires no negative supply. The +12V
supply provides voltage for SCART function switching,
and provides power for the internally generated audio
supply, V_AUD. Place all bypass capacitors as close
as possible to the MAX4399. Bypass V12 to ground
with a 10µF capacitor in parallel with a 0.1µF ceramic
capacitor. Connect all V_AUD pins together and
bypass pin 30 with a 10µF electrolytic capacitor in parallel with a 0.47µF low-ESR ceramic capacitor to audio
ground. Bypass V_AUD pins 11 and 22 each with a
0.1µF capacitor to audio ground. Bypass AUD_BIAS to
audio ground with a 10µF electrolytic in parallel with a
0.1µF ceramic capacitor.
Bypass V_DIG with a 0.1µF ceramic capacitor to digital
ground. Bypass each V_VID to video ground with a
0.01µF ceramic capacitor. Connect V_VID in series with
a 200nH ferrite bead to the +5V supply. Bypass the
internally generated video bias, VID_BIAS with a 0.1µF
low-ESR ceramic capacitor to G_VID.
Layout and Grounding
For optimal performance, use controlled-impedance
traces for video signal paths, and place input termination resistors and output back-termination resistors
close to the MAX4399. Avoid running video traces parallel to high-speed data lines.
The MAX4399 provides separate ground connections for
video, audio, and digital supplies. For best performance
use separate ground planes for each of the ground
returns, and connect all three ground planes together at a
single point. Refer to the MAX4399 evaluation kit for a
proven circuit board layout example.
AUX slow switch statusVCR slow switch statusTV slow switch status
TV Audio Mute
Volume Control
Zero-Crossing Detector
DESCRIPTION
76543210
———————0Off
———————1On (power-on default)
—— 00000—+6dB gain
—— 00001—+4dB gain
—— 00010—+2dB gain
—— 00011—0dB gain (power-on default)
—— 00100—-2dB gain
—— 00101—-4dB gain
—————————
—— 11110—-54dB gain
—— 11111—-56dB gain
—0——————Off
—1——————On (power-on default)
——— 00———0 (power-on default)
——— 01———Same level as ENC_FS_IN
——— 10———Same level as VCR_FS_IN
——— 11———V_VID
—— 0—————
—— 1—————
—0—————
—1—————
BIT
COMMENTS
Low (<2V) internal source (power-on
default)
Medium (4.5V to 7V). External SCART
source with 16:9 aspect ratio.
High (>9.5V). External SCART source
with 4:3 aspect ratio.
Normal operation. Pulldown on
TV_R/C_OUT is off (power-on default).
Ground. Pulldown on TV_R/C_OUT is
on. The output amplifier driving
TV_R/C_OUT turns off.
Composite video from the Y/C mixer is
output
The TV_Y/CVBS_OUT signal selected in
register 06h is output (power-on default)
Composite video from the Y/C mixer is
output (power-on default)
The TV_Y/CVBS_OUT signal selected in
register 06h is output
Low (<2V) internal source (power-on
default)
Medium (4.5V to 7V). External SCART
source with 16:9 aspect ratio.
High (>9.5V). External SCART source with
4:3 aspect ratio.
Normal operation. Pulldown on
TV_R/C_OUT is off (power-on default)
Ground. Pulldown on TV_R/C_OUT is on.
The output amplifier driving
VCR_R/C_OUT turns off.
COMMENTS
Mute (power-on
default)
DC restore clamp active at input (poweron default)
Mute (power-on
default)
DESCRIPTION
Set AUX Slow Switching
AUX_R/C_OUT Ground
76543210
—————— 00
—————— 01
—————— 10High impedance
—————— 11
————— 0——
————— 1——
BIT
COMMENTS
Low (<2V). Internal source (power-on
default).
Medium (4.5V to 7V). External SCART
source with 16:9 aspect ratio.
High (>9.5V). External SCART source
with 4:3 aspect ratio.
Normal operation. Pulldown on
TV_R/C_OUT is off (power-on default).
Ground. Pulldown on TV_R/C_OUT is
on. The output amplifier driving
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
68L QFN THIN.EPS
PACKAGE OUTLINE
68L QFN THIN, 10x10x0.8 MM
21-0142
PACKAGE OUTLINE
68L QFN THIN, 10x10x0.8 MM
21-0142
A
A
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