The MAX3983 is a quad copper-cable signal conditioner
that operates from 2.5Gbps to 3.2Gbps. It provides compensation for 4x copper InfiniBand and 10Gbase-CX4
Ethernet links, allowing spans of 20m with 24AWG and
15m with 28AWG. The cable driver section provides four
selectable preemphasis levels. The input to the cable
driver compensates for up to 0.5m of FR4 circuit board
material. The cable receiver section provides additional
fixed input equalization while offering selectable preemphasis to drive FR4 circuit boards up to 0.5m.
The MAX3983 also features signal detection on all eight
inputs and internal loopback that allows for diagnostic
testing. It is packaged in a 10mm x 10mm, 68-pin QFN
and operates from 0°C to +85°C.
Applications
4x InfiniBand (4 x 2.5Gbps)
10Gbase-CX4 Ethernet (4 x 3.125Gbps)
10G Fibre Channel XAUI (4 x 3.1875Gbps)
4x Copper-Cable or Backplane Transmission
(1Gbps to 3.2Gbps)
Features
♦ Link Features
Span 20m with 24AWG, 15m with 28AWG
Span 0.5m of FR4 on Each Host
1.6W Total Power with 3.3V Supply
Loopback Function
♦ Cable Driver Features
Selectable Output Preemphasis
FR4 Input Equalization
Signal Detect for Each Channel
Output Disable
♦ Cable Receiver Features
Selectable FR4 Output Preemphasis
Cable Input Equalization
Signal Detect for Each Channel
Output Disable
(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +6.0V
(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless otherwise noted.)
Note 1:Guaranteed by design and characterization.
Note 2:Measured with 2in of FR4 through InfiniBand connector with TX_PE1 = TX_PE0 =1.
Note 3:Measured at the chip using 0000011111 or equivalent pattern. TX_PE1 = TX_PE0 = 0 for minimum preemphasis.
Note 4:All channels under test are not transmitting during test. Channel tested with XAUI CJPAT, as well as this pattern: 19 zeros,
Note 5:Cables are unequalized, Amphenol Spectra-Strip 24AWG and 28AWG or equivalent equipped with Fujitsu “MicroGiga”
connector or equivalent. All other channels are quiet. Residual deterministic jitter is the difference between the source jitter and the output jitter at the load. The deterministic jitter (DJ) at the output of the transmission line must be from mediainduced loss and not from clock-source modulation. Depending upon the system environment, better results can be
achieved by selecting different preemphasis levels.
Note 6:Tested with a 1GHz sine wave applied at TX_IN under test with less than 5in of FR4.
Note 7:Measured with 3in of FR4 with RX_PE = 1.
Note 8:Measured at the chip using 0000011111 or equivalent pattern. RX_PE = low (minimum). Signal source is 1V
P-P
with 5m,
28AWG InfiniBand cable.
Note 9:All other receive channels are quiet. TX_ENABLE = 0. Channel tested with XAUI CJPAT as well as this pattern: 19 zeros,
Note 11: Tested with a 1GHz sine wave applied at RX_IN under test with less than 5in of FR4.
Note 12: Channel tested with XAUI CJPAT as well as this pattern: 19 zeros, 1, 10 zeros, 1010101010 (D21.5 character), 1100000101
Note 13: Cables are unequalized, Amphenol Spectra-Strip 24AWG or equivalent equipped with Fujitsu “MicroGiga” connector or
equivalent. Residual deterministic jitter is the difference between the source jitter at point A and the load jitter at point B in
Figure 2. The deterministic jitter (DJ) at the output of the transmission line must be from media-induced loss and not from
clock-source modulation. Depending upon the system environment, better results can be achieved by selecting different
preemphasis levels.
Note 14: Valid with pattern generator deterministic jitter as high as 0.17UI
3, 15VCC1Power-Supply Connection for TX Inputs. Connect to +3.3V.
4, 7, 10, 13
5, 8, 11, 14
6, 9, 12, 40,
43, 46
18TX_ENABLE
19N.C.No Connection. Do not connect this pin.
20, 23, 26,
29, 32
21, 24, 27,30TX_OUT1+ to
22, 25, 28,31TX_OUT1- to
33TX_PE0
34TX_PE1
TX_SD1 to
TX_SD4
TX_IN1- to
TX_IN4-
TX_IN1+ to
TX_IN4+
GNDCircuit Ground
V
CC
TX_OUT4+
TX_OUT4-
PC Board Receiver Signal Detect, TTL Output. This output is open-collector TTL, and therefore
requires an external 4.7kΩ to 10kΩ pullup resistor to V
signal level is not valid.
PC Board Receiver Negative Data Inputs, CML. These inputs are internally differentially terminated to
the corresponding TX_IN+ with 100Ω.
PC Board Receiver Positive Data Inputs, CML. These inputs are internally differentially terminated to
the corresponding TX_IN- with 100Ω.
Cable Transmitter Enable Input, LVTTL with 40kΩ Internal Pullup. This pin enables all four cable
transmitter outputs TX_OUT[1:4]. When low, differential output is less than 30mV
for normal operation.
2Power-Supply Connection for TX Outputs. Connect to +3.3V.
Cable Transmitter Positive Data Outputs, CML. These outputs are terminated with 50Ω to V
Cable Transmitter Negative Data Outputs, CML. These outputs are terminated with 50Ω to V
Cable Transmitter Preemphasis Control Input, LVTTL with 40kΩ Internal Pullup. This pin is the least
significant bit of the 2-bit preemphasis control. Set high or open to assert this bit.
Cable Transmitter Preemphasis Control Input, LVTTL with 40kΩ Internal Pullup. This pin is the most
significant bit of the 2-bit preemphasis control. Set high or open to assert this bit.
. These outputs sink current when the input
CC
. Set high or open
P-P
CC
CC
2.
2.
35, 36, 50,51RX_SD4 to
RX_SD1
37, 49VCC3Power-Supply Connection for RX Inputs. Connect to +3.3V.
38, 41, 44,47RX_IN4- to
RX_IN1-
39, 42, 45,48RX_IN4+ to
RX_IN1+
52RX_ENABLE
53POR
54, 57, 60,
63, 66
V
CC
Cable Receiver Signal Detect, TTL Output. This output is open-collector TTL, and therefore it requires
an external 4.7kΩ to 10kΩ pullup resistor to V
level is not valid.
Cable Receiver Negative Data Inputs, CML. These inputs are internally differentially terminated to the
corresponding RX_IN+ with 100Ω.
Cable Receiver Positive Data Inputs, CML. These inputs are internally differentially terminated to the
corresponding RX_IN- with 100Ω.
PC Board Transmitter Enable Input, LVTTL with 40kΩ Internal Pullup. This pin enables all four PC
board transmitter outputs RX_OUT[1:4]. When low, differential output is less than 30mV
or open for normal operation.
PC Board Transmitter Positive Data Outputs, CML. These outputs are terminated with 50Ω to V
PC Board Transmitter Negative Data Outputs, CML. These outputs are terminated with 50Ω to V
PC Board Transmitter Preemphasis Control Input, LVTTL with 40kΩ Internal Pullup. Set high or open
to assert this bit.
Loopback Enable Input, LVTTL with 40kΩ Internal Pullup. Set low for normal operation. Set high or
open for internal connection of TX_IN to RX_OUT. TX_OUT continues to transmit when loopback is
enabled.
Exposed Pad. Signal and supply ground. For optimal high-frequency performance and thermal
conductivity, this pad must be soldered to the circuit board ground.
1
V
CC
40kΩ
1
1
V
CC
40kΩ
V
3
CC
40kΩ
LVTTL
LVTTL
LVTTL
V
VCC2
V
2
CC
CML
4
CC
FIXED
EQUALIZER
2
V
CC
LIMITER
4
PRE-
EMPHASIS
SIGNAL
DETECT
CML
V
CC
POWER
MANAGEMENT
2VCC1
V
2
CC
TX_OUT[1:4]+
TX_OUT[1:4]-
TX_SD[1:4]
POR
CC
CC
4.
4.
4
V
CC
RX_OUT[1:4]+
RX_OUT[1:4]-
RX_ENABLE
RX_PE
RX_SD[1:4]
PRE-
EMPHASIS
4
V
CC
SIGNAL
DETECT
LVTTL
LVTTL
CML
V
4
CC
V
4
CC
V
3
CC
40kΩ
3
V
CC
40kΩ
1
0
LIMITER
FIXED
EQUALIZER
CML
MAX3983
3
V
CC
GND
V
3
CC
RX_IN[1:4]+
RX_IN[1:4]-
Detailed Description
The MAX3983 comprises a PC board receiver and
cable driver section (TX), as well as a cable receiver
and PC board driver section (RX). Equalization and signal detection are provided in each receiver, and preemphasis is included in each transmitter. The MAX3983
includes separate enable control for the TX outputs and
RX outputs. Loopback is provided for diagnostic testing.
PC Board Receiver and Cable Driver
(TX_IN and TX_OUT)
Data is fed into the MAX3983 from the host through a
CML input stage and fixed equalization stage. The
fixed equalizer in the PC board receiver corrects for up
to 20in of PC board loss on FR4 material. The cable driver includes four-state preemphasis to compensate for
up to 20m of 24AWG, 100Ω balanced cable. Table 1 is
provided for easy translation between preemphasis
expressions. Residual jitter of the MAX3983 is independent of up to 0.17UI
P-P
source jitter.
Cable Receiver and PC Board Driver
(RX_IN and RX_OUT)
The fixed equalizer on each RX input provides approximately 6dB equalization to correct for up to 5m of
28AWG, 100Ω balanced cable. The PC board driver
includes two-state preemphasis to compensate for up
to 20in of FR4 material.
Signal-Detect Outputs
Signal detect (SD) is provided on all eight data inputs.
Pullup resistors should be connected from the SD outputs to a supply in the 3.0V to 5.5V range. The signaldetect outputs are not valid until power-up is complete.
Typical signal-detect response time is 0.35µs.
In the RX section, the SD output asserts high when the
RX_IN signal amplitude is greater than 175mV
P-P
.
RX_SD deasserts low when the RX_IN signal amplitude
drops below 85mV
P-P
.
In the TX section, the SD output asserts high when the
TX_IN signal amplitude is greater than 800mV
P-P
.
TX_SD deasserts low when the TX_IN signal amplitude
drops below 200mV
P-P
.
TX and RX Enable
The TX_ENABLE and RX_ENABLE pins enable TX and
RX, respectively. Typical enable time is 15ns, and typical disable time is 25ns. The enable inputs may be
connected to signal-detect outputs to automatically
detect an incoming signal (see the Autodetect section).
Power-On Reset
To limit inrush current, the MAX3983 includes internal
power-on reset circuitry. Connect a capacitor 0.1µF ≤
C
If all four RX or TX signal-detect outputs are to be connected together to form one signal detect, the leakage
current of the output stage needs to be considered.
Each SD output sinks a maximum of 25µA when asserted, so when four are connected together, a maximum of
100µA is possible. The value of the pullup resistor connected to pullup voltage V
PULLUP
should be selected so
the leakage current does not cause the output voltage to
fall below the threshold of the next stage. For example, if
the signal-detect outputs are connected together and to
a stage with a logic-high threshold of 1.5V, the pullup
resistor needs to be chosen so V
PULLUP
- I
LEAKAGE
x
R
PULLUP
> 1.5V. In this case, if V
PULLUP
= 3.0V,
R
PULLUP
should be less than 15kΩ.
Autodetect
The MAX3983 can automatically detect an incoming signal and enable the appropriate outputs. Autodetect of
the RX side is done by connecting RX_SD[1:4] together
with a pullup resistor (value 4.7kΩ to 10kΩ to VCC) to
RX_ENABLE. For the TX side, this is done by connecting
TX_SD[1:4] together with a pullup resistor (value 4.7kΩ
to 10kΩ to VCC) to TX_ENABLE (Figure 4). If signal is
detected on all channels, SD is high and forces the corresponding ENABLE high. Leaving the inputs to the
MAX3983 open (i.e., floating) is not recommended, as
noise amplification can occur and create undesirable
output signals. Autodetect is recommended to eliminate
noise amplification or possible oscillation. When using
autodetect, the link length is determined by the received
signal strength. It is possible to reach longer distances if
the autodetect configuration is not used.
Using Loopback with Autodetect
If the MAX3983 is configured for autodetection,
RX_ENABLE is controlled by the RX_SD[1:4] outputs.
Since loopback requires RX_ENABLE to be high, a simple OR gate can be used to enable the RX outputs
when either RX_SD[1:4] is high or when LOOPBACK is
high (Figure 5).
InfiniBand and 10Gbase-CX4 Transition
Time Specification
InfiniBand specifies a minimum transition time (20% to
80%) of 100ps and CX4 specifies a minimum of 60ps.
Both are specified at the connector interface to the
cable. The output transition times of the MAX3983 are
45ps (typ) and therefore require some care to increase
this time. Approximately 3in of FR4 with 4-mil-wide lines
is sufficient to lengthen the transition time to 60ps. For
100ps transition times, additional length can be used or
an additional 1.5pF capacitor can be placed across the
outputs of the MAX3983. Do not use high-speed dielectric material for the circuit board if the application
requires the use of the InfiniBand or CX4 type connector
system. With such materials, the fast edges of the
Figure 4. Autodetection Using Corresponding Signal-Detect
Outputs and Enable Input
Figure 5. Loopback in Autodetect Mode
3.0V ≤ V
RX OR TX_SD1
MAX3983
RX OR TX_SD2
RX OR TX_SD3
RX OR TX_SD4
RX OR TX_ENABLE
≤ 5.5V
PULLUP
4.7kΩ≤ R ≤ 10kΩ
RX_SD1
MAX3983
RX_SD2
RX_SD3
RX_SD4
RX_ENABLE
LOOPBACK
3.0V ≤ V
≤ 5.5V
PULLUP
4.7kΩ≤ R ≤ 10kΩ
TO HOST
MAX3983 will produce excessive crosstalk in InfiniBand
and CX4 cable assemblies.
Crosstalk
For InfiniBand and 10Gbase-CX4 applications, it is
imperative to know the near-end crosstalk characteristics
of the cable assemblies. 10Gbase-CX4 has defined the
upper limit over frequency for near-end crosstalk (NEXT)
with single and multiple aggressors. InfiniBand has only
specified a percentage as measured in the time domain
relative to the transmitter output. Regardless of the specification method, NEXT is a critical component of the link
performance. When using larger amounts of preemphasis, the received eye height is small and vulnerable to
NEXT. For those situations requiring a large transmit preemphasis, the NEXT should be less than -30dB at frequencies from 1GHz to 3GHz. It should be noted that
cables that meet the 10Gbase-CX4 NEXT and MDNEXT
should provide adequate isolation.
Layout Considerations
Circuit board layout and design can significantly affect
the performance of the MAX3983. Use good high-frequency design techniques, including minimizing
ground inductance and using controlled-impedance
transmission lines on the data signals. Power-supply
decoupling should also be placed as close to the V
CC
pins as possible. There should be sufficient supply filtering. Always connect all V
CC
s to a power plane. Take
care to isolate the input from the output signals to
reduce feedthrough. The performance of the equalizer
is optimized for lossy environments. For best results,
use board material with a dielectric tangential loss of
approximately 0.02 and 4-mil-wide transmission lines.
High-speed materials with tangential loss of less than
0.01 can be used, but require special care to reduce
near-end crosstalk in cable assemblies.
Exposed-Pad Package
The exposed-pad, 68-pin QFN package incorporates
features that provide a very low thermal resistance path
for heat removal from the IC. The pad is electrical
ground on the MAX3983 and must be soldered to the
circuit board for proper thermal and electrical performance. For more information on exposed-pad packages, refer to Maxim Application Note HFAN-08.1:
Thermal Considerations of QFN and Other ExposedPaddle Packages.
*THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND
FOR PROPER THERMAL AND ELECTRICAL OPERATION OF THE MAX3983.
MAX3983
Quad Copper-Cable Signal Conditioner
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
68L QFN.EPS
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
21-0122
C
C
1
2
1
2
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