Rainbow Electronics MAX3942 User Manual

General Description

The MAX3942 is designed to drive high-speed optical
modulators at data rates up to 10.7Gbps. It functions as
a modulation circuit, with an integrated control op amp
externally programmed by a DC voltage.

A high-bandwidth, fully differential signal path is internally
implemented to minimize jitter accumulation. When a
clock signal is available, the integrated data-retiming
function can be selected to reject input-signal jitter.

The MAX3942 receives differential CML signals (ground­referenced) with on-chip line terminations of 50Ω. Each
of the differential outputs has an on-chip 50Ω resistor for
back termination. The driver is able to deliver a modula­tion current of 40mA

P-P

to 120mA

P-P

, with an edge
speed of 23ps (typical 20% to 80%). This modulation cur­rent reflects a modulation voltage of 1.0V

P-P

to 3.0V

P-P

single ended or 2.0V

P-P

to 6.0V

P-P

differential.

The MAX3942 also includes an adjustable pulse-width
control circuit to precompensate for asymmetrical mod­ulator characteristics. It is available in a compact 4mm

✕ 4mm, 24-pin thin QFN package and operates over

the -40°C to +85°C temperature range.

Features

♦ 23ps Edge Speed

♦ Single-Ended Modulation Voltage Up to 3V

P-P

♦ Differential Modulation Voltage Up to 6V

P-P

♦ Selectable Data-Retiming Latch

♦ Up to 10.7Gbps Operation

♦ 50Ω On-Chip Input and Output Terminations

♦ Pulse-Width Adjustment

♦ Enable and Polarity Controls

♦ ESD Protection

Applications

Mach Zehnder Modulators

Packaged Direct-Modulated Lasers

SONET OC-192 and SDH STM-64 Transmission
Systems

DWDM Systems

Long/Short-Reach Optical Transmitters

10Gbps Ethernet

MAX3942

10Gbps Modulator Driver

________________________________________________________________ Maxim Integrated Products 1

Typical Application Circuit

19-2934; Rev 0; 7/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

Pin Configuration appears at end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX3942ETG -40°C to +85°C 24 Thin QFN (4mm

✕ 4mm)

L2

L1

1000pF

50Ω

50Ω

0.01µF

0.01µF

0.1µF

50Ω

MACH ZEHNDER

MODULATOR

50Ω

-5.2V

-5.2V

MODEN

MAX3942

MODSET

V

RTEN

+

MODSET

-

OUT-

OUT+

EE

-5.2V

0.01µF

DATA+ DATA+

MAX3952

10Gbps

SERIALIZER

0.01µF

DATA- DATA-

0.01µF

CLK+ CLK+

0.01µF

CLK- CLK-

PLRT GND

50Ω

50Ω

50Ω

50Ω

PWC+ PWC- V

2kΩ

-5.2V

L1 AND L2 ARE HIGH-FREQUENCY FERRITE BEADS

REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE.

MAX3942

10Gbps Modulator Driver

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage V

EE

..............................................-6.0V to +0.5V

Voltage at MODEN,

RTEN, PLRT, MODSET............................(V

EE

- 0.5V) to +0.5V
Voltage at DATA+, DATA-, CLK+, and CLK-……-1.65V to +0.5V

Voltage at OUT+, OUT- ................................……….-4V to +0.5V

Voltage at PWC+, PWC- ...................(V

EE

- 0.5V) to (VEE+ 1.7V)

Continuous Power Dissipation (T

A

= +85°C)

24-Pin Thin QFN (derate 20.8mW/° above +85°C) ....1354mW

Current into or out of OUT+, OUT-.................……………...80mA

Storage Temperature Range .....................……-55°C to +150°C

Operating Temperature Range ....................……-40°C to +85°C

Lead Temperature (soldering, 10s)............………………+300°C

ELECTRICAL CHARACTERISTICS

(VEE= -5.5V to -4.9V, TA= -40°C to +85°C. Typical values are at VEE= -5.2V, I

MOD

= 100mA, and TA= +25°C, unless otherwise noted.)

Power-Supply Voltage V

Supply Current I

Power-Supply Noise Rejection PSNR f ≤ 2MHz (Note 2); see Figure 3 15 dB

SIGNAL INPUT (Note 3)

Input Data Rates NRZ 10.7 Gbps

Single-Ended Input Resistance R

Single-Ended Input Voltage V

Differential Input Voltage V

Differential Input Return Loss RL

MODULATION (Note 5)

Maximum Modulation Current 112 120 mA

Minimum Modulation Current V

MODSET Voltage Range V

E q ui val ent M od ul ati on Resi stance R

Modulation Set Bandwidth Modulation depth 10%, 50Ω driver load 5 MHz

MODSET Input Resistance 20 kΩ

Modulation-Current Temperature
Stability

Modulation-Current-Setting Error 50Ω driver load, TA = +25°C -10 +10 %

Output Resistance R

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

EE

EE

IN

IS

ID

IN

MODSET

MODEQV

OUT

Excluding I
(Note 1)

Input to GND 42.5 50 58.5 Ω

DC-coupled, Figure 1a -1 0

AC-coupled, Figure 1b -0.4 +0.4

DC-coupled (Note 4) 0.2 2.0

AC-coupled (Note 4) 0.2 1.6

≤ 15GHz 15 dB

MODSET

(Note 7) 11.1 Ω

(Note 6) -980 0 ppm/°C

OUT+ and OUT- to GND 42.5 50 58.5 Ω

MOD

= V

-5.5 -4.9 V

Retime disabled 125 175

Retime enabled 140 200

EE

V

EE

37 40 mA

VEE + 1 V

mA

V

V

P-P

P-P

P-P

MAX3942

10Gbps Modulator Driver

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VEE= -5.5V to -4.9V, TA= -40°C to +85°C. Typical values are at VEE= -5.2V, I

MOD

= 100mA, and TA= +25°C, unless otherwise noted.)

Note 1: Supply current remains elevated once the retiming function has been enabled. Power must be cycled to reduce supply

current after the retiming function has been disabled.

Note 2: Power-supply noise rejection is specified as PSNR = 20Log(V

noise (on Vcc)

/ ∆V

OUT

). V

OUT

is the voltage across a 50Ω load.

V

noise (on Vcc)

= 100mV

P-P

.

Note 3: For DATA+, DATA-, CLK+, and CLK-.
Note 4: CLK input characterized at 10.7Gbps.
Note 5: Minimum voltage on OUT+ and OUT- is V

EE

+ 1.9V.

Note 6: Guaranteed by design and characterization using the circuit shown in Figure 3.
Note 7: R

MODEQV

= (V

MODSET

- VEE) / (I

MOD

- 37mA).

Note 8: 50Ω load, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern.
Note 9: Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter).

Measured with a 10.7Gbps 2

7

- 1 PRBS pattern with 80 zeros and 80 ones inserted in the data pattern.

Note 10: For MODEN and PLRT.

Off Current

Differential Output Return Loss RL

Output Edge Speed 20% to 80% (Notes 6, 8) 23 32 ps

Setup/Hold Time tSU, t

Pulse-Width Adjustment Range (Notes 6, 8) ±30 ±50 ps

Pulse-Width Control Input Range
(Single Ended)

Pulse-Width Control Input Range
(Differential)

Output Overshoot δ (Notes 6, 8) 5 %

Driver Random Jitter RJ

Driver Deterministic Jitter DJ

CONTROL INPUTS

Input High Voltage V

Input Low Voltage V

Input Current (Note 10) -80 +200 µA

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MODEN = V
high, DATA- = low

OUTIMOD

HD

DR

DR

IH

IL

= 50mA ≤ 10GHz 10 dB

Figure 2 (Note 6) 25 ps

For PWC+ and PWC-

(PWC+) - (PWC-) -0.5 +0.5 V

(Note 6) 0.3 0.8 ps

PWC- = GND (Notes 6, 9) 8 13 ps

(Note 10)

(Note 10)

, MODSET = VEE, DATA+ =

EE

1.6 mA

VEE +

0.5

V

EE

2.0

+

VEE +

1.5

V

EE

0.8

+

V

RMS

P-P

V

V

MAX3942

10Gbps Modulator Driver

4 _______________________________________________________________________________________

Figure 1. Definition of Single-Ended Input Voltage Range

Figure 2. Setup and Hold Timing Definition

Test Circuits and Timing Diagrams

0V

-0.5V

-1.0V
(a) DC-COUPLED SINGLE-ENDED CML INPUT

0.4V

0V

-0.4V
(b) AC-COUPLED SINGLE-ENDED (CML OR PECL) INPUT

CLK+

CLK-

DATA-

t

SU

100mV

1.0V

800mV

t

HD

100mV

VIS = 0.1V

P-P

DC-COUPLED

TO 0.8V

0.1V

P-P

AC-COUPLED

TO 1V

P-P

P-P

DATA+

= 0.2V

TO 1.6V

P-P

= 40mA

P-P

TO 2V

P-P

TO 120mA

P-P

P-P

P-P

(DATA+) - (DATA-)

NOTE: I

I

OUT+

I

OUT-

OUT+

AND I

RELATE TO RETIMED DATA. SEE FIGURE 3 FOR POLARITY.

OUT-

V

ID

DC-COUPLED

0.2V
AC-COUPLED

I

MOD

MAX3942

10Gbps Modulator Driver

_______________________________________________________________________________________ 5

Figure 3. AC Characterization Circuit

Test Circuits and Timing Diagrams (continued)

PATTERN

GENERATOR

-5.2V

50Ω

50Ω

50Ω

50Ω

0.1µF

RTEN

PLRT PWC+ PWC-

CLK+

CLK-

DATA+

DATA-

V

EE

1000pF

V

MODSET

MODEN

MAX3942

V

EE

OUT-

OUT+

GNDMODSET

I

OUT-

I

OUT+

50Ω

50Ω

OSCILLOSCOPE

50Ω

Z

L

MAX3942

10Gbps Modulator Driver

6 _______________________________________________________________________________________

Typical Operating Characteristics

(Typical values are at VEE= -5.2V, I

MOD

= 100mA, TA= +25°C, unless otherwise noted.)

10.7Gbps ELECTRICAL EYE DIAGRAM

(V

MOD

= 2V

P-P

DIFFERENTIAL, 2

31

- 1 PRBS)

MAX3942 toc01

16ps/div

10.7Gbps ELECTRICAL EYE DIAGRAM

(V

MOD

= 6V

P-P

DIFFERENTIAL, 2

31

- 1 PRBS)

MAX3942 toc02

16ps/div

SUPPLY CURRENT vs. TEMPERATURE

(50Ω LOAD, EXCLUDES I

MOD

)

MAX3942 toc03

TEMPERATURE (°C)

I

EE

(mA)

80706050403020100-10-20-30

110

120

130

140

150

160

170

100

-40 90

RETIMING ENABLED

RETIMING DISABLED

PULSE WIDTH vs. R

PWC

MAX3942 toc04

R

PWC-

(Ω)

PULSE-WIDTH POSITIVE PULSE (ps)

2505001000 7501500 12501750

760

770

780

790

800

810

820

830

840

850

750

2000 0

R

PWC+

(Ω)

175015001000 1250500 7502500 2000

MEASURED AT 1.25Gbps
WITH A 1010 PATTERN

0

0.6

0.4

0.2

1.0

0.8

1.8

1.6

1.4

1.2

2.0

-50 -30 -10 10 30 50 70 90

PULSE-WIDTH DISTORTION

vs. TEMPERATURE

MAX3942 toc05

TEMPERATURE (°C)

PULSE-WIDTH DISTORTION (ps)

DIFFERENTIAL S22 vs. FREQUENCY

(DEVICE POWERED)

MAX3942 toc09

FREQUENCY (GHz)

|S

22

| (dB)

12963

-27

-24

-21

-18

-15

-12

-9

-6

-3

0

-30
015

0

1

10

10k

POWER-SUPPLY NOISE REJECTION

vs. FREQUENCY

10

5

15

25

20

30

MAX3942 toc07

FREQUENCY (Hz)

PSNR (dB)

100 1k

DIFFERENTIAL V

(ZL = 50Ω ON OUT+ AND OUT-)

7

V

IS RELATIVE TO V

MODSET

6

)

P-P

5

(V

MOD

4

3

2

DIFFERENTIAL V

1

0

0 1.00

DIFFERENTIAL S11 vs. FREQUENCY

(DEVICE POWERED)

0

-5

-10

-15

I (dB)

-20

11

IS

-25

-30

-35

-40
015

FREQUENCY (GHz)

1293 6

MAX3942 toc08

V

MODSET

MOD

EE

(V)

vs. V

MODSET

MAX3942 toc06

0.750.500.25

MAX3942

10Gbps Modulator Driver

_______________________________________________________________________________________ 7

Detailed Description

The MAX3942 modulator driver accepts differential
clock and data inputs that are compatible with PECL
and CML logic levels.

The modulation output stage is composed of a high­speed differential pair and a programmable current
source with a maximum modulation current of 120mA.
The rise and fall times are typically 23ps. The modulation
current is designed to produce a modulation voltage up
to 3.0V

P-P

single endedly, or 6.0V

P-P

differentially when

driving a 50Ω module. The 3.0V

P-P

results from 120mA

P-P

through the parallel combination of the 50Ω modulator
load and the internal 50Ω back termination.

Polarity Switch

The MAX3942 includes a polarity switch. When the
PLRT pin is high or left floating, the outputs maintain the
polarity of the input data. When the PLRT pin is low, the
outputs are inverted relative to the input data.

Clock/Data Input Logic Levels

The MAX3942 is directly compatible with ground-refer­ence CML. Either DC- or AC-coupling may be used for
CML referenced to ground. For all other logic types,
AC-coupling should be used.

Optional Data Input Latch

To reject pattern-dependent jitter in the input data, a syn­chronous differential clock signal should be connected to
the CLK+ and CLK- inputs, and the RTEN control input
should be connected to V

EE

.

Pin Description

PIN NAME FUNCTION

1 DATA+ Noninverting Data Input, with 50Ω On-Chip Termination

2 DATA- Inverting Data Input, with 50Ω On-Chip Termination

3, 4, 14, 17 GND Ground. All pins must be connected to board ground.

5 CLK+ Noninverting Clock Input for Data Retiming, with 50Ω On-Chip Termination

6 CLK- Inverting Clock Input for Data Retiming, with 50Ω On-Chip Termination

7, 11, 12, 13,

18, 19, 21, 24

8 PWC+ Positive Input for Modulation Pulse-Width Adjustment (see the Design Procedure section).

9 PWC-

10 MODSET Modulation Current Set. Apply a voltage to set the modulation current of the driver output.

15 OUT-

16 OUT+

20 PLRT

22 MODEN

23 RTEN Data-Retiming Input. Connect to VEE for retimed data. Connect to GND to bypass retiming latch.

EP

V

EE

Exposed

Pad

Negative Supply Voltage. All pins must be connected to board VEE.

Negative Input for Modulation Pulse-Width Adjustment. Ground to disable the pulse-width
adjustment feature (see the Design Procedure section).

Inverting Driver Output. Provides modulation output with 50Ω back termination. Sinks current when
PLRT is high and when differential data is high.

Noninverting Driver Output. Provides modulation output with 50Ω back termination. Sinks current
when PLRT is high and when differential data is low.

Differential Data Polarity Swap Input. Set high or float for normal operation. Set low to invert the
differential signal polarity. Contains an internal 100kΩ pullup to GND.

TTL/CMOS Modulation Enable Input. Set low or float for normal operation. Set high to put the EAM
in the absorption (logic 0) state. Contains an internal 100kΩ pulldown to V

Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance.
See the Layout Considerations section.

EE

.

MAX3942

10Gbps Modulator Driver

8 _______________________________________________________________________________________

The input data is retimed on the rising edge of CLK+. If
RTEN is connected to ground, the retiming function is dis­abled and the input data is directly connected to the out­put stage. Leave CLK+ and CLK- open when retiming is
disabled.

Pulse-Width Control

The pulse-width control circuit can be used to compen­sate for pulse-width distortion introduced by the modu­lator. The differential voltage between PWC+ and PWC­adjusts the pulse-width compensation. The adjustment
range is typically ±50ps. Optional single-ended opera­tion is possible by forcing a voltage on the PWC+ pin
while leaving the PWC- pin unconnected. When PWC­is connected to ground, the pulse-width control circuit
is automatically disabled.

Modulation Output Enable

The MAX3942 incorporates a modulation current­enable input. When MODEN is low or floating, the mod­ulation outputs OUT+ and OUT- are enabled. When
MODEN is high, the drive current is switched to OUT+.
The typical enable time is 2ns and the typical disable
time is 2ns.

Design Procedure

Programming the Modulation Voltage

The modulation voltage results from I

MOD

passing

through the load impedance (ZL) in parallel with the
internal 50Ω termination resistor (R

OUT

):

To program the desired modulation current, force a
voltage at the MODSET pin (see the Typical Application
Circuit). The resulting I

MOD

current can be calculated

by the following equation:

An internal, independent current source drives a constant
37mA to the modulation circuitry and any voltage above
V

EE

on the MODSET pin adds to this. The input imped-

ance of the MODSET pin is typically 20kΩ. Note that the
minimum output voltage is VEE+ 1.9V.

Programming the Pulse-Width Control

Three methods of control are possible when pulse predis­tortion is desired to minimize distortion at the receiver.
The pulse width may be set with a 2kΩ potentiometer with
the center tapped to VEE(or equivalent fixed resistors), or
by applying a voltage to the PWC+ pin, or by applying a
differential voltage across the PWC+ and PWC- pins. See
Table 1 for the desired effect of the pulse-width setting.
Pulse width is defined as (positive pulse width)/((positive
pulse width + negative pulse width)/2).

Input Termination Requirement

The MAX3942 data and clock inputs are CML compati­ble. However, it is not necessary to drive the IC with a
standard CML signal. As long as the specified input volt­age swings are met, the MAX3942 operates properly.

Applications Information

Layout Considerations

To minimize loss and crosstalk, keep the connections
between the MAX3942 output and the modulator as
short as possible. Use good high-frequency layout
techniques and multilayer boards with an uninterrupted
ground plane to minimize EMI and crosstalk. Circuit
boards should be made using low-loss dielectrics. Use
controlled-impedance lines for the clock and data
inputs, as well as for the data output.

Table 1. Pulse-Width Control

(

)

VI

≈×

MOD MOD

ZR

L OUT

ZR

L OUT

×

+

PULSE
WIDTH

(%)

R

R

PWC+

PWC+

, R

+ R

PWC­PWC-

FOR

= 2kΩ

V

PWC- OPEN

PWC+

(V)

V

PWC+

V

-

PWC-

(V)

V

I

MOD

MODSET

≈+

11.1

37mA

Ω

100 R

>100 R

<100 R

PWC+

PWC+

PWC+

= R

> R

< R

PWC-

PWC-

PWC-

VEE + 1 0

> VEE + 1 >0

< VEE + 1 <0

MAX3942

10Gbps Modulator Driver

_______________________________________________________________________________________ 9

Interface Schematics

Figures 5 and 6 show simplified input and output cir­cuits of the MAX3942 modulator driver.

To minimize inductance, keep the connections from
OUT, GND, and VEEas short as possible. This is crucial
for optimal performance.

Laser Safety and IEC 825

Using the MAX3942 EAM driver alone does not ensure
that a transmitter design is compliant with IEC 825. The
entire transmitter circuit and component selections must
be considered. Each customer must determine the level
of fault tolerance required by their application, recogniz­ing that Maxim products are not designed or authorized
for use as components in systems intended for surgical
implant into the body, for applications intended to sup­port or sustain life, or for any other application where the
failure of a Maxim product could create a situation where
personal injury or death may occur.

Figure 5. Simplified Input Circuit

Figure 4. Functional Diagram

CLK+

CLK-

50Ω 50Ω

MODENRTEN PLRT

V

EE

50Ω

50Ω 50Ω

50Ω

OUT-

OUT+

DQ

DATA+

DATA-

50Ω 50Ω

0

MUX

1

PWC

PWC+ PWC-

2kΩ

V

EE

POLARITY

MAX3942

DATA+/CLK+

I

MOD

+

V

MODSET

V

MODSET

-

EE

V

EE

GND

50

Ω

50

Ω

MAX3942

DATA-/CLK-

V

EE

MAX3942

10Gbps Modulator Driver

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information

For the latest package outline information, go to

www.maxim-ic.com/packages

.

Exposed-Pad Package

The exposed pad on the 24-pin QFN provides a very
low thermal resistance path for heat removal from the
IC. The pad is also electrical ground on the MAX3942
and must be soldered to the circuit board ground for
proper thermal and electrical performance. Refer to
Maxim Application Note HFAN-08.1: Thermal

Considerations for QFN and Other Exposed-Pad
Packages for additional information.

Figure 6. Simplified Output Circuit

Chip Information

TRANSISTOR COUNT: 1918

PROCESS: SiGe Bipolar

Pin Configuration

GND

OUT-

V

EE

TOP VIEW

VEERTEN

24

GND GND

MAX3942

50Ω 50Ω

EE

MODEN

V

23

22

21

PLRT

20

EE

V

19

GND

OUT+

V

EE

DATA+

DATA-

GND

GND

CLK+

CLK-

1

2

3

4

5

6

MAX3942

7

8

9

10

EE.

V

PWC+

PWC-

MODSET

18

V

EE

17

GND

16

OUT+

15

OUT-

14

GND

V

13

EE

11

12

EE

EE

V

V

PART PACKAGE TYPE PACKAGE CODE

MAX3942ETG

24 Thin QFN

(4mm

✕ 4mm ✕ 0.8mm)

T2444-1

24 THIN QFN (4mm x 4mm)

EXPOSED PAD CONNECTED TO GROUND